coreboot March 2011

coreboot@coreboot.org

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210 discussions

correct 'power_on_after_fail' setting
by Josef Kellermann 09 Mar '11

09 Mar '11

Hi, bit 0 of pm reg#74 have to be set turn on system after power resumes. See '42661_sb600_rrg_nda_3.02.pdf' for detail. Signed-off-by: Josef Kellermann <seppk(a)arcor.de> <mailto://seppk@arcor.de>

1 0

[commit] r6439 - in trunk/src: mainboard/amd/bimini_fam10 mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/amd/tilapia_fam10 mainboard/asus/m4a78-em mainboard/asus/m4a78...
by repository service 08 Mar '11

08 Mar '11

Author: sduplichan Date: Wed Mar 9 00:01:46 2011 New Revision: 6439 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6439 Log: Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...(a)notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asus/m4a78-em/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdht/ht_wrapper.c Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -237,3 +237,34 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + + return 0; +} Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -232,3 +232,34 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + + return 0; +} Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -337,3 +337,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -231,3 +231,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/asus/m4a78-em/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a78-em/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/asus/m4a78-em/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -232,3 +232,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -232,3 +232,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -228,3 +228,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -230,3 +230,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -222,3 +222,37 @@ post_cache_as_ram(); } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -233,3 +233,34 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + + return 0; +} Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -238,3 +238,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -253,3 +253,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -246,3 +246,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 post_code(0x42); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -295,3 +295,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Mar 9 00:01:46 2011 (r6439) @@ -250,3 +250,37 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + +/** + * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) + * Description: + * This routine is called every time a non-coherent chain is processed. + * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a + * swap list. The first part of the list controls the BUID assignment and the + * second part of the list provides the device to device linking. Device orientation + * can be detected automatically, or explicitly. See documentation for more details. + * + * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially + * based on each device's unit count. + * + * Parameters: + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain + * @param[out] u8** list = supply a pointer to a list + * @param[out] BOOL result = true to use a manual list + * false to initialize the link automatically + */ +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + /* If the BUID was adjusted in early_ht we need to do the manual override */ + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { + printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + } + + return 0; +} Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Wed Mar 9 00:01:46 2011 (r6439) @@ -1199,4 +1199,7 @@ u8 get_sbbusn(u8 sblk); #endif +#include "northbridge/amd/amdht/porting.h" +BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); + #endif /* AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c ============================================================================== --- trunk/src/northbridge/amd/amdht/ht_wrapper.c Tue Mar 8 21:49:18 2011 (r6438) +++ trunk/src/northbridge/amd/amdht/ht_wrapper.c Wed Mar 9 00:01:46 2011 (r6439) @@ -97,42 +97,6 @@ } - -/** - * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) - * Description: - * This routine is called every time a non-coherent chain is processed. - * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a - * swap list. The first part of the list controls the BUID assignment and the - * second part of the list provides the device to device linking. Device orientation - * can be detected automatically, or explicitly. See documentation for more details. - * - * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially - * based on each device's unit count. - * - * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically - */ -static BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) -{ - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; - /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { - printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); - if ((node == 0) && (link == 0)) { /* BSP SB link */ - *List = swaplist; - return 1; - } - } - - return 0; -} - - /** * void getAmdTopolist(u8 ***p) *

1 0

[PATCH]Fix option_table.h issues
by Georgi, Patrick 08 Mar '11

08 Mar '11

Hi, attached patch makes option_table.h a dependency for all romstage/ramstage files built from C, forcing the build system to create option_table.h earlier in the build. This should fix the build issues that were seen by Jonathan, Josef, and others. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

3 2

[commit] r6438 - in trunk: . src/pc80
by repository service 08 Mar '11

08 Mar '11

Author: oxygene Date: Tue Mar 8 21:49:18 2011 New Revision: 6438 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6438 Log: Add option_table.h as dependency for all C based object files if option tables are used. This is to make sure that the file exists when it is needed. While this isn't the case for every C source file, it doesn't hurt either to create the file a bit sooner than strictly necessary. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/Makefile trunk/Makefile.inc trunk/src/pc80/Makefile.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Mar 8 13:58:16 2011 (r6437) +++ trunk/Makefile Tue Mar 8 21:49:18 2011 (r6438) @@ -207,9 +207,10 @@ # $1 obj class # $2 source suffix (c, S) # $3 additional compiler flags +# $4 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template -$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h +$(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC) $(3) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$< en$(EMPTY)def @@ -219,7 +220,7 @@ filetypes-of-class=$(subst .,,$(sort $(suffix $($(1)-srcs)))) $(foreach class,$(classes), \ $(foreach type,$(call filetypes-of-class,$(class)), \ - $(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts))))) + $(eval $(call create_cc_template,$(class),$(type),$($(class)-$(type)-ccopts),$($(class)-$(type)-deps))))) foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Tue Mar 8 13:58:16 2011 (r6437) +++ trunk/Makefile.inc Tue Mar 8 21:49:18 2011 (r6438) @@ -54,6 +54,9 @@ romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__ driver-S-ccopts:=-DASSEMBLY +ramstage-c-deps:=$$(OPTION_TABLE_H) +romstage-c-deps:=$$(OPTION_TABLE_H) + ####################################################################### # Add handler to compile ACPI's ASL define ramstage-objs_asl_template @@ -174,7 +177,7 @@ @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< -$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h +$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Tue Mar 8 13:58:16 2011 (r6437) +++ trunk/src/pc80/Makefile.inc Tue Mar 8 21:49:18 2011 (r6438) @@ -7,9 +7,6 @@ romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c subdirs-y += vga -$(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H) -$(obj)/pc80/mc146818rtc_early.romstage.o : $(OPTION_TABLE_H) - cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE) cmos.default-type = 0xaa

1 0

self modifying code in intel vga bios?
by cinap_lenrek＠gmx.de 08 Mar '11

08 Mar '11

Fish- has catched this on a Intel(r)915GM/910ML/915MS Graphics Controller with realemu: bad mem write c0c11 bad memory access 1d17b0 4a008800 00000002 00000000 0000a002 00009000 00005108 ac007bda 00007bc0 0000 0000 0000 c000 csZoPdI 61ed c6 MOV CS:[c11], $01 question to the coreboot guys: did you ever see the bios writing in the rom area? i found this quote on: http://www.coreboot.org/VGA_support "Even if your VGA BIOS uses self-modifying code you get a correct image" i know that the rom area is usualy cached in ram but to catch mistakes i disallow writing to the rom area... fish will make full traces later this day... it could be just a screwup on my side... just curious :) -- cinap

3 2

RFC: Make ec/acpi ports configurable
by Sven Schnelle 08 Mar '11

08 Mar '11

Hi List, the Lenovo Embedded Controller contains 2 register pairs for ACPI: the default 0x62/0x66 pair, and a 0x1600/0x1604 pair, which is intended to be used by SMM code. While the current code works with the 0x62/0x66 pair (which is fine because there are no SMM users right now), we might switch to 0x1600/0x1604 for later versions where the SMM code actually uses the EC. So i thought about using the sconfig 'register' keyword for specifying the Register pair. If it is not given in devicetree.cb, the default ACPI addresses will be used. I've attached a short patch as an example to this mail (i have not tried if it works - it is just for discussion). One question is if we should use global static variables for the register addresses, or pass struct ec_acpi_config * to all functions? And we may think about renaming the 'register' keyword to something like 'config', as this describes better what it does. Regards, Sven. >From 9a3d656d19849bf842b0f2e1e3a86ee6b0d5a77a Mon Sep 17 00:00:00 2001 From: Sven Schnelle <svens(a)stackframe.org> Date: Tue, 8 Mar 2011 16:43:28 +0100 Subject: [PATCH] ec/acpi: make ACPI register pair configurable To: coreboot(a)coreboot.org Cc: svens(a)stackframe.org, svens(a)stackframe.org Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/acpi/chip.h | 31 +++++++++++++++++++++++++++++++ src/ec/acpi/ec.c | 30 +++++++++++++++++++++++------- src/mainboard/lenovo/x60/devicetree.cb | 2 ++ 3 files changed, 56 insertions(+), 7 deletions(-) create mode 100644 src/ec/acpi/chip.h diff --git a/src/ec/acpi/chip.h b/src/ec/acpi/chip.h new file mode 100644 index 0000000..b0d1121 --- /dev/null +++ b/src/ec/acpi/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_ACPI_CHIP_H +#define EC_ACPI_CHIP_H + +extern struct chip_operations ec_acpi_ops; + +struct ec_acpi_config { + int cmd_reg; + int data_reg; +}; + +#endif diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 7a01b7e..80d5056 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -24,13 +24,17 @@ #include <arch/io.h> #include <delay.h> #include "ec.h" +#include "chip.h" + +static int ec_cmd_reg = EC_SC; +static int ec_data_reg = EC_DATA; int send_ec_command(u8 command) { int timeout; timeout = 0x7ff; - while ((inb(EC_SC) & EC_IBF) && --timeout) { + while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { udelay(10); if ((timeout & 0xff) == 0) printk(BIOS_SPEW, "."); @@ -41,7 +45,7 @@ int send_ec_command(u8 command) // return -1; } - outb(command, EC_SC); + outb(command, ec_cmd_reg); return 0; } @@ -50,7 +54,7 @@ int send_ec_data(u8 data) int timeout; timeout = 0x7ff; - while ((inb(EC_SC) & EC_IBF) && --timeout) { // wait for IBF = 0 + while ((inb(ec_cmd_reg) & EC_IBF) && --timeout) { // wait for IBF = 0 udelay(10); if ((timeout & 0xff) == 0) printk(BIOS_SPEW, "."); @@ -61,14 +65,14 @@ int send_ec_data(u8 data) // return -1; } - outb(data, EC_DATA); + outb(data, ec_data_reg); return 0; } int send_ec_data_nowait(u8 data) { - outb(data, EC_DATA); + outb(data, ec_data_reg); return 0; } @@ -80,7 +84,7 @@ u8 recv_ec_data(void) timeout = 0x7fff; while (--timeout) { // Wait for OBF = 1 - if (inb(EC_SC) & EC_OBF) { + if (inb(ec_cmd_reg) & EC_OBF) { break; } udelay(10); @@ -92,7 +96,7 @@ u8 recv_ec_data(void) // return -1; } - data = inb(EC_DATA); + data = inb(ec_data_reg); printk(BIOS_DEBUG, "recv_ec_data: 0x%02x\n", data); return data; @@ -113,6 +117,18 @@ int ec_write(u8 addr, u8 data) return send_ec_data(data); } +static void ec_acpi_init(device_t dev) +{ + struct ec_acpi_config *cfg = dev->chip_info; + + if (cfg->cmd_reg) + ec_cmd_reg = cfg->cmd_reg; + + if (cfg->data_reg) + ec_data_reg = cfg->data_reg; +} + struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") + .enable_dev = ec_acpi_init }; diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 2817255..eaad967 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -87,6 +87,8 @@ chip northbridge/intel/i945 end end chip ec/acpi + register "cmd_reg" = "0x1604" + register "data_reg" = "0x1600" device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 -- 1.7.4.1

1 0

[PATCH] nvramtool: fixed working with files only on a non-coreboot system
by Mathias Krause 08 Mar '11

08 Mar '11

nvramtool tried to get the CMOS layout from the coreboot option table even when told to take a layout file. This patch fixes that case by slightly changing the order of evaluating the specific options. Now almost all combinations are valid (CMOS content from NVRAM/CBFS/file with CMOS layout from CBFS/option table/layout file). Additionally I fixed some white space issues (spaces to tabs) and throw in some newlines to aid readability of the code. Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com>

2 1

[commit] r6437 - trunk/util/nvramtool/cli
by repository service 08 Mar '11

08 Mar '11

Author: oxygene Date: Tue Mar 8 13:58:16 2011 New Revision: 6437 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6437 Log: nvramtool: Change precedence order for data sources nvramtool couldn't handle certain combinations of sources for CMOS layout and CMOS data. This change allows for nearly all combinations. Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/util/nvramtool/cli/nvramtool.c Modified: trunk/util/nvramtool/cli/nvramtool.c ============================================================================== --- trunk/util/nvramtool/cli/nvramtool.c Tue Mar 8 08:50:43 2011 (r6436) +++ trunk/util/nvramtool/cli/nvramtool.c Tue Mar 8 13:58:16 2011 (r6437) @@ -102,13 +102,9 @@ parse_nvramtool_args(argc, argv); - if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].found) { - set_layout_filename(nvramtool_op_modifiers - [NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].param); - fn = get_layout_from_file; - } else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_OPT_TABLE].found) { - fn = get_layout_from_cmos_table; - } else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].found) { + /* If we should operate on a CBFS file default to reading the layout + * and CMOS contents from it. */ + if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].found) { open_cbfs(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CBFS_FILE].param); if (!nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) { cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, NULL); @@ -117,36 +113,55 @@ exit(1); } } + fn = get_layout_from_cbfs_file; } + + /* If the user wants to use a specific layout file or explicitly use + * the coreboot option table allow him to override previous settings. */ + if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].found) { + set_layout_filename(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_LAYOUT_FILE].param); + fn = get_layout_from_file; + } else if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_OPT_TABLE].found) { + fn = get_layout_from_cmos_table; + } + + /* Allow the user to use a file for the CMOS contents, possibly + * overriding a previously opened "cmos.default" file from the CBFS. */ if (nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) { - int fd; struct stat fd_stat; - if ((fd = open(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param, O_RDWR | O_CREAT, 0666)) < 0) { + int fd; + + if ((fd = open(nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param, O_RDWR | O_CREAT, 0666)) < 0) { fprintf(stderr, "Couldn't open '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); exit(1); } + if (fstat(fd, &fd_stat) == -1) { fprintf(stderr, "Couldn't stat '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); exit(1); } + if (fd_stat.st_size < 128) { lseek(fd, 127, SEEK_SET); write(fd, "\0", 1); fsync(fd); } + cmos_default = mmap(NULL, 128, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); if (cmos_default == MAP_FAILED) { fprintf(stderr, "Couldn't map '%s'\n", nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].param); exit(1); } } + + /* Switch to memory based CMOS access. */ if (cmos_default) { select_hal(HAL_MEMORY, cmos_default); - fn = get_layout_from_cbfs_file; } register_cmos_layout_get_fn(fn); - op_fns[nvramtool_op.op] (); + op_fns[nvramtool_op.op](); + return 0; }

1 0

[commit] r6436 - in trunk/src: arch/x86 arch/x86/include arch/x86/init arch/x86/lib pc80
by repository service 07 Mar '11

07 Mar '11

Author: oxygene Date: Tue Mar 8 08:50:43 2011 New Revision: 6436 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6436 Log: Move cmos.default handling to bootblock The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/Kconfig trunk/src/arch/x86/Makefile.bootblock.inc trunk/src/arch/x86/include/bootblock_common.h trunk/src/arch/x86/init/bootblock_normal.c trunk/src/arch/x86/init/bootblock_simple.c trunk/src/arch/x86/lib/walkcbfs.S trunk/src/pc80/mc146818rtc_early.c Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/Kconfig Tue Mar 8 08:50:43 2011 (r6436) @@ -91,14 +91,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string -config USE_CMOS_RECOVERY - bool - default n if ROMCC - default y - config HAVE_CMOS_DEFAULT def_bool n - depends on USE_CMOS_RECOVERY config CMOS_DEFAULT_FILE string Modified: trunk/src/arch/x86/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/x86/Makefile.bootblock.inc Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/Makefile.bootblock.inc Tue Mar 8 08:50:43 2011 (r6436) @@ -57,7 +57,7 @@ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d Modified: trunk/src/arch/x86/include/bootblock_common.h ============================================================================== --- trunk/src/arch/x86/include/bootblock_common.h Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/include/bootblock_common.h Tue Mar 8 08:50:43 2011 (r6436) @@ -17,17 +17,45 @@ static void bootblock_southbridge_init(void) { } #endif -static unsigned long findstage(char* target) +static void *walkcbfs(char *target) { - unsigned long entry; + void *entry; asm volatile ( "mov $1f, %%esp\n\t" - "jmp walkcbfs\n\t" + "jmp walkcbfs_asm\n\t" "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); return entry; } +/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */ +struct cbfs_stage { + unsigned long compression; + unsigned long entry; // this is really 64bit, but properly endianized +}; + +static unsigned long findstage(char* target) +{ + return ((struct cbfs_stage*)walkcbfs(target))->entry; +} + static void call(unsigned long addr, unsigned long bist) { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } + +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> + +static void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_chksum_valid()) { + unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + if (cmos_default) { + int i; + for (i = 14; i < 128; i++) { + cmos_write(cmos_default[i], i); + } + } + } +} +#endif Modified: trunk/src/arch/x86/init/bootblock_normal.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_normal.c Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/init/bootblock_normal.c Tue Mar 8 08:50:43 2011 (r6436) @@ -8,6 +8,10 @@ bootblock_southbridge_init(); } +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + unsigned long entry; if (do_normal_boot()) entry = findstage("normal/romstage"); Modified: trunk/src/arch/x86/init/bootblock_simple.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_simple.c Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/init/bootblock_simple.c Tue Mar 8 08:50:43 2011 (r6436) @@ -6,6 +6,11 @@ bootblock_northbridge_init(); bootblock_southbridge_init(); } + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + const char* target1 = "fallback/romstage"; unsigned long entry; entry = findstage(target1); Modified: trunk/src/arch/x86/lib/walkcbfs.S ============================================================================== --- trunk/src/arch/x86/lib/walkcbfs.S Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/arch/x86/lib/walkcbfs.S Tue Mar 8 08:50:43 2011 (r6436) @@ -15,19 +15,13 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) -#define CBFS_STAGE_COMPRESSION 0 -#define CBFS_STAGE_ENTRY (CBFS_STAGE_COMPRESSION + 4) -#define CBFS_STAGE_LOAD (CBFS_STAGE_ENTRY + 8) -#define CBFS_STAGE_LEN (CBFS_STAGE_LOAD + 8) -#define CBFS_STAGE_MEMLEN (CBFS_STAGE_LEN + 4) - /* input %esi: filename input %esp: return address (not pointer to return address!) output %eax: entry point clobbers %ebx, %ecx, %edi */ -walkcbfs: +walkcbfs_asm: cld mov CBFS_HEADER_PTR, %eax @@ -67,8 +61,6 @@ mov CBFS_FILE_OFFSET(%ebx), %eax bswap %eax add %ebx, %eax - add $CBFS_STAGE_ENTRY, %eax /* eax = ((cbfs_stage* (cbfs_file* ebx)->offset)->entry) */ - mov 0(%eax), %eax jmp *%esp tryharder: Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Mon Mar 7 10:09:51 2011 (r6435) +++ trunk/src/pc80/mc146818rtc_early.c Tue Mar 8 08:50:43 2011 (r6436) @@ -11,15 +11,6 @@ #error "CONFIG_MAX_REBOOT_CNT too high" #endif -#if CONFIG_USE_CMOS_RECOVERY -#include <cbfs.h> -#include <console/loglevel.h> - -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) -#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) -#endif - static int cmos_error(void) { unsigned char reg_d; @@ -63,25 +54,6 @@ unsigned char byte; if (cmos_error() || !cmos_chksum_valid()) { -#if CONFIG_USE_CMOS_RECOVERY - char *cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT); - if (cmos_default) { - int i; - printk_warning("WARNING - CMOS CORRUPTED. RESTORING DEFAULTS.\n"); - /* First 14 bytes are reserved for - RTC and ignored by nvramtool, too. - Only 128 bytes: 128+ requires cmos configuration and - contains only suspend-to-ram data, which isn't part - of the recovery procedure. */ - for (i = 14; i < 128; i++) { - cmos_write(cmos_default[i], i); - } - /* Now reboot to run with default cmos. */ - outb(0x06, 0xcf9); - for (;;) asm("hlt"); /* Wait for reset! */ - } -#endif - /* There are no impossible values, no checksums so just * trust whatever value we have in the the cmos, * but clear the fallback bit.

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Google Summer of Code 2011
by Marc Jones 07 Mar '11

07 Mar '11

GSoC mentoring org signup starts this week and is due by March 11. I can take the lead this year, unless someone else would like to do it. If we are accepted (I expect we will be), Student applications are March 28 - April 8. Please add your project ideas to the wiki : http://www.coreboot.org/GSoC Who would like to be a mentor this year? Marc -- http://se-eng.com

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coreboot March 2011