coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

[patch] P-states for selected socket 754 processors
by Jonathan A. Kollasch 04 Mar '11

04 Mar '11

Add P-states for select Socket 754 processors. States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX are from AMD document 30430 3.51. States for ADA3200AIO4BX derived from SSDT of a MS-7135. States for TMDML34BKX5LD derived from legacy PowerNow! table of a MS-7135, and therefore lack accurate TDP information. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> -----

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Re: [coreboot] Troubles with 17'' WXGA on Roda RK886EX
by Vitaly Chertovskih 04 Mar '11

04 Mar '11

Hi! I've grabbed the right one vga bios with 0xae.Ignoring the seabios checksum, it starts normally. Now, coreboot copies it into mem and i can see intel vgabios boot logo, but it appears only on the external LCD. The problem remains the same. Internal LCD is blank, but highlightened. On the 15'' Roda RK8 - all is good. On my 17'' RF8 - blank screen. What shall i do? Please, help. Here is some log. Coreboot init VGA: **** CBFS: follow chain: fff00000 + 28 + 54f + align -> fff00580 Check pci8086,27ae.rom In CBFS, ROM address for PCI: 00:02.0 = fff005b8 PCI expansion ROM, signature 0xaa55, INIT size 0xea00, data ptr 0x0040 PCI ROM image, vendor ID 8086, device ID 27ae, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fff005b8 to 0xc0000, 0xea00 bytes Real mode stub @00000600: 606 bytes Calling Option ROM... DISPLAY=3 ... Option ROM returned. ****** Seabios : ***** Scan for VGA option rom Running option rom at c000:0003 unimplemented handle_155fXX:40: a=10005f40 b=00000011 c=00000055 d=00000000 ds=0000 es=c000 ss=0000 si=0008c2b0 di=00000080 bp=00006efc sp=00006e6a cs=c000 ip=4bd4 f=0046 unimplemented handle_155fXX:40: a=00005f35 b=0000078f c=00000002 d=000000c0 ds=c000 es=c000 ss=0000 si=00071423 di=00000080 bp=00006efc sp=00006ed6 cs=c000 ip=4bd4 f=0046 Turning on vga text mode console *******

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Troubles with 17'' WXGA on Roda RK886EX
by Vitaly Chertovskih 04 Mar '11

04 Mar '11

Hi! I'm experiencing some troubles with VGA on notebook "Roda RF8". That notebook's motherboard and other specification is exact to Roda RK886EX, only the screen is larger (17'' WXGA 1440x900). On that week I installed coreboot on Roda RK886EX, it starts perfectly. But when i flashed the same coreboot on notebook RF8 - the screen is lightened, but remains blank. When i connect external LCD - it(external) works well with coreboot. So, i think, that the trouble is in initialization of that internal widescreen LCD. Roda RK886EX have LCD 15.1“ XGA (1024x768) - works perfect. Roda RF8 - 17'' WXGA 1440x900 - blank (but lightened) screen (other init and OS booting is perfect with external LCD) The log file says nothing - when coreboot or seabios calls vga.bin - all is ok, like on Roda RK886EX. Please, help me. Where and how i can fix that? P.S. I build coreboot, choosing Roda motherboard, adding compiled SeaBIOS image (I download it from coreboot.org), and including VGA onboard rom, grabbed from /dev/mem as described in howtos on coreboot.org. I include my log from COM1.

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[commit] r6430 - trunk/src/cpu/amd/model_fxx
by repository service 04 Mar '11

04 Mar '11

Author: jakllsch Date: Fri Mar 4 00:09:43 2011 New Revision: 6430 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6430 Log: Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code. With this change the last P-state entry of the last CPU in the table is successfully conveyed into the SSDT. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/powernow_acpi.c Thu Mar 3 21:52:50 2011 (r6429) +++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c Fri Mar 4 00:09:43 2011 (r6430) @@ -622,7 +622,7 @@ Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage); Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100; Pstate_num++; - } while ((Pstate_num < MAXP) && (data->pstates[Pstate_num].freqMhz != 0)); + } while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0)); for (i=0;i<Pstate_num;i++) printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i,

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[patch] correct off-by-one in pre-rev-F model F powernow code
by Jonathan A. Kollasch 03 Mar '11

03 Mar '11

Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code. With this change the last P-state entry of the last CPU in the table is successfully conveyed into the SSDT. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ----

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build service results for r6429
by repository service 03 Mar '11

03 Mar '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "jakllsch" checked in revision 6429 to the coreboot repository. This caused the following changes: Change Log: Improve ck804 IOAPIC and HPET resource handling. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:adl855pc has been fixed If something broke during this checkin please be a pain in jakllsch's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6429 - trunk/src/southbridge/nvidia/ck804
by repository service 03 Mar '11

03 Mar '11

Author: jakllsch Date: Thu Mar 3 21:52:50 2011 New Revision: 6429 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6429 Log: Improve ck804 IOAPIC and HPET resource handling. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/nvidia/ck804/lpc.c Modified: trunk/src/southbridge/nvidia/ck804/lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/lpc.c Thu Mar 3 16:36:08 2011 (r6428) +++ trunk/src/southbridge/nvidia/ck804/lpc.c Thu Mar 3 21:52:50 2011 (r6429) @@ -104,15 +104,6 @@ pci_write_config8(dev, 0x6d, new); } -static void enable_hpet(struct device *dev) -{ - unsigned long hpet_address; - - pci_write_config32(dev, 0x44, 0xfed00001); - hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); -} - unsigned pm_base = 0; static void lpc_init(device_t dev) @@ -130,12 +121,6 @@ return; #endif -#if 0 - /* Posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif - /* Power after power fail */ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); @@ -166,12 +151,6 @@ pci_write_config8(dev, 0xe8, byte); #endif - /* Enable Error reporting. */ - /* Set up sync flood detected. */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - /* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ byte_old = byte; @@ -190,9 +169,6 @@ /* Initialize ISA DMA. */ isa_dma_init(); - /* Initialize the High Precision Event Timers (HPET). */ - enable_hpet(dev); - rom_dummy_write(dev); } @@ -205,6 +181,9 @@ /* We got one for APIC, or one more for TRAP. */ pci_dev_read_resources(dev); + /* HPET */ + pci_get_resource(dev, 0x44); + /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */ for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */ pci_get_resource(dev, index); @@ -223,10 +202,42 @@ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + if (dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE) { + res = find_resource(dev, 0x14); /* IOAPIC */ + if (res) { + res->base = IO_APIC_ADDR; + res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + + res = find_resource(dev, 0x44); /* HPET */ + if (res) { + res->base = 0xfed00000; + res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + } + } +} + +static void ck804_lpc_set_resources(device_t dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + /* APIC */ + res = find_resource(dev, 0x14); + if (res) { + pci_write_config32(dev, 0x14, res->base); + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } + + /* HPET */ + res = find_resource(dev, 0x44); + if (res) { + pci_write_config32(dev, 0x44, res->base|1); + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } } /** @@ -299,7 +310,7 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus,

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[patch] improve ck804 HPET resource handling
by Jonathan A. Kollasch 03 Mar '11

03 Mar '11

Improve ck804 IOAPIC and HPET resource handling. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> -----

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build service results for r6428
by repository service 03 Mar '11

03 Mar '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "jakllsch" checked in revision 6428 to the coreboot repository. This caused the following changes: Change Log: Configure PCIe lanes on ms7135 as original BIOS does. Signed-off-by: <jakllsch(a)kollasch.net> Acked-by: <jakllsch(a)kollasch.net> Build Log: Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6428&device=adl855pc&vendo… If something broke during this checkin please be a pain in jakllsch's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6428 - trunk/src/mainboard/msi/ms7135
by repository service 03 Mar '11

03 Mar '11

Author: jakllsch Date: Thu Mar 3 16:36:08 2011 New Revision: 6428 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6428 Log: Configure PCIe lanes on ms7135 as original BIOS does. Signed-off-by: <jakllsch(a)kollasch.net> Acked-by: <jakllsch(a)kollasch.net> Modified: trunk/src/mainboard/msi/ms7135/Kconfig Modified: trunk/src/mainboard/msi/ms7135/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7135/Kconfig Thu Mar 3 09:29:03 2011 (r6427) +++ trunk/src/mainboard/msi/ms7135/Kconfig Thu Mar 3 16:36:08 2011 (r6428) @@ -58,4 +58,8 @@ int default 13 +config CK804_PCI_E_X + int + default 0 + endif # BOARD_MSI_MS7135

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coreboot March 2011