coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

via apollo pro 133 code (for mue)
by Anders Jenbo 02 Mar '11

02 Mar '11

Hi here is the code i did for the via apollo pro 133(a), i also included the code for the board that i was working on so you have some sample code to work with. I was working on the SMB code when i last left it so it isn't able to detect the ram yet, but the serial output works so you have some thing to debug with. -Anders

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[PATCH] outb(* 0x80) to post_code()
by Alex G. 02 Mar '11

02 Mar '11

Applies to fresh svn.......................[OK] abuild run......................................[OK] See patch. Alex

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Re: [coreboot] how to deal with large romstage size?
by Keith Hui 02 Mar '11

02 Mar '11

>> Hi, >> >> I think you need to make the complete flash visible in a southbridge bootblock.c >> >> It would help if you could publish your current code so we can do better than asking the crystal ball for answers ;) >> > it's based on D945gclf, but MRC is under NDA, :-( > > Thanks! It's the Memory Reference Code, for those who don't know. You probably can place a banner to be sent via serial port where MRC is about to come into play ie. raminit is about to start, and replace the MRC in the review copy you post up here with some code to generate 110k of dead beefs. :-D When we try it and the banner shows, that would be a good sign. AMD wins a point in supporting open source, again. -_-

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Tiny bootblock vs Bigbootblock
by ali hagigat 02 Mar '11

02 Mar '11

I created a new source code tree for only one motherboard, ASUS, MEW_AM. There is no build/bootblock folder and CONFIG_TINY_BOOTBLOCK and CONFIG_BOOTBLOCK_SIMPLE are not set. What is the difference between tiny and big boot block? My second question is that the code of bootblock is copied to romstage too. I mean we have a duplicate code in two different components. Is that right?

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Re: [coreboot] how to deal with large romstage size?
by Keith Hui 01 Mar '11

01 Mar '11

Arrandale and QM57... very nice recent hardware. You are going to need to 1) make TINY_BOOTBLOCK work, 2) make sure QM57 can map the entire ROM, 3) make CAR work on Arrandale, IIRC coreboot still has no support for anything in the Intel Core family of CPUs. Good luck. > 主题： Re: [coreboot] how to deal with large romstage size? >> Hi all, >> >> After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly. >> Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB? >> >> Thanks a lot! >> 2011-03-01 >> > >> It is not a direct limitation on romstage's size, but a result of most >> chipsets mapping only the top 64KB of flash to the memory space. Most >> chipsets require some programming to have the entire flash rom appear >> in memory. Your code didn't run properly because not all of it has >> been mapped to memory space and get effectively cut. >> >> But my romstage for Intel 440BX is only about 11KB. What chipset are >> you dealing with? > > my chipset is intel arrandal+qm57,it's MRC code is very large(about 110KB > after build) :-( > >> Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub, >> well within the 64KB limit, which does nothing but enable enough >> hardware (southbridge to be exact) to make the entire rom visible, >> then locates and executes the real romstage which is now just another >> stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be >> a reference. > > actually, it can run at bootblock,but can not reach "cache_as_ram:". > So I think the code failed at jmp to the romstage in CBFS. >

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coreboot certified hardware
by Carl-Daniel Hailfinger 01 Mar '11

01 Mar '11

Hi, I wonder if we want to establish something like the "Designed for Windows XP" or "Yes it runs with Netware" certificates? It would certainly be a nice marketing aid for vendors, and at the same time it would promote coreboot visibility. If there is interest in such an idea, we will have to decide which criteria have to be fulfilled to get such a certificate, and if the certificate has an expiry date and/or is bound to a specific svn revision. Off the top of my head, I can think of the following criteria: - coreboot+SeaBIOS works well enough to boot $ENTERPRISE_LINUX, $ENDUSER_LINUX and Windows 7 (Vista and XP as well?) - Nvidia and ATI graphics drivers (both free and closed) work if booted with a coreboot+SeaBIOS image? - Frequency scaling and the various suspend methods work - Soft poweroff works - IRQ routing and all PCI/PCIe/AGP/whatever slots work - Legacy ports (if present) work - Fans work well enough (temperature-based scaling if present in the "normal" BIOS) - Source for a working coreboot image (including the Kconfig settings for the board, and possibly NVRAM settings?) is available for free without NDA - Board port merged into coreboot svn - SeaBIOS source code is available - SeaBIOS code is merged into SeaBIOS git - flashrom works on the board (no lockdown) or there is a way to boot unlocked and run flashrom for your image of choice - At least some serial output (coreboot version) if a serial port (header) is present, otherwise... USB Debug? Floppy? LPC bus? POST card on port 82h? Did I forget something? Are some criteria useless? What would Jane User expect from a normal mainboard if she didn't know coreboot was running? Regards, Carl-Daniel -- http://www.hailfinger.org/

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#178: Life Insurance - How To Buy Life Insurance Policies
by coreboot 01 Mar '11

01 Mar '11

#178: Life Insurance - How To Buy Life Insurance Policies -------------------------------------+------------------------------------- Reporter: anonymous | Owner: Type: enhancement | c-d.hailfinger.devel.2006@… Priority: major | Status: new Component: flashrom (please use | Milestone: flashrom v1.1 trac on flashrom.org) | Keywords: life insurance Dependencies: | Patch Status: patch needs review -------------------------------------+------------------------------------- [[Image(http://www.johnkatsouris.co.uk/images/family_park.jpg)]] Buying such services like '''[http://www.lifeinsurance.net.au/ life insurance]''' in making things better for those people to have its best ways that will be better for them during this days. It can make things better for those people to have its best ways to satisfy their needs in life living in this world. This '''insurances''' people can have the things they need in life living in this world. Having such services that will make things better for them having the best services that will make them have a '''Life Insurance''' in making things better for them during this days. [[Image(http://onlinearnings.com/wp-content/uploads/2009/07/happy-life- insurance.jpg)]] It can make things better for those people having such '''[http://www.lifeinsurance.net.au/ life insurance]''' in a certain period of time. It is best for those people to have such ways that can be better for those people on having the things that will make them have such '''Living Insurance''' in a certain period of time that will make those people have its best ways in living. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/178> coreboot <http://www.coreboot.org/>

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build service results for r6422
by repository service 01 Mar '11

01 Mar '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "svens" checked in revision 6422 to the coreboot repository. This caused the following changes: Change Log: Add lex output lex.yy.c_shipped wasn't committed in r6420, which breaks the build if you don't have the expert option checked that rebuilds those files. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Build Log: Compilation of amd:bimini_fam10 has been fixed Compilation of amd:dbm690t has been fixed Compilation of amd:inagua has been fixed Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:persimmon has been fixed Compilation of amd:pistachio has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of arima:hdama has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asrock:e350m1 has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2n-e has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:m4a78-em has been fixed Compilation of asus:m4a785-m has been fixed Compilation of broadcom:blast has been fixed Compilation of dell:s1850 has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of hp:dl145_g1 has been fixed Compilation of intel:d945gclf has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:kt690 has been fixed Compilation of lenovo:x60 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of newisys:khepri has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of roda:rk886ex has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of tyan:s2735 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s2912_fam10 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:pc2500e has been fixed Compilation of wyse:s50 has been fixed If something broke during this checkin please be a pain in svens's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] r6421-correct-ids.patch
by Sylvain 'ythier' Hitier 01 Mar '11

01 Mar '11

(Please keep me in CC, I'm not subscribed to the list) After reading r6421. Index: src/mainboard/asus/m2v/devicetree.cb =================================================================== --- src/mainboard/asus/m2v/devicetree.cb (revision 6421) +++ src/mainboard/asus/m2v/devicetree.cb (working copy) @@ -5,7 +5,7 @@ end end device pci_domain 0 on # PCI domain - subsystemid 0x143 0 inherit + subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 Index: src/mainboard/gigabyte/ma78gm/devicetree.cb =================================================================== --- src/mainboard/gigabyte/ma78gm/devicetree.cb (revision 6421) +++ src/mainboard/gigabyte/ma78gm/devicetree.cb (working copy) @@ -6,7 +6,7 @@ end end device pci_domain 0 on - subsystemid 0x3060 0x1022 inherit + subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 Index: src/mainboard/roda/rk886ex/devicetree.cb =================================================================== --- src/mainboard/roda/rk886ex/devicetree.cb (revision 6421) +++ src/mainboard/roda/rk886ex/devicetree.cb (working copy) @@ -28,7 +28,7 @@ end device pci_domain 0 on - subsystemid 0x4352 0x0686 inherit + subsystemid 0x4352 0x6886 inherit device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port Regards, Sylvain "ythier" Hitier -- Free hugs for Free Software Fellows! Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse

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[commit] r6425 - in trunk/src/mainboard: asus/m2v gigabyte/ma78gm roda/rk886ex
by repository service 01 Mar '11

01 Mar '11

Author: svens Date: Tue Mar 1 23:02:37 2011 New Revision: 6425 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6425 Log: Fix some subsystemid statements in r6421 Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/mainboard/asus/m2v/devicetree.cb trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb trunk/src/mainboard/roda/rk886ex/devicetree.cb Modified: trunk/src/mainboard/asus/m2v/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/m2v/devicetree.cb Tue Mar 1 22:57:11 2011 (r6424) +++ trunk/src/mainboard/asus/m2v/devicetree.cb Tue Mar 1 23:02:37 2011 (r6425) @@ -5,7 +5,7 @@ end end device pci_domain 0 on # PCI domain - subsystemid 0x143 0 inherit + subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge # Devices on link 0, link 0 == LDT 0 Modified: trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb Tue Mar 1 22:57:11 2011 (r6424) +++ trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb Tue Mar 1 23:02:37 2011 (r6425) @@ -6,7 +6,7 @@ end end device pci_domain 0 on - subsystemid 0x3060 0x1022 inherit + subsystemid 0x1022 0x3060 inherit chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 Modified: trunk/src/mainboard/roda/rk886ex/devicetree.cb ============================================================================== --- trunk/src/mainboard/roda/rk886ex/devicetree.cb Tue Mar 1 22:57:11 2011 (r6424) +++ trunk/src/mainboard/roda/rk886ex/devicetree.cb Tue Mar 1 23:02:37 2011 (r6425) @@ -28,7 +28,7 @@ end device pci_domain 0 on - subsystemid 0x4352 0x0686 inherit + subsystemid 0x4352 0x6886 inherit device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port

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coreboot March 2011