coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

Re: [coreboot] [PATCH] Proposal for dealing with superio *.c includes
by Keith Hui 03 Mar '11

03 Mar '11

> Option C with GPLv2+ licensing. A few quick things: SUPERIO_FINTEK_F81865F_HAS_EARLY_SERIAL seems long-winded for a name. I prefer to define CONFIG_SUPERIO_HAS_EARLY_SERIAL (or even just CONFIG_HAS_EARLY_SERIAL) within the superio Kconfig and not in mainboard Kconfig. This I think would be a per-superio setting. While we're at it, have we seen a board with 2+ superios? Having said that though, isn't early serial support sort of mandatory anyway? Secretly I'm hoping that some of my ideas end up in here. :-) Cheers Keith

4 6

[PATCH] add PC87384 SuperIO
by Sven Schnelle 03 Mar '11

03 Mar '11

Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/superio/nsc/Kconfig | 2 + src/superio/nsc/Makefile.inc | 1 + src/superio/nsc/pc87384/Makefile.inc | 22 +++++++++ src/superio/nsc/pc87384/chip.h | 31 +++++++++++++ src/superio/nsc/pc87384/pc87384.h | 28 ++++++++++++ src/superio/nsc/pc87384/superio.c | 80 ++++++++++++++++++++++++++++++++++ 6 files changed, 164 insertions(+), 0 deletions(-) create mode 100644 src/superio/nsc/pc87384/Makefile.inc create mode 100644 src/superio/nsc/pc87384/chip.h create mode 100644 src/superio/nsc/pc87384/pc87384.h create mode 100644 src/superio/nsc/pc87384/superio.c diff --git a/src/superio/nsc/Kconfig b/src/superio/nsc/Kconfig index 3a98d83..0d97bc4 100644 --- a/src/superio/nsc/Kconfig +++ b/src/superio/nsc/Kconfig @@ -30,6 +30,8 @@ config SUPERIO_NSC_PC87366 bool config SUPERIO_NSC_PC87382 bool +config SUPERIO_NSC_PC87384 + bool config SUPERIO_NSC_PC87392 bool config SUPERIO_NSC_PC87417 diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc index 08f28df..c11170e 100644 --- a/src/superio/nsc/Makefile.inc +++ b/src/superio/nsc/Makefile.inc @@ -23,6 +23,7 @@ subdirs-y += pc87351 subdirs-y += pc87360 subdirs-y += pc87366 subdirs-y += pc87382 +subdirs-y += pc87384 subdirs-y += pc87392 subdirs-y += pc87417 subdirs-y += pc87427 diff --git a/src/superio/nsc/pc87384/Makefile.inc b/src/superio/nsc/pc87384/Makefile.inc new file mode 100644 index 0000000..b577489 --- /dev/null +++ b/src/superio/nsc/pc87384/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c + diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h new file mode 100644 index 0000000..4eaa92f --- /dev/null +++ b/src/superio/nsc/pc87384/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87384_CHIP_H +#define SUPERIO_NSC_PC87384_CHIP_H + +#include <uart8250.h> +extern struct chip_operations superio_nsc_pc87384_ops; + +struct superio_nsc_pc87384_config { + struct uart8250 com1, com2; +}; + +#endif diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h new file mode 100644 index 0000000..fe573b7 --- /dev/null +++ b/src/superio/nsc/pc87384/pc87384.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87384_H +#define SUPERIO_NSC_PC87384_H + +#define PC87384_PP 0x01 +#define PC87384_SP2 0x02 +#define PC87384_SP1 0x03 +#define PC87384_GPIO 0x07 +#endif diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c new file mode 100644 index 0000000..5bd318f --- /dev/null +++ b/src/superio/nsc/pc87384/superio.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "pc87384.h" + +static void init(device_t dev) +{ + struct superio_nsc_pc87384_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case PC87384_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case PC87384_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + + case PC87384_GPIO: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} }, + { &ops, PC87384_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } }, + { &ops, PC87384_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } }, + { &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nsc_pc87384_ops = { + CHIP_NAME("NSC PC87384 Super I/O") + .enable_dev = enable_dev, +}; -- 1.7.4.1

2 2

[commit] r6427 - in trunk/src/superio/nsc: . pc87384
by repository service 03 Mar '11

03 Mar '11

Author: svens Date: Thu Mar 3 09:29:03 2011 New Revision: 6427 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6427 Log: add PC87384 SuperIO Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/superio/nsc/pc87384/ trunk/src/superio/nsc/pc87384/Makefile.inc - copied, changed from r6425, trunk/src/superio/nsc/Makefile.inc trunk/src/superio/nsc/pc87384/chip.h trunk/src/superio/nsc/pc87384/pc87384.h trunk/src/superio/nsc/pc87384/superio.c Modified: trunk/src/superio/nsc/Kconfig trunk/src/superio/nsc/Makefile.inc Modified: trunk/src/superio/nsc/Kconfig ============================================================================== --- trunk/src/superio/nsc/Kconfig Wed Mar 2 20:56:28 2011 (r6426) +++ trunk/src/superio/nsc/Kconfig Thu Mar 3 09:29:03 2011 (r6427) @@ -30,6 +30,8 @@ bool config SUPERIO_NSC_PC87382 bool +config SUPERIO_NSC_PC87384 + bool config SUPERIO_NSC_PC87392 bool config SUPERIO_NSC_PC87417 Modified: trunk/src/superio/nsc/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/Makefile.inc Wed Mar 2 20:56:28 2011 (r6426) +++ trunk/src/superio/nsc/Makefile.inc Thu Mar 3 09:29:03 2011 (r6427) @@ -23,6 +23,7 @@ subdirs-y += pc87360 subdirs-y += pc87366 subdirs-y += pc87382 +subdirs-y += pc87384 subdirs-y += pc87392 subdirs-y += pc87417 subdirs-y += pc87427 Copied and modified: trunk/src/superio/nsc/pc87384/Makefile.inc (from r6425, trunk/src/superio/nsc/Makefile.inc) ============================================================================== --- trunk/src/superio/nsc/Makefile.inc Tue Mar 1 23:02:37 2011 (r6425, copy source) +++ trunk/src/superio/nsc/pc87384/Makefile.inc Thu Mar 3 09:29:03 2011 (r6427) @@ -1,11 +1,12 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,14 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -subdirs-y += pc8374 -subdirs-y += pc87309 -subdirs-y += pc87351 -subdirs-y += pc87360 -subdirs-y += pc87366 -subdirs-y += pc87382 -subdirs-y += pc87392 -subdirs-y += pc87417 -subdirs-y += pc87427 -subdirs-y += pc97307 -subdirs-y += pc97317 +ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c + Added: trunk/src/superio/nsc/pc87384/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87384/chip.h Thu Mar 3 09:29:03 2011 (r6427) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87384_CHIP_H +#define SUPERIO_NSC_PC87384_CHIP_H + +#include <uart8250.h> +extern struct chip_operations superio_nsc_pc87384_ops; + +struct superio_nsc_pc87384_config { + struct uart8250 com1, com2; +}; + +#endif Added: trunk/src/superio/nsc/pc87384/pc87384.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87384/pc87384.h Thu Mar 3 09:29:03 2011 (r6427) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NSC_PC87384_H +#define SUPERIO_NSC_PC87384_H + +#define PC87384_PP 0x01 +#define PC87384_SP2 0x02 +#define PC87384_SP1 0x03 +#define PC87384_GPIO 0x07 +#endif Added: trunk/src/superio/nsc/pc87384/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nsc/pc87384/superio.c Thu Mar 3 09:29:03 2011 (r6427) @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "pc87384.h" + +static void init(device_t dev) +{ + struct superio_nsc_pc87384_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case PC87384_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case PC87384_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + + case PC87384_GPIO: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} }, + { &ops, PC87384_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } }, + { &ops, PC87384_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } }, + { &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nsc_pc87384_ops = { + CHIP_NAME("NSC PC87384 Super I/O") + .enable_dev = enable_dev, +};

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Re: [coreboot] how to deal with large romstage size?
by Keith Hui 03 Mar '11

03 Mar '11

> Hi all, > > After I add some memory initialisize code, the romstage is over 64K byte,and tne code can't run properly. > Then what should I do when romstage is over 64K byte? Is romstage's size limits to 64KB? > > Thanks a lot! > 2011-03-01 > It is not a direct limitation on romstage's size, but a result of most chipsets mapping only the top 64KB of flash to the memory space. Most chipsets require some programming to have the entire flash rom appear in memory. Your code didn't run properly because not all of it has been mapped to memory space and get effectively cut. But my romstage for Intel 440BX is only about 11KB. What chipset are you dealing with? Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub, well within the 64KB limit, which does nothing but enable enough hardware (southbridge to be exact) to make the entire rom visible, then locates and executes the real romstage which is now just another stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be a reference. Hope this help. Keith

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Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
by Keith Hui 02 Mar '11

02 Mar '11

> > Please don't gzip patches, it lowers the chance of someone reviewing > them to zero ;-) I figured if we're coding at this level, gzip won't be a hurdle. I announced it up front, didn't I? :p > > There is 65x microcode in the model_67x directory, and it's not split up > into single files as for the other CPUs. > The microcodes are static and are not supposed to change, our CPU drivers are grouped by family, and the microcodes are going to be included one after another in one place anyway even when made separate, so why have 5 files for 5 microcodes in the 67x family for example when one will do? Of course I retained the comments therein that marks the microcodes and the processors they're intended for. To put things in perspective, the microcode data we get from Intel has hundreds of them all in one file. > + if (cpuid_res.ebx != 0x756e6547 || cpuid_res.edx != 0x49656e69 || > cpuid_res.ecx != 0x6c65746e) { > + printk(BIOS_INFO, "Not 'GenuineIntel' Processor"); > + return 0; > + } > > This is not necessary. When model_6**_init() is executed, it's clear > already that this is an intel cpu. I'm not sure if the check for choosing the CPU driver to execute is on these CPUID signatures, or through some other fields. This check is carried from v1. I agree we can take a chance and take it out; we'll revisit when something breaks. :D > > +/* if (signature & 0x1000) { > + printk(BIOS_DEBUG,"Overdrive chip no L2 cache configuration\n"); > + return 0; > + } > + > + if (signature < 0x630 || signature >= 0x680) { > + printk(BIOS_DEBUG,"L2 cache on CPUID %x does not require > configuration\n", signature); > + return 0; > + }*/ > > I think this code should just be dropped That may change when (IF) we manage to get coreboot on a socket 8 board on which a Pentium II OverDrive processor sits. Again this piece is from the original code from v1. I agree the second signature check is not needed. > > Is it generally possible to move p6_configure_l2_cache to a generic > place, maybe to cpu/x86/cache ? > > +/*--- End L2 init code from corebbot v1 ---*/ > > I think this kind of comment is not needed. > That's a marker to help preserve my sanity. :-p > +static inline void strcpy(char *dst, char *src) > +{ > + while (*src) *dst++ = *src++; > +} > > I know I am the idiot who introduced this in a model_xxx_init.c file, > but maybe we should move it to lib/strcpy.c ? Well, 63x and 67x don't even need this; they don't support the processor brand string that 6bx do. Same with the fill_processor_name() function. I'll just take them out entirely. > > +static struct cpu_device_id cpu_table[] = { > + { X86_VENDOR_INTEL, 0x0650 }, > + { X86_VENDOR_INTEL, 0x0651 }, > + { X86_VENDOR_INTEL, 0x0652 }, > + { X86_VENDOR_INTEL, 0x0653 }, > + { X86_VENDOR_INTEL, 0x0671 }, > + { X86_VENDOR_INTEL, 0x0672 }, > + { X86_VENDOR_INTEL, 0x0673 }, > + { 0, 0 }, > +}; > > Instead of using a common driver, can two drivers use a common set of > shared functions instead? > It's already partially done. src/cpu/intel/model_67x/l2_cache.c (new in this patch) is linked in by model_65x driver too. Next prime suspect: fill_processor_name() in 6bx and a few other CPU models I'm no expert of. But 65x and 67x really are so similar that one driver can do both. Now is our end goal here to spin off model_63x/65x/66x/67x/68x/6ax/6bx all into their own CPU drivers when most of what's being done is duplicating code from model_6xx which is what they collectively once were? What's the rationale behind this need for split? I think a split should only be done when different initialization sequence are needed, eg. the special L2 initialization sequence for these SECC P6s. Same with motherboard models. When P2B-LS support matures I'd probably use the same directory for P2B-L and P2B-S support. They share the same circuit board anyway, and a -LS can emulate both by moving two jumpers. > +ifeq ($(CONFIG_USE_DCACHE_RAM),y) > +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc > +endif > > This will break all targets except the ones you worked on. > I read this and thought, "I gotta run abuild." So I did. The errors I saw all seems to be k8/k10 targets and/or ACPI related. Even the entire P2B family that is in the tree passed abuild with this patch applied. Oh they haven't been migrated to CAR yet. Thanks Keith

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Hello
by Andy 02 Mar '11

02 Mar '11

How to use the coreboot-5917 software??

2 1

Re: [coreboot] [commit] r6418 - trunk/src/northbridge/amd/lx
by Nils 02 Mar '11

02 Mar '11

Hi Patrick, >Author: oxygene >Date: Tue Mar 1 08:30:14 2011 >New Revision: 6418 >URL: https://tracker.coreboot.org/trac/coreboot/changeset/6418 > >Log: >Mark non-returning function as noreturn to help some compiler versions > >Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com> >Acked-by: Patrick Georgi <patrick.georgi at secunet.com> > >Modified: > trunk/src/northbridge/amd/lx/raminit.c > >Modified: trunk/src/northbridge/amd/lx/raminit.c >============================================================================== >--- trunk/src/northbridge/amd/lx/raminit.c Tue Mar 1 08:26:00 2011 >(r6417) >+++ trunk/src/northbridge/amd/lx/raminit.c Tue Mar 1 08:30:14 2011 >(r6418) >@@ -32,7 +32,7 @@ > printk(BIOS_DEBUG, " * %s\n", s); > } > >-static void hcf(void) >+static void __attribute__((noreturn)) hcf(void) > { > print_emerg("DIE\n"); > /* this guarantees we flush the UART fifos (if any) and also Should this change also be applied for the almost same function in Geode GX2? Thanks,Nils.

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[PATCH] Proposal for dealing with superio *.c includes
by Alex G. 02 Mar '11

02 Mar '11

Hi guys! I present a proposal for dealing with the annoying: #include "superio/vendor/model/early_serial.c" present in virtually all romstage.c files. The steps are as follows: 1) Declare a generic prototype: superio_enable_early_serial(); 2) Remove #include */early_serial.c from romstage 3) add a romstage-$(CONFIG_THIS_SUPERIO) += early_serial.c to the superio's Makefile.inc 4) Include the generic "superio/early_serial.h" definition in romstage.c 5) Include the superio specific header in romstage.c 6) Done I'm demonstrating this with the fintek/f81865f superio, and the amd/persimmon board. Besides discussion, this patch is also intended for inclusion. See patch for more details.

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[PATCH] Add K8T800, K8T800Pro*, and K8M800* support
by Alex G. 02 Mar '11

02 Mar '11

Find attached a new version of my previous patch for the K8T800. In my previous patch, I was worried that the .tblpointer could contain incorrect values. I have hexdumped the image for the A8V-E SE (K8T8900 chipset), and it contains the correct values. The same applies to the board I'm porting (with K8T800 chipset). I remember someone on IRC asking about the previous patch for the K8T800. I've added the PCI ID for the K8M800 VGA controller to the K8M890 driver, so the VGA might work (TM) on the K8M800. The code for the K8T800 works. The reason I'm not also putting up a patch for the ASUS K8V-X SE is that IRQs are not (yet) working well for this board. Alex *These northbridges have not been tested.

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[commit] r6426 - trunk/src/southbridge/via/k8t890
by repository service 02 Mar '11

02 Mar '11

Author: stuge Date: Wed Mar 2 20:56:28 2011 New Revision: 6426 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6426 Log: Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/via/k8t890/k8x8xx.h Modified: trunk/src/southbridge/via/k8t890/k8x8xx.h ============================================================================== --- trunk/src/southbridge/via/k8t890/k8x8xx.h Tue Mar 1 23:02:37 2011 (r6425) +++ trunk/src/southbridge/via/k8t890/k8x8xx.h Wed Mar 2 20:56:28 2011 (r6426) @@ -5,7 +5,7 @@ * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -14,7 +14,8 @@ * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H

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coreboot March 2011