coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

AGP video card reset again showing only half the RAM. Why?
by Keith Hui 07 Mar '11

07 Mar '11

Tonight I observed that on my P2B-LS board, my nvidia geforce fx5200 AGP card with 128MB ram, after the first initialization run showing 128MB RAM, reset again showing only 64MB RAM. Is this as simple as a AGP graphics aperture problem? Or is it something more?

2 1

option_table.h missing
by Josef Kellermann 07 Mar '11

07 Mar '11

Hi, I got the following build time failure with revision 6435: HOSTCC cbfstool/cbfstool.o HOSTCXX cbfstool/cbfstool (link) CC lib/uart8250.romstage.o src/lib/uart8250.c:25:26: error: option_table.h: Datei oder Verzeichnis nicht gefunden src/lib/uart8250.c: In function 'uart_init': src/lib/uart8250.c:112: error: 'CMOS_VSTART_baud_rate' undeclared (first use in this function) src/lib/uart8250.c:112: error: (Each undeclared identifier is reported only once src/lib/uart8250.c:112: error: for each function it appears in.) src/lib/uart8250.c:112: error: 'CMOS_VLEN_baud_rate' undeclared (first use in this function) make: *** [build/lib/uart8250.romstage.o] Fehler 1 Can anyone tell me what's wrong ? Thanks. Josef

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Trac reminder: list of new ticket(s)
by coreboot tracker 07 Mar '11

07 Mar '11

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[PATCH] [and discussion] Add target for ASUS K8V-X SE motherboard
by Alex G. 07 Mar '11

07 Mar '11

This is the most up-to-date patch on a board I have been struggling with for over a month now I am posting this patch for both discussion and inclusion. The good part is we get to linux. The bad part is that linux gets bored of waiting for the IRQs. The IRQs do not seem to work, at least, they partially do not work. This board is on loan from a friend, and I will have to give it back in a few days. If I can't get it to work, I'd at least like my work to be available for the next person who may want to get this model running. The first obvious sign of something going wrong is the keyboard not responding in SeaBIOS. Later, linux tells us: "..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 0) ... ...... works." message from linux. This indicates to me that linux is setting up the timer as IRQ0 through the i8259A, through the IOAPIC pin 0 as ExtInt, and to the LAPIC lint0 as ExtInt. The mfg BIOS sets it up through the IOAPIC pin2, and it works. We later see the i8259 IMR= fffa, which means IRQ0 (timer) and IRQ2(cascade) are unmasked. In the mfg BIOS, the IMR = fffb, which means that only IRQ2 is unmasked, so the timer should be set up through the IOAPIC pin 2. Under coreboot, linux finally says ata3: lost interrupt (Status 0x58) and dies. Well, maybe it's just the IOAPIC acting up, so let's put a "noapic" in the kernel arguments and see what happens. IRQs still do not work and linux stops at the same error message. The fact that the IOAPIC is accepting IRQ0 from the PIC means that the IOAPIC should at least work as a VirtualWire, but the fact that interrupts still do not work in "noapic" mode indicates the opposite. Is it the IOAPIC acting up, or the i8259? Maybe I'm looking at the problem from the wrong perspective. I'd appreciate any suggestions or hints to get this board corebooting. I'm also attaching the boot log from both coreboot and the mfg BIOS for a more complete reference. Alex

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[commit] r6435 - trunk/src/mainboard/lenovo/x60/acpi
by repository service 07 Mar '11

07 Mar '11

Author: svens Date: Mon Mar 7 10:09:51 2011 New Revision: 6435 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6435 Log: X60: add thermal zone 1 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Mar 7 10:00:50 2011 (r6434) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Mar 7 10:09:51 2011 (r6435) @@ -39,6 +39,7 @@ KBLT, 1, /* Keyboard Light */ Offset (0x78), TMP0, 8, /* Thermal Zone 0 temperature */ + TMP1, 8, /* Thermal Zone 1 temperature */ Offset (0x81), PAGE, 8 /* Information Page Selector */ } Modified: trunk/src/mainboard/lenovo/x60/acpi/thermal.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Mon Mar 7 10:00:50 2011 (r6434) +++ trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Mon Mar 7 10:09:51 2011 (r6435) @@ -23,4 +23,19 @@ Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } } + + ThermalZone(THM1) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(99)) + } + + Method(_PSV, 0, NotSerialized) { + Return (C2K(94)) + } + + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } }

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[commit] r6434 - trunk/src/mainboard/lenovo/x60/acpi
by repository service 07 Mar '11

07 Mar '11

Author: svens Date: Mon Mar 7 10:00:50 2011 New Revision: 6434 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6434 Log: X60: add thermal zone 0 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Sun Mar 6 18:58:31 2011 (r6433) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Mar 7 10:00:50 2011 (r6434) @@ -36,7 +36,9 @@ LEDS, 8, /* LED state */ Offset (0x3B), , 1, - KBLT, 1, /* Keyboard Light */ + KBLT, 1, /* Keyboard Light */ + Offset (0x78), + TMP0, 8, /* Thermal Zone 0 temperature */ Offset (0x81), PAGE, 8 /* Information Page Selector */ } Modified: trunk/src/mainboard/lenovo/x60/acpi/thermal.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Sun Mar 6 18:58:31 2011 (r6433) +++ trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Mon Mar 7 10:00:50 2011 (r6434) @@ -0,0 +1,26 @@ +Scope(\_TZ) +{ + Method(C2K, 1, NotSerialized) + { + Multiply(Arg0, 10, Local0) + Add (Local0, 2732, Local0) + if (LLessEqual(Local0, 2732)) { + Return (3000) + } + + if (LGreater(Local0, 4012)) { + Return (3000) + } + Return (Local0) + } + + ThermalZone(THM0) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(127)) + } + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) + } + } +}

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hardware specs and bios info
by donnie hylton 07 Mar '11

07 Mar '11

i only have a 32 bit edition of windows installed and i know nothing about programming so i am not able to use the linux tools listed. so i have sent the hardware specs in the attachments that i created using some programs for windows i found. my laptop is a toshiba l35 s2151. in the hardware specs and the bios info the number of total memory slots says 4 even though there are only 2. i have taken the laptop apart more than once and have only seen 2 ram slots. here is a link to the processor. http://ark.intel.com/Product.aspx?id=27149&processor=420&spec-codes=SL8VZ in the hardware spec attachment that i sent it says that the package socket is 479 mPGA but on the intel webpage under Ordering / sSpecs / Steppings the processor is listed as Intel® Celeron® M Processor 420 (1M Cache, 1.60 GHz, 533 MHz FSB) uFCPGA, Tray and having a socket type of PPGA478. that is 3 different listings PPGA478,479 mPGA,uFCPGA from 2 different sources intel and speccy a program from piriform. __________________________________________ BreakThru.com - Pure email. Zero spam. http://friendfinder.com/go/f47930 - Dating Personals and Social Networking http://quizhappy.com/go/f301 - Ph.D certified tests and quizzes http://dine.com/go/f5554 - Restaurant Reviews in your area

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[PATCH] X60: add thermal zone 1
by Sven Schnelle 06 Mar '11

06 Mar '11

Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/acpi/thermal.asl | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl index b7256ce..35b6f14 100644 --- a/src/mainboard/lenovo/x60/acpi/thermal.asl +++ b/src/mainboard/lenovo/x60/acpi/thermal.asl @@ -23,4 +23,19 @@ Scope(\_TZ) Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) } } + + ThermalZone(THM1) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(99)) + } + + Method(_PSV, 0, NotSerialized) { + Return (C2K(94)) + } + + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP1)) + } + } } -- 1.7.4.1

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a question about ASUS, MEW-AM
by ali hagigat 06 Mar '11

06 Mar '11

Where the graphics card is initialized in the source code? Is it using Internal graphics card or external? I found some vga routines in pc80 and console folders.

2 1

Add NSC PC87364 support to superiotool
by Michael Karcher 06 Mar '11

06 Mar '11

Hello jankeso, in the process of writing a board enable procedure for your mainboard I stumbled upon the fact that the chip used to control the write enable line is most likely your Super I/O chip, which is a NSC PC87364. superiotool currently does not support dumping that chip, so I can not verify that indeed the GPIO port of the Super I/O chip is accessed (at address 0x80C). I attached a patch to dump the contents of that chip to this mail. Please apply that patch to current superiotool CVS sources (to be obtained from svn://coreboot.org/repos/trunk/util/superiotool) and attach the output to a reply to this mail or upload to paste.flashrom.org. This mail has been cc'ed to the coreboot list for getting this patch included into superiotool. If something is wrong with that patch, please Cc: me, as I am not subscribed to the coreboot list. Thanks. Regards, Michael Karcher

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coreboot March 2011