coreboot September 2010

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[commit] r5778 - trunk/src/mainboard/emulation/qemu-x86
by repository service 06 Sep '10

06 Sep '10

Author: myles Date: Mon Sep 6 22:20:47 2010 New Revision: 5778 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5778 Log: Update RoadRunner and SpaceRunner config to get in sync with current standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/mainboard.c Sun Sep 5 07:52:33 2010 (r5777) +++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c Mon Sep 6 22:20:47 2010 (r5778) @@ -10,15 +10,15 @@ /* not sure how these are routed in qemu */ static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; -static void qemu_init(device_t dev) +static void qemu_nb_init(device_t dev) { - /* The VGA OPROM already lives at 0xc0000, - * force coreboot to use it. - */ - dev->on_mainboard = 1; - - /* Now do the usual initialization */ - pci_dev_init(dev); + /* Map memory at 0xc0000 - 0xfffff */ + int i; + uint8_t v = pci_read_config8(dev, 0x59); + v |= 0x30; + pci_write_config8(dev, 0x59, v); + for (i=0; i<6; i++) + pci_write_config8(dev, 0x5a + i, 0x33); /* This sneaked in here, because Qemu does not * emulate a SuperIO chip @@ -32,6 +32,31 @@ pci_assign_irqs(0, 3, enetIrqs); } +static struct device_operations nb_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, + .ops_pci = 0, +}; + +static const struct pci_driver nb_driver __pci_driver = { + .ops = &nb_operations, + .vendor = 0x8086, + .device = 0x1237, +}; + +static void qemu_init(device_t dev) +{ + /* The VGA OPROM already lives at 0xc0000, + * force coreboot to use it. + */ + dev->on_mainboard = 1; + + /* Now do the usual initialization */ + pci_dev_init(dev); +} + static struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources,

1 0

[PATCH] cbfstool "add-lzma" method
by Kevin O'Connor 06 Sep '10

06 Sep '10

This patch enhances cbfstool so that it can support "cbfstool ROM add-lzma FILE NAME" calls. This is useful for callers that wish to add an lzma compressed raw file. Right now, SeaBIOS supports lzma raw files for things like floppy images. Today, adding one of these files requires a two step process - for example: $ lzma -zc /path/to/myfloppy.img > myfloppy.img.lzma $ cbfstool coreboot.rom add myfloppy.img.lzma floppyimg/MyFloppy.lzma raw Unfortunately, various versions of "lzma" are quirky and the above can be troublesome. With the patch below, a user need only execute: $ cbfstool coreboot.rom add-lzma myfloppy.img floppyimg/MyFloppy.lzma Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Index: util/cbfstool/cbfs.h =================================================================== --- util/cbfstool/cbfs.h (revision 5777) +++ util/cbfstool/cbfs.h (working copy) @@ -73,6 +73,7 @@ #define CBFS_COMPONENT_OPTIONROM 0x30 #define CBFS_COMPONENT_BOOTSPLASH 0x40 #define CBFS_COMPONENT_RAW 0x50 +#define CBFS_COMPONENT_LZMA_RAW 0x40000050 #define CBFS_COMPONENT_VSA 0x51 #define CBFS_COMPONENT_MBI 0x52 #define CBFS_COMPONENT_MICROCODE 0x53 Index: util/cbfstool/common.c =================================================================== --- util/cbfstool/common.c (revision 5777) +++ util/cbfstool/common.c (working copy) @@ -142,6 +142,7 @@ {CBFS_COMPONENT_OPTIONROM, "optionrom"}, {CBFS_COMPONENT_BOOTSPLASH, "bootsplash"}, {CBFS_COMPONENT_RAW, "raw"}, + {CBFS_COMPONENT_LZMA_RAW, "lzma-raw"}, {CBFS_COMPONENT_VSA, "vsa"}, {CBFS_COMPONENT_MBI, "mbi"}, {CBFS_COMPONENT_MICROCODE, "microcode"}, Index: util/cbfstool/cbfstool.c =================================================================== --- util/cbfstool/cbfstool.c (revision 5777) +++ util/cbfstool/cbfstool.c (working copy) @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#include <stdlib.h> #include <stdio.h> #include <stdint.h> #include <string.h> @@ -28,6 +29,7 @@ CMD_ADD, CMD_ADD_PAYLOAD, CMD_ADD_STAGE, + CMD_ADD_LZMA, CMD_CREATE, CMD_LOCATE, CMD_PRINT @@ -187,6 +189,73 @@ return 0; } +static int cbfs_add_lzma(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; + void *rom = loadrom(romname); + + if (rom == NULL) { + printf("Could not load ROM image '%s'.\n", romname); + return 1; + } + + if (argc < 5) { + printf("not enough arguments to '%s'.\n", cmd); + return 1; + } + + char *filename = argv[3]; + char *cbfsname = argv[4]; + + uint32_t filesize = 0; + void *filedata = loadfile(filename, &filesize, 0, SEEK_SET); + if (filedata == NULL) { + printf("Could not load file '%s'.\n", filename); + return 1; + } + + uint32_t base = 0; + void *cbfsfile = NULL; + + uint32_t type = CBFS_COMPONENT_LZMA_RAW; + if (argc > 5) { + if (intfiletype(argv[5]) != ((uint64_t) - 1)) + type = intfiletype(argv[5]); + else + type = strtoul(argv[5], NULL, 0); + } + if (argc > 6) { + base = strtoul(argv[6], NULL, 0); + } + uint32_t compresssize = filesize; + void *compressed_data; + for (;;) { + compressed_data = malloc(compresssize); + if (! compressed_data) { + printf("Could not allocate %d space\n", compresssize); + return 1; + } + uint32_t actualsize = compresssize; + extern void do_lzma_compress(char *in, int in_len, + char *out, int *out_len); + do_lzma_compress(filedata, filesize, compressed_data, + &compresssize); + if (compresssize <= actualsize) + break; + // Try again with required size. + free(compressed_data); + } + + cbfsfile = create_cbfs_file(cbfsname, compressed_data, + &compresssize, type, &base); + if (add_file_to_cbfs(cbfsfile, compresssize, base)) + return 1; + if (writerom(romname, rom, romsize)) + return 1; + return 0; +} + static int cbfs_create(int argc, char **argv) { char *romname = argv[1]; @@ -249,6 +318,7 @@ {CMD_ADD, "add", cbfs_add}, {CMD_ADD_PAYLOAD, "add-payload", cbfs_add_payload}, {CMD_ADD_STAGE, "add-stage", cbfs_add_stage}, + {CMD_ADD_LZMA, "add-lzma", cbfs_add_lzma}, {CMD_CREATE, "create", cbfs_create}, {CMD_LOCATE, "locate", cbfs_locate}, {CMD_PRINT, "print", cbfs_print} @@ -265,6 +335,7 @@ " add FILE NAME TYPE [base address] Add a component\n" " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" + " add-lzma FILE NAME [TYPE] [base] Lzma compress and add\n" " create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n" " locate FILE NAME ALIGN Find a place for a file of that size\n" " print Show the contents of the ROM\n\n"

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[PATCH] Wait for RTC power well on vt8237r early smbus.
by Kevin O'Connor 06 Sep '10

06 Sep '10

Code must not access the smbus registers before the RTC power well is ready (PSON gating). Some boards boot faster than this power well stabilization, and thus see bad data when accessing the smbus registers. --- src/southbridge/via/vt8237r/vt8237r.h | 1 + src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 9 +++++++++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 54a46f8..d54c533 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -47,6 +47,7 @@ #define IDE_UDMA 0x50 /* SMBus */ +#define VT8237R_PSON 0x82 #define VT8237R_POWER_WELL 0x94 #define VT8237R_SMBUS_IO_BASE_REG 0xd0 #define VT8237R_SMBUS_HOST_CONF 0xd2 diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 357ad81..4372a4a 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -132,12 +132,15 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +#define PSONREADY_TIMEOUT 0x7fffffff + /** * Enable the SMBus on VT8237R-based systems. */ void enable_smbus(void) { device_t dev; + int loops; /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -150,6 +153,12 @@ void enable_smbus(void) die("Power management controller not found\n"); } + /* Make sure the RTC power well is up before touching smbus. */ + loops = 0; + while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) + && loops < PSONREADY_TIMEOUT) + ++loops; + /* * 7 = SMBus Clock from RTC 32.768KHz * 5 = Internal PLL reset from susp -- 1.7.2.2

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Re: [coreboot] CS5536 OHCI not working
by Jens Rottmann 06 Sep '10

06 Sep '10

Hi Peter, >> It's possible that this is more of a problem of your thumb drive >> than of the USB stack. > Indeed. Especially if the drive is actually a high speed device then > frequently it will not work perfectly running at full speed. In the meantime I've tested 1 USB keyboard and 8 storage devices from different vendors (2 card readers, 1 M-Systems uDOC, 5 thumb drives, 1 of which is an ancient USB 1.1 only). None worked. > An interesting data point would be for you to attach the drive when > the system is running Linux, *without* the ehci_hcd driver loaded, > only ohci_hcd. Tried that with the 1st card reader which had made me write the original message. Works with OHCI-only in Linux. Cheers, Jens

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[PATCH] Enable qemu memory range 0xc0000-0xfffff automatically.
by Kevin O'Connor 06 Sep '10

06 Sep '10

Instead of requiring users to modify qemu to allow writes to 0xc0000-0xfffff, have coreboot qemu support enable the memory range at startup. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/mainboard/emulation/qemu-x86/mainboard.c | 41 +++++++++++++++++++++----- 1 files changed, 33 insertions(+), 8 deletions(-) diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c index 7ab02d9..55fc5c3 100644 --- a/src/mainboard/emulation/qemu-x86/mainboard.c +++ b/src/mainboard/emulation/qemu-x86/mainboard.c @@ -10,15 +10,15 @@ /* not sure how these are routed in qemu */ static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; -static void qemu_init(device_t dev) +static void qemu_nb_init(device_t dev) { - /* The VGA OPROM already lives at 0xc0000, - * force coreboot to use it. - */ - dev->on_mainboard = 1; - - /* Now do the usual initialization */ - pci_dev_init(dev); + // Map memory at 0xc0000 - 0xfffff + int i; + uint8_t v = pci_read_config8(dev, 0x59); + v |= 0x30; + pci_write_config8(dev, 0x59, v); + for (i=0; i<6; i++) + pci_write_config8(dev, 0x5a + i, 0x33); /* This sneaked in here, because Qemu does not * emulate a SuperIO chip @@ -32,6 +32,31 @@ static void qemu_init(device_t dev) pci_assign_irqs(0, 3, enetIrqs); } +static struct device_operations nb_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = qemu_nb_init, + .ops_pci = 0, +}; + +static const struct pci_driver nb_driver __pci_driver = { + .ops = &nb_operations, + .vendor = 0x8086, + .device = 0x1237, +}; + +static void qemu_init(device_t dev) +{ + /* The VGA OPROM already lives at 0xc0000, + * force coreboot to use it. + */ + dev->on_mainboard = 1; + + /* Now do the usual initialization */ + pci_dev_init(dev); +} + static struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, -- 1.7.2.2

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Trac reminder: list of new ticket(s)
by coreboot tracker 06 Sep '10

06 Sep '10

1 0

[PATCH] cbfstool default type for add command.
by Kevin O'Connor 06 Sep '10

06 Sep '10

The "raw" type is a good default for the "add" command. Allow the user to add files without specifying a type ("raw" will be assumed). Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- util/cbfstool/cbfstool.c | 16 +++++++--------- 1 files changed, 7 insertions(+), 9 deletions(-) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 7c22a65..311a3e8 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -70,15 +70,13 @@ static int cbfs_add(int argc, char **argv) uint32_t base = 0; void *cbfsfile = NULL; - if (argc < 6) { - printf("not enough arguments to 'add'.\n"); - return 1; + uint32_t type = CBFS_COMPONENT_RAW; + if (argc > 5) { + if (intfiletype(argv[5]) != ((uint64_t) - 1)) + type = intfiletype(argv[5]); + else + type = strtoul(argv[5], NULL, 0); } - uint32_t type; - if (intfiletype(argv[5]) != ((uint64_t) - 1)) - type = intfiletype(argv[5]); - else - type = strtoul(argv[5], NULL, 0); if (argc > 6) { base = strtoul(argv[6], NULL, 0); } @@ -332,7 +330,7 @@ void usage(void) " cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n" " -h Display this help message\n\n" "COMMANDs:\n" - " add FILE NAME TYPE [base address] Add a component\n" + " add FILE NAME [TYPE] [base address] Add a component\n" " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" " add-lzma FILE NAME [TYPE] [base] Lzma compress and add\n" -- 1.7.2.2

1 0

Question about did my MB is supported
by Condor 06 Sep '10

06 Sep '10

Hello all, i read information on the coreboot site but i still doubt did my MB is supported. I expect to run Linux with lilo and Windows 7 32 bit. Here is information for my MB answering questions from FAQ: Will coreboot work on my machine? 1. My board vendor is ASUSTeK, CPU P4 2.8 GHz, no idea for others things :S 2. lspci output: # lspci -tvnn -[0000:00]-+-00.0 Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] +-01.0-[01]----00.0 ATI Technologies Inc RV630 PRO AGP [Radeon HD 2600 PRO AGP] [1002:9587] +-06.0 Intel Corporation 82865G/PE/P Processor to I/O Memory Interface [8086:2576] +-1d.0 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] +-1d.1 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] +-1d.2 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] +-1d.3 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] +-1d.7 Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] +-1e.0-[02]----05.0 Marvell Technology Group Ltd. 88E8001 Gigabit Ethernet Controller [11ab:4320] +-1f.0 Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] +-1f.1 Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] +-1f.2 Intel Corporation 82801EB (ICH5) SATA Controller [8086:24d1] +-1f.3 Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] \-1f.5 Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] 3. IO Chip: Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627THF/THG (id=0x82, rev=0x84) at 0x2e Register dump: idx 20 21 22 23 24 25 26 28 29 2a 2b 2c 2d 2e 2f val 82 84 ff fe e2 00 00 20 00 00 1a 58 20 00 ff def 82 NA ff 00 MM 00 MM 00 00 00 MM MM MM 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 00 04 3c def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 83 def 01 00 60 00 64 01 0c 80 LDN 0x07 (GPIO 1, GPIO 5, game port, MIDI port) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 val 08 02 01 03 30 00 ff ff ff ff d3 00 def 00 02 01 03 30 09 ff 00 00 ff 00 00 LDN 0x08 (GPIO 2) idx 30 f0 f1 f2 f3 f4 f5 f6 f7 val 01 ff 38 00 00 ff 00 00 00 def 00 ff 00 00 00 RR 00 00 00 LDN 0x09 (GPIO 3, GPIO 4) idx 30 f0 f1 f2 f3 f4 f5 f6 val 03 ef 40 00 00 fe 01 00 def 00 ff 00 00 00 ff 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f3 f4 f6 f7 f9 fe ff val 01 00 00 00 ae 04 00 00 00 10 00 af 37 00 00 00 00 00 00 def 00 00 00 00 MM MM 00 00 00 00 00 00 00 00 00 00 00 RR RR LDN 0x0b (Hardware monitor) idx 30 60 61 70 val 01 02 90 00 def 00 00 00 00 4. flashrom -v ./flashrom -V flashrom v0.9.2-r1153 on Linux 2.6.35.4-smp (i686), built with libpci 3.1.5, GCC 4.4.4, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1579M loops per second, 10 myus = 10 us, 100 myus = 94 us, 1000 myus = 1015 us, 10000 myus = 12684 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer Inc." DMI string baseboard-product-name: "P4P800SE" DMI string baseboard-version: "Rev 2.xx" DMI string chassis-type: "<OUT OF SPEC>" Found chipset "Intel ICH5/ICH5R", enabling flash write... chipset PCI ID is 8086:24d0, BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. --- cut --- Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x9d, id2 0x6e Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Probing for Sanyo LF25FW203A, 2048 KB: skipped. --- cut --- 5. URL of my main board: It's seems is very hard to be find but i think is that one: http://support.asus.com/search/search.aspx?keyword=p4p800se&SLanguage=en-us 6. No idea what can be that information. Thank you. Regards, Condor

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[commit] r5775 - in trunk/src/mainboard/lippert: roadrunner-lx spacerunner-lx
by repository service 06 Sep '10

06 Sep '10

Author: myles Date: Fri Sep 3 17:16:36 2010 New Revision: 5775 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5775 Log: Update RoadRunner and SpaceRunner config to get in sync with current standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Modified: trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb Fri Sep 3 16:54:50 2010 (r5774) +++ trunk/src/mainboard/lippert/roadrunner-lx/devicetree.cb Fri Sep 3 17:16:36 2010 (r5775) @@ -48,8 +48,8 @@ irq 0x70 = 7 end device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME irq 0x70 = 9 end device pnp 2e.5 on # PS/2 keyboard @@ -61,8 +61,8 @@ irq 0x70 = 12 end device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - # io 0x64 = 0x1200 + io 0x62 = 0x1220 # Simple I/O + # io 0x64 = 0x1228 # SPI end device pnp 2e.8 off # MIDI io 0x60 = 0x300 Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Fri Sep 3 16:54:50 2010 (r5774) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Fri Sep 3 17:16:36 2010 (r5775) @@ -63,16 +63,15 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) - 0x1E2C, // disable ATXPowerGood - will cause a reboot! - 0x0423, // don't delay POWerOK1/2 - 0x9072, // watchdog triggers POWOK, counts seconds + 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal + 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset + 0x9072, // watchdog triggers PWROK, counts seconds #if !CONFIG_USE_WATCHDOG_ON_BOOT - 0x0073, 0x0074, // disable watchdog by setting timeout to 0 + 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) - 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled - 0x46B8, 0x0CB9, // enable pullups + 0x46B8, 0x0CB9, // enable pullups on RS485_EN 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) 0x26C8, // config GP15,12,11 as output; GP14 as input Modified: trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb Fri Sep 3 16:54:50 2010 (r5774) +++ trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb Fri Sep 3 17:16:36 2010 (r5775) @@ -49,8 +49,8 @@ irq 0x70 = 7 end device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME irq 0x70 = 9 end device pnp 2e.5 on # PS/2 keyboard @@ -62,8 +62,8 @@ irq 0x70 = 12 end device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 + io 0x62 = 0x1220 # Simple I/O + io 0x64 = 0x1228 # SPI end device pnp 2e.8 off # MIDI io 0x60 = 0x300 Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Fri Sep 3 16:54:50 2010 (r5774) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Fri Sep 3 17:16:36 2010 (r5775) @@ -129,16 +129,15 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) - 0x1E2C, // disable ATXPowerGood - 0x0423, // don't delay POWerOK1/2 - 0x9072, // watchdog triggers POWOK, counts seconds + 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal + 0x1423, // don't delay PoWeROK1/2 + 0x9072, // watchdog triggers PWROK, counts seconds #if !CONFIG_USE_WATCHDOG_ON_BOOT - 0x0073, 0x0074, // disable watchdog by setting timeout to 0 + 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) - 0x072C, // VIN6=enabled?, FAN4/5 disabled, VIN7=internal, VIN3=internal - 0x66B8, 0x0CB9, // enable pullups + 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x07C8, // config GP12-10 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55

4 3

filo prompt, how to access usb disk?
by BeBa 05 Sep '10

05 Sep '10

Hi, I just flashed a ga-6bxc and find no way to access its usb sticks. Filo has been compiled with IDE_NEW_DISK and USB_STACK. filo> kernel uda1:/vmlinuz spits out: File not found. I think that the devices are not seen at all. Is there a way to find it out? probe seems to check only IDE stuff, is that true? If so, then hwat else can I try? thanks BeBa

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coreboot September 2010