coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

DIP32 top hat flash
by Tadas S 03 Sep '10

03 Sep '10

These sockets are good because their pins are hard to bend, so I used it on the bottom of the "pie": http://rocky.digikey.com/weblib/Mill-Max/Web%20Photos/110-13-632-41-001000.… This ones pins are easier to bend, so I used them to bend Chip Enable pins. http://www.buyicnow.com/pic/SOCKET/P00001177.jpg If part is deselected (Chip Enable floating), Chip Enable pin should be high, but my flash part doesn't have internal pull-ups, so sometimes during flashing deselected chip was badly flashed. I soldered external 200 kilohm resistors to pull-up both Chip Enable pins. Now it works for me :) I hope someone will have time to update wiki :) Thanks, Tadas

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[PATCH 2/2] Amd_ddr3_mct_InitPhyCompensation
by She, Kerry 03 Sep '10

03 Sep '10

Hello, AMD DDR3 MCT function InitPhyCompensation() compliant with AGESA code. Signed-off-by: Kerry She <Kerry.she(a)amd.com>

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[PATCH 1/2] Amd_ddr2_mct_InitPhyCompensation
by She, Kerry 03 Sep '10

03 Sep '10

Hello, AMD DDR2 MCT function InitPhyCompensation() compliant with AGESA code. Signed-off-by: Kerry She <Kerry.she(a)amd.com>

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[commit] r5773 - trunk/util/inteltool
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 11:36:37 2010 New Revision: 5773 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5773 Log: Add support for dumping ACPI registers for i7 Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/inteltool/powermgt.c Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Fri Sep 3 11:33:50 2010 (r5772) +++ trunk/util/inteltool/powermgt.c Fri Sep 3 11:36:37 2010 (r5773) @@ -21,6 +21,66 @@ #include <stdio.h> #include "inteltool.h" +static const io_register_t ich10_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK + { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 + { 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK + { 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK +#if DANGEROUS_REGISTERS + /* These registers return 0 on read, but reading them may cause + * the system to enter Cx states, which might hang the system. + */ + { 0x14, 1, "LV2 (Mobile)" }, + { 0x15, 1, "LV3 (Mobile)" }, + { 0x16, 1, "LV4 (Mobile)" }, +#endif + { 0x17, 2, "RESERVED" }, + { 0x19, 1, "RESERVED" }, + { 0x1a, 2, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK + { 0x2C, 4, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8 + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control; + { 0x3d, 2, "RESERVED" }, + { 0x3f, 1, "RESERVED" }, + { 0x40, 2, "RESERVED" }, + { 0x42, 1, "GPE_CNTL" }, + { 0x43, 1, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, // Device Activity Status + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK + { 0x51, 1, "RESERVED" }, + { 0x52, 2, "RESERVED" }, + { 0x54, 4, "C3_RES (Mobile)" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 2, "TCO_RLD" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "TCO_TMR" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + static const io_register_t ich9_pm_registers[] = { { 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK { 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2 @@ -473,6 +533,11 @@ printf("\n============= PMBASE ============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH10R: + pmbase = pci_read_word(sb, 0x40) & 0xff80; + pm_registers = ich10_pm_registers; + size = ARRAY_SIZE(ich10_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH:

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[commit] r5772 - trunk/util/inteltool
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 11:33:50 2010 New Revision: 5772 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5772 Log: Add support for dumping RCBA registers for i7 Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/inteltool/rootcmplx.c Modified: trunk/util/inteltool/rootcmplx.c ============================================================================== --- trunk/util/inteltool/rootcmplx.c Fri Sep 3 11:32:17 2010 (r5771) +++ trunk/util/inteltool/rootcmplx.c Fri Sep 3 11:33:50 2010 (r5772) @@ -36,14 +36,15 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_ICH8M: case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: case PCI_DEVICE_ID_INTEL_ICH9R: case PCI_DEVICE_ID_INTEL_ICH9: case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: - case PCI_DEVICE_ID_INTEL_ICH8M: - case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break;

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[commit] r5771 - trunk/util/inteltool
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 11:32:17 2010 New Revision: 5771 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5771 Log: Remove some errant spaces Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/inteltool/pcie.c Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Fri Sep 3 11:31:13 2010 (r5770) +++ trunk/util/inteltool/pcie.c Fri Sep 3 11:32:17 2010 (r5771) @@ -98,17 +98,17 @@ case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; - case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_PM965: case PCI_DEVICE_ID_INTEL_Q965: - case PCI_DEVICE_ID_INTEL_82Q35: - case PCI_DEVICE_ID_INTEL_82G33: - case PCI_DEVICE_ID_INTEL_82Q33: + case PCI_DEVICE_ID_INTEL_82Q35: + case PCI_DEVICE_ID_INTEL_82G33: + case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: - dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; - dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; - break; + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82810: case PCI_DEVICE_ID_INTEL_82810DC: case PCI_DEVICE_ID_INTEL_82810E_MC:

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[commit] r5770 - trunk/util/inteltool
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 11:31:13 2010 New Revision: 5770 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5770 Log: Add DMIBAR support for Intel X58 southbridge Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/inteltool/pcie.c Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Fri Sep 3 10:57:32 2010 (r5769) +++ trunk/util/inteltool/pcie.c Fri Sep 3 11:31:13 2010 (r5770) @@ -114,6 +114,9 @@ case PCI_DEVICE_ID_INTEL_82810E_MC: printf("This northbrigde does not have DMIBAR.\n"); return 1; + case PCI_DEVICE_ID_INTEL_X58: + dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1;

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[commit] r5769 - trunk
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 10:57:32 2010 New Revision: 5769 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5769 Log: Add convenience rules for cscope to Makefile. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Sep 3 10:53:06 2010 (r5768) +++ trunk/Makefile Fri Sep 3 10:57:32 2010 (r5769) @@ -330,6 +330,9 @@ printf "#endif\n" >> $(obj)/build.ht mv $(obj)/build.ht $(obj)/build.h +cscope: + cscope -bR + doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot @@ -354,7 +357,10 @@ clean: clean-for-update rm -f $(obj)/coreboot* .ccwrap -distclean: +clean-cscope: + rm -f cscope.out + +distclean: clean-cscope rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile @@ -383,5 +389,5 @@ @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html $(HOSTCC) -g $(STACK) -Wall -o $@ $< -.PHONY: $(PHONY) clean distclean doxygen doxy coreboot .xcompile +.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy coreboot .xcompile

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[commit] r5768 - in trunk/util/crossgcc: . patches
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 10:53:06 2010 New Revision: 5768 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5768 Log: The current workaround for binutils on mingw (or any non texinfo system) failed. While we're at it, improve DESTDIR handling Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch Modified: trunk/util/crossgcc/buildgcc Modified: trunk/util/crossgcc/buildgcc ============================================================================== --- trunk/util/crossgcc/buildgcc Fri Sep 3 00:02:53 2010 (r5767) +++ trunk/util/crossgcc/buildgcc Fri Sep 3 10:53:06 2010 (r5768) @@ -372,9 +372,6 @@ else printf "Building binutils ${BINUTILS_VERSION} ... " ( - # workaround for building binutils 2.20.1 on MINGW: - touch binutils-${BINUTILS_VERSION}/bfd/doc/bfd.info - # now build binutils cd build-binutils rm -f .failed ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ @@ -394,6 +391,7 @@ printf "Building GCC ${GCC_VERSION} ... " ( cd build-gcc + export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed # GCC does not honour HOSTCFLAGS at all. CFLAGS are used for # both target and host object files. This is pretty misdesigned. @@ -423,7 +421,7 @@ printf "Building GDB ${GDB_VERSION} ... " ( cd build-gdb - export PATH=$PATH:$PREFIX/bin + export PATH=$PATH:$DESTDIR$TARGETDIR/bin rm -f .failed CFLAGS="$HOSTCFLAGS" ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ --without-python --disable-werror --disable-nls Added: trunk/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/crossgcc/patches/binutils-2.20.1_no-bfd-doc.patch Fri Sep 3 10:53:06 2010 (r5768) @@ -0,0 +1,11 @@ +--- binutils-2.20.1/bfd/Makefile.in~ 2010-07-25 10:56:45 +0000 ++++ binutils-2.20.1/bfd/Makefile.in 2010-07-25 10:19:24 +0000 +@@ -320,7 +320,7 @@ + # RELEASE=y + INCDIR = $(srcdir)/../include + CSEARCH = -I. -I$(srcdir) -I$(INCDIR) +-SUBDIRS = doc po ++SUBDIRS = po + bfddocdir = doc + libbfd_la_LDFLAGS = $(am__append_1) -release `cat libtool-soversion` \ + @SHARED_LDFLAGS@ $(am__empty)

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Re: [coreboot] [PATCH] fix 'AMD Fam10 code breaks with gcc 4.5.0'
by Paul Menzel 02 Sep '10

02 Sep '10

Dear Scott, Am Donnerstag, den 02.09.2010, 16:06 -0500 schrieb Scott: > -----Original Message----- > From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Paul Menzel > Sent: Thursday, September 02, 2010 04:11 AM > To: coreboot(a)coreboot.org > Subject: Re: [coreboot] [PATCH] fix 'AMD Fam10 code breaks with gcc 4.5.0' > Am Donnerstag, den 02.09.2010, 10:59 +0200 schrieb Paul Menzel: > > Am Donnerstag, den 02.09.2010, 00:40 -0500 schrieb Scott: > > > > > The subversion comment for -r 5571 states: > > > > > > The AMD Fam10 code breaks with coreboot 4.5.0. > > > Potentially caused by reordering. Going back to 4.4.4 > > > which is known working on Fam10 until gcc or the Fam10 code is fixed. > > > > > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > > > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > > > > > > > > > I encountered the same problem and debugged it. The AP code that disables > > > cache as ram before the final halt has to be all inline. Function calls > > > require a valid stack, and the stack is kept in the very cache as ram that > > > the code is disabling. I found with gcc 450, the code for rdmsr, disable_cache, > > > and enable_cache and not getting inlined as intended. Function calls are > > > > s/and/are/ > > > > > generated, and the first one after the AP clears msr 268 fails. The solution > > > is to force these functions to generate inline code by adding > > > __attribute__((always_inline)) to their declarations: > > > > great find!!! Could you please send a patch according to the development > > guidelines. Especially do not forget to add your Signed-off-by line. > > They are documented in the Wiki [1]. > > > Just to leave no doubt, could you please add that you tested your fix > > using GCC 4.5.0 with the used hardware. > > > > [.] > OK, I resubmitted it. Currently tested on simnow only. I will make a > Tilapia binary and ask the AMD guys to test it. By the way, the patch > file has Windows style line endings. I wonder if others can use it easily... I guess next time this message should go to the list since it contains information interesting to the others too.

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coreboot September 2010