coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

[PATCH] added ich10r gpio support to intel tool
by Warren Turkal 01 Sep '10

01 Sep '10

I have attached a patch for ich10r support for dumping gpio registers. I am looking for comments and a possible committer. Thanks, wt

4 7

build service results for r5761
by repository service 01 Sep '10

01 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "cozzie" checked in revision 5761 to the coreboot repository. This caused the following changes: Change Log: Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5761&device=atc-6220&vendo… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5761 - trunk/util/inteltool
by repository service 01 Sep '10

01 Sep '10

Author: cozzie Date: Wed Sep 1 05:40:57 2010 New Revision: 5761 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5761 Log: Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/util/inteltool/gpio.c Modified: trunk/util/inteltool/gpio.c ============================================================================== --- trunk/util/inteltool/gpio.c Tue Aug 31 21:19:16 2010 (r5760) +++ trunk/util/inteltool/gpio.c Wed Sep 1 05:40:57 2010 (r5761) @@ -152,6 +152,41 @@ { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich10_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "RESERVED" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "RESERVED" }, + { 0x40, 4, "GPIO_USE_SEL3" }, + { 0x44, 4, "GPIO_SEL3" }, + { 0x48, 4, "GPIO_LVL3" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 4, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + { 0x60, 4, "GP_RST_SEL" }, + { 0x64, 4, "RESERVED" }, + { 0x68, 4, "RESERVED" }, + { 0x6c, 4, "RESERVED" }, + { 0x70, 4, "RESERVED" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + int print_gpios(struct pci_dev *sb) { int i, size; @@ -161,6 +196,11 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH10R: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich10_gpio_registers; + size = ARRAY_SIZE(ich10_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH9DH: case PCI_DEVICE_ID_INTEL_ICH9DO: case PCI_DEVICE_ID_INTEL_ICH9R:

1 0

via pc3500g
by illdred 01 Sep '10

01 Sep '10

Good day, I would like to use coreboot on my machine. I have a VIA PC3500G motherboard. VIA C7 cpu, VIA CN896 northbirdge, VIA 8237A southbridge Will it work? looks to me like the only unsupported piece is the northbridge. lspci -tvnn -+-[0000:80]---01.0 VIA Technologies, Inc. VT1708/A [Azalia HDAC] (VIA High Definition Audio Controller) [1106:3288] \-[0000:00]-+-00.0 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:0364] +-00.1 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:1364] +-00.2 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:2364] +-00.3 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:3364] +-00.4 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:4364] +-00.5 VIA Technologies, Inc. CN896/VN896/P4M900 I/O APIC Interrupt Controller [1106:5364] +-00.6 VIA Technologies, Inc. CN896/VN896/P4M900 Security Device [1106:6364] +-00.7 VIA Technologies, Inc. CN896/VN896/P4M900 Host Bridge [1106:7364] +-01.0-[01]-- +-02.0-[02]--+-00.0 ATI Technologies Inc RV610 video device [Radeon HD 2400 PRO] [1002:94c3] | \-00.1 ATI Technologies Inc RV610 audio device [Radeon HD 2400 PRO] [1002:aa10] +-03.0-[03]-- +-0f.0 VIA Technologies, Inc. Device [1106:5337] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237A PCI to ISA Bridge [1106:3337] +-11.7 VIA Technologies, Inc. VT8251 Ultra VLINK Controller [1106:287e] +-13.0 VIA Technologies, Inc. VT8237A Host Bridge [1106:337b] \-13.1-[04-05]--+-04.0-[05]--+-00.0 ATI Technologies Inc RV 610LE PCI [Radeon HD 2400] [1002:94cc] | \-00.1 ATI Technologies Inc RV610 audio device [Radeon HD 2400 PRO] [1002:aa10] \-0e.0 VIA Technologies, Inc. VT6102 [Rhine-II] [1106:3065] superiotool -dV superiotool r5728 Probing for ...<snip> Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 01 10 1e 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 00 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 00 02 48 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 01 00 00 00 00 81 1f 00 00 08 00 08 20 00 01 00 38 00 00 00 00 00 00 00 60 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 08 03 00 00 3f 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 flashrom -V flashrom v0.9.2-r1001 on Linux 2.6.33-dirigible33 (i686), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease) flashrom is free software, get the source code at http://www.flashrom.org Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "PC1" DMI string baseboard-product-name: "PC3500G" DMI string baseboard-version: "3.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, id 8716 Found chipset "VIA VT8237A", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff enabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled Serial flash pin 29 Serial flash port 0x0820 Calibrating delay loop... 387M loops per second, delay more than 10% too short, recalculating... 381M loops per second, delay more than 10% too short, recalculating... 434M loops per second, delay more than 10% too short, recalculating... 436M loops per second, delay more than 10% too short, recalculating... 436M loops per second, delay loop is unreliable, trying to continue 10 myus = 10 us, 100 myus = 89 us, 1000 myus = 873 us, 10000 myus = 31905 us, OK. <snip> Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L4005" (512 KB, SPI) at physical address 0xfff80000. <snip> === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! ===

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2010