coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

util directory
by ali hagigat 03 Sep '10

03 Sep '10

Inside util/abuild we have two files: abuild and abuild.1 What language do they have written with? What is their functions in short? Are they necessary for building a coreboot image?

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build service results for r5767
by repository service 03 Sep '10

03 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5767 to the coreboot repository. This caused the following changes: Change Log: Fix compilation for mtarvon. CAR initialization does early_mtrr_init, jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of intel:mtarvon has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5767 - trunk/src/mainboard/intel/mtarvon
by repository service 03 Sep '10

03 Sep '10

Author: myles Date: Fri Sep 3 00:02:53 2010 New Revision: 5767 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5767 Log: Fix compilation for mtarvon. CAR initialization does early_mtrr_init, jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/intel/mtarvon/romstage.c Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Thu Sep 2 22:30:31 2010 (r5766) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Sep 3 00:02:53 2010 (r5767) @@ -33,7 +33,6 @@ #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include "superio/intel/i3100/i3100.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/i3100_early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" @@ -52,10 +51,11 @@ #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" -#include "../jarrell/debug.c" +#if 0 /* skip_romstage doesn't compile with gcc */ #include "arch/i386/lib/stages.c" +#endif -static void main(unsigned long bist) +void main(unsigned long bist) { msr_t msr; u16 perf; @@ -72,11 +72,12 @@ }; if (bist == 0) { +#if 0 /* skip_romstage doesn't compile with gcc */ /* Skip this if there was a built in self test failure */ - early_mtrr_init(); if (memory_initialized()) { skip_romstage(); } +#endif } /* Set up the console */ i3100_enable_superio();

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build service results for r5766
by repository service 02 Sep '10

02 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5766 to the coreboot repository. This caused the following changes: Change Log: Trivial warning fix for adl855pc. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of digitallogic:adl855pc has been fixed Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5766&device=mtarvon&vendor… Compilation of lanner:em8510 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5766 - trunk/src/northbridge/intel/i855
by repository service 02 Sep '10

02 Sep '10

Author: myles Date: Thu Sep 2 22:30:31 2010 New Revision: 5766 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5766 Log: Trivial warning fix for adl855pc. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/northbridge/intel/i855/raminit.c Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Thu Sep 2 20:36:29 2010 (r5765) +++ trunk/src/northbridge/intel/i855/raminit.c Thu Sep 2 22:30:31 2010 (r5766) @@ -872,10 +872,14 @@ static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value) { +#if CONFIG_DEBUG_RAM_SETUP u32 value1 = pci_read_config32(ctrl->d0, reg); +#endif pci_write_config32(ctrl->d0, reg, new_value); +#if CONFIG_DEBUG_RAM_SETUP u32 value2 = pci_read_config32(ctrl->d0, reg); PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2); +#endif } /* if ram still doesn't work do this function */

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build service results for r5765
by repository service 02 Sep '10

02 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5765 to the coreboot repository. This caused the following changes: Change Log: Fix abuild to build all boards. Revision 5754 changed the way vendors and boards were specified in Kconfig, and abuild depended on that. Since that rev it has only built qemu. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5765&device=adl855pc&vendo… Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5765&device=mtarvon&vendor… Compilation of lanner:em8510 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5765&device=em8510&vendor=… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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revision 5762 change causing AMD Tilapia build to fail
by Scott 02 Sep '10

02 Sep '10

Hello, The include file change of rev 5762 is causing the AMD Tilapia build to fail for me. The work-around I found is to add: #include <option_table.h> to src/cpu/amd/quadcore/quadcore.c. Thanks, Scott

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build service results for r5764
by repository service 02 Sep '10

02 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5764 to the coreboot repository. This caused the following changes: Change Log: Revert 5762. It silently broke a lot of boards because abuild was broken. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5764&device=atc-6220&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5765 - trunk/util/abuild
by repository service 02 Sep '10

02 Sep '10

Author: myles Date: Thu Sep 2 20:36:29 2010 New Revision: 5765 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5765 Log: Fix abuild to build all boards. Revision 5754 changed the way vendors and boards were specified in Kconfig, and abuild depended on that. Since that rev it has only built qemu. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/util/abuild/abuild Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Thu Sep 2 20:29:31 2010 (r5764) +++ trunk/util/abuild/abuild Thu Sep 2 20:36:29 2010 (r5765) @@ -166,9 +166,9 @@ else printf " Creating config file... " xml " <config>autogenerated</config>" - grep "depends[\t ]on[\t ]*VENDOR" src/mainboard/$VENDOR/$MAINBOARD/../Kconfig | \ + grep "if[\t ]*VENDOR" src/mainboard/$VENDOR/$MAINBOARD/../Kconfig | \ sed "s,^.*$VENDOR_.*$[^A-Z0-9_]*,CONFIG_\1=y," > .config - grep "config[\t ]*BOARD" src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \ + grep "if[\t ]*BOARD" src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \ sed "s,^.*$BOARD_.*$[^A-Z0-9_]*,CONFIG_\1=y," >> .config grep "select[\t ]*ARCH" src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \ sed "s,^.*$ARCH_.*$[^A-Z0-9_]*,CONFIG_\1=y," >> .config

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[commit] r5764 - in trunk/src: include/pc80 mainboard/amd/dbm690t pc80
by repository service 02 Sep '10

02 Sep '10

Author: myles Date: Thu Sep 2 20:29:31 2010 New Revision: 5764 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5764 Log: Revert 5762. It silently broke a lot of boards because abuild was broken. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/include/pc80/mc146818rtc.h trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/pc80/Makefile.inc trunk/src/pc80/mc146818rtc.c trunk/src/pc80/mc146818rtc_early.c Modified: trunk/src/include/pc80/mc146818rtc.h ============================================================================== --- trunk/src/include/pc80/mc146818rtc.h Wed Sep 1 23:03:03 2010 (r5763) +++ trunk/src/include/pc80/mc146818rtc.h Thu Sep 2 20:29:31 2010 (r5764) @@ -81,6 +81,14 @@ #define PC_CKS_RANGE_END 45 #define PC_CKS_LOC 46 +/* coreboot cmos checksum is usually only built over bytes 49..125 + * LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined + * in option_table.h + */ +#if CONFIG_HAVE_OPTION_TABLE +#include <option_table.h> +#endif + #ifndef UTIL_BUILD_OPTION_TABLE #include <arch/io.h> static inline unsigned char cmos_read(unsigned char addr) Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Wed Sep 1 23:03:03 2010 (r5763) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Thu Sep 2 20:29:31 2010 (r5764) @@ -25,6 +25,12 @@ string default amd/dbm690t +# This is a temporary fix, and should be removed when the race condition for +# building option_table.h is fixed. +config WARNINGS_ARE_ERRORS + bool + default n + config DCACHE_RAM_BASE hex default 0xc8000 Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Wed Sep 1 23:03:03 2010 (r5763) +++ trunk/src/pc80/Makefile.inc Thu Sep 2 20:29:31 2010 (r5764) @@ -8,4 +8,3 @@ subdirs-y += vga $(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H) -$(obj)/pc80/mc146818rtc_early.initobj.o : $(OPTION_TABLE_H) Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Wed Sep 1 23:03:03 2010 (r5763) +++ trunk/src/pc80/mc146818rtc.c Thu Sep 2 20:29:31 2010 (r5764) @@ -2,9 +2,6 @@ #include <pc80/mc146818rtc.h> #include <boot/coreboot_tables.h> #include <string.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif /* control registers - Moto names */ Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Wed Sep 1 23:03:03 2010 (r5763) +++ trunk/src/pc80/mc146818rtc_early.c Thu Sep 2 20:29:31 2010 (r5764) @@ -1,10 +1,6 @@ #include <pc80/mc146818rtc.h> #include <fallback.h> -#if CONFIG_USE_OPTION_TABLE -#include <option_table.h> -#endif - #ifndef CONFIG_MAX_REBOOT_CNT #error "CONFIG_MAX_REBOOT_CNT not defined" #endif

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coreboot September 2010