coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

[inteltool] renamed in bridgetool, added support of other non-Intel chipsets.
by Антон Кочков 05 Sep '10

05 Sep '10

inteltool: renamed in bridgetool, added support of other chipsets. Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> ---

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--divide!! and .xcompile
by ali hagigat 05 Sep '10

05 Sep '10

I found the following variable in .xcompile: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none It seems that there is no definition of --divide option for GNU assembler. What is it supposed to do?

4 11

[commit] r5777 - trunk/src/northbridge/amd/amdmct/mct_ddr3
by repository service 05 Sep '10

05 Sep '10

Author: zbao Date: Sun Sep 5 07:52:33 2010 New Revision: 5777 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5777 Log: Trivial. Currently the max frequency is preset as 400Mhz. We need to set a platform specific value. Before that, we can set it manually if the boards need to run in a higher frequency, which has been tested on Tilapia. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Sat Sep 4 08:13:02 2010 (r5776) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Sun Sep 5 07:52:33 2010 (r5777) @@ -1295,6 +1295,7 @@ * Specific information. Return the least of these three in * DCTStatStruc.PresetmaxFreq. */ + /* TODO: Set the proper max frequency in wrappers/mcti_d.c. */ u16 proposedFreq; u16 word;

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ABIT IP35-E flashrom read success, hardware info
by Антон Кочков 04 Sep '10

04 Sep '10

2 1

[commit] r5776 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 04 Sep '10

04 Sep '10

Author: oxygene Date: Sat Sep 4 08:13:02 2010 New Revision: 5776 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5776 Log: AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Sep 3 17:16:36 2010 (r5775) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Sat Sep 4 08:13:02 2010 (r5776) @@ -3461,9 +3461,10 @@ i = 0; /* use i for the dct setting required */ if (pDCTstat->MAdimms[0] < 4) i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) + if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { dword &= 0xF18FFF18; index_reg = 0x98; /* force dct = 0 */ + } } Set_NB32_index_wait(dev, index_reg, 0x0a, dword); Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Sep 3 17:16:36 2010 (r5775) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Sat Sep 4 08:13:02 2010 (r5776) @@ -3127,9 +3127,10 @@ i = 0; /* use i for the dct setting required */ if (pDCTstat->MAdimms[0] < 4) i = 1; - if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) + if (((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) && (pDCTstat->MAdimms[i] == 4)) { dword &= 0xF18FFF18; index_reg = 0x98; /* force dct = 0 */ + } } Set_NB32_index_wait(dev, index_reg, 0x0a, dword);

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CS5536 OHCI not working
by Jens Rottmann 04 Sep '10

04 Sep '10

Hi, is OHCI / USB storage support supposed to be working or is this still very early experimental stuff? If it's known to work only on few supported chipsets yet, then never mind, just ignore me, we don't actually need this, I just fancied giving it a try. But if it's supposed to be mostly working now, you might be interested to hear that this is all I'm getting: FILO version 0.6.0 (root@jensrv) Fri Sep 3 16:49:08 CEST 2010 00:0f.5 2095:1022.5 EHCI controller Not supported. 00:0f.4 2094:1022.4 OHCI controller OHCI Version 1.0 fullspeed device doing control transfer with 0. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8c0, condition: f doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8d0, condition: f doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8d0, condition: f device 0x0951:0x160b is USB 2.0 doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8d0, condition: f doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8d0, condition: f doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8c0, condition: f (MSC) it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out doing control transfer with 1. first_td at f6bf8a0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8d0, condition: f has 1 luns Waiting for device to become ready... bulk: 1f bytes from 233035, finalize: 0, maxpacketsize: 40 doing bulk transfer with 1(2). first_td at f6bf8a0, last f6bf8b0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f bulk: d bytes from 233028, finalize: 1, maxpacketsize: 40 doing bulk transfer with 1(1). first_td at f6bf8a0, last f6bf8b0 intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 0; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f intst: 44; ctrl: b4; cmdst: 4; head: f6bf8a0 -> f6bf8b0, tail: f6bf8b0, condition: f [ ... continues infinitely ... ] I added a counter forcing the loop @ libpayload/drivers/usb/ohci.c:206 to break after 50 repetitions, but this didn't get me anywhere: in the end USB storage would report a complete bogus nr of sectors for my thumb drive. I'd like to be more helpful, but I don't have a clue what this loop is for, or what wait_for_ed() does or who this Ed person is anyway. ;-) Cheers, Jens

3 2

guidance needed with GA-6BXC rev 2.0
by BeBa 03 Sep '10

03 Sep '10

Hi, I have never used coreboot before and would like to try it out with ga-6BXC. According to the wiki (http://www.coreboot.org/GIGABYTE_GA-6BXC) one needs nothing special to get coreboot going with this board. First, I will use my other computer with amd64 bit gentoo distro to build coreboot with a payload. should I do anything special to the 'make' command in coreboot in order for it to work in ga-6BXC which is equipped with a 32bit proccesor? thanks for any answers BenBa

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[PATCH] sync Road-/SpaceRunner with current standard BIOSes
by Jens Rottmann 03 Sep '10

03 Sep '10

Update RoadRunner and SpaceRunner config to get in sync with current standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- --- src/mainboard/lippert/roadrunner-lx/devicetree.cb (rev 5767) +++ src/mainboard/lippert/roadrunner-lx/devicetree.cb (working copy) @@ -48,8 +48,8 @@ irq 0x70 = 7 end device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME irq 0x70 = 9 end device pnp 2e.5 on # PS/2 keyboard @@ -61,8 +61,8 @@ irq 0x70 = 12 end device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - # io 0x64 = 0x1200 + io 0x62 = 0x1220 # Simple I/O + # io 0x64 = 0x1228 # SPI end device pnp 2e.8 off # MIDI io 0x60 = 0x300 --- src/mainboard/lippert/roadrunner-lx/romstage.c (rev 5767) +++ src/mainboard/lippert/roadrunner-lx/romstage.c (working copy) @@ -63,16 +63,15 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) - 0x1E2C, // disable ATXPowerGood - will cause a reboot! - 0x0423, // don't delay POWerOK1/2 - 0x9072, // watchdog triggers POWOK, counts seconds + 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal + 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset + 0x9072, // watchdog triggers PWROK, counts seconds #if !CONFIG_USE_WATCHDOG_ON_BOOT - 0x0073, 0x0074, // disable watchdog by setting timeout to 0 + 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins 0xBF27, 0xFF28, 0x2529, // (GP36=FAN_CTL3, GP13=PWROK1) - 0x1E2C, // VIN6=enabled?, FAN4/5 enabled, VIN7=internal, VIN3=enabled - 0x46B8, 0x0CB9, // enable pullups + 0x46B8, 0x0CB9, // enable pullups on RS485_EN 0x36C0, // enable Simple-I/O for GP15,14,12,11= LIVE_LED, WD_ACTIVE, RS485_EN2,1 0xFFC3, // enable Simple-I/O for GP47-40 (GPIOs on Supervisory Connector) 0x26C8, // config GP15,12,11 as output; GP14 as input --- src/mainboard/lippert/spacerunner-lx/devicetree.cb (rev 5767) +++ src/mainboard/lippert/spacerunner-lx/devicetree.cb (working copy) @@ -49,8 +49,8 @@ irq 0x70 = 7 end device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME irq 0x70 = 9 end device pnp 2e.5 on # PS/2 keyboard @@ -62,8 +62,8 @@ irq 0x70 = 12 end device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 + io 0x62 = 0x1220 # Simple I/O + io 0x64 = 0x1228 # SPI end device pnp 2e.8 off # MIDI io 0x60 = 0x300 --- src/mainboard/lippert/spacerunner-lx/romstage.c (rev 5767) +++ src/mainboard/lippert/spacerunner-lx/romstage.c (working copy) @@ -129,16 +129,15 @@ static const u16 sio_init_table[] = { // hi=data, lo=index 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) - 0x1E2C, // disable ATXPowerGood - 0x0423, // don't delay POWerOK1/2 - 0x9072, // watchdog triggers POWOK, counts seconds + 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal + 0x1423, // don't delay PoWeROK1/2 + 0x9072, // watchdog triggers PWROK, counts seconds #if !CONFIG_USE_WATCHDOG_ON_BOOT - 0x0073, 0x0074, // disable watchdog by setting timeout to 0 + 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0 #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) - 0x072C, // VIN6=enabled?, FAN4/5 disabled, VIN7=internal, VIN3=internal - 0x66B8, 0x0CB9, // enable pullups + 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED 0x07C8, // config GP12-10 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 _

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[PATCH] libpayload: scan all PCI functions for USB
by Jens Rottmann 03 Sep '10

03 Sep '10

The AMD CS5536's USB controllers are located at device 0F, functions 4 and 5. They're not found if only function 0 is checked. So if a device exists at all, try all its functions. usb_controller_initialize() will silently skip all device classes != 0C03. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- --- payloads/libpayload/drivers/usb/usbinit.c (rev 5767) +++ payloads/libpayload/drivers/usb/usbinit.c (working copy) @@ -126,7 +126,7 @@ */ for (bus = 0; bus < 256; bus++) for (dev = 0; dev < 32; dev++) - if (pci_read_config32 (PCI_DEV(bus, dev, 0), 8) >> 16 == 0x0c03) + if (pci_read_config16(PCI_DEV(bus, dev, 0), 10) != 0xFFFF) for (func = 7; func >= 0 ; func--) usb_controller_initialize (bus, dev, func); usb_poll(); _

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[commit] r5774 - trunk/payloads/libpayload/drivers/usb
by repository service 03 Sep '10

03 Sep '10

Author: oxygene Date: Fri Sep 3 16:54:50 2010 New Revision: 5774 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5774 Log: The AMD CS5536's USB controllers are located at device 0F, functions 4 and 5. They're not found if only function 0 is checked. So if a device exists at all, try all its functions. usb_controller_initialize() will silently skip all device classes != 0C03. (changed to continue to use 32bit accesses -pg) Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/payloads/libpayload/drivers/usb/usbinit.c Modified: trunk/payloads/libpayload/drivers/usb/usbinit.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/usbinit.c Fri Sep 3 11:36:37 2010 (r5773) +++ trunk/payloads/libpayload/drivers/usb/usbinit.c Fri Sep 3 16:54:50 2010 (r5774) @@ -126,7 +126,7 @@ */ for (bus = 0; bus < 256; bus++) for (dev = 0; dev < 32; dev++) - if (pci_read_config32 (PCI_DEV(bus, dev, 0), 8) >> 16 == 0x0c03) + if (pci_read_config32 (PCI_DEV(bus, dev, 0), 8) >> 16 != 0xffff) for (func = 7; func >= 0 ; func--) usb_controller_initialize (bus, dev, func); usb_poll();

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coreboot September 2010