coreboot September 2010

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[commit] r5784 - trunk/src/devices/oprom
by repository service 07 Sep '10

07 Sep '10

Author: myles Date: Wed Sep 8 01:27:59 2010 New Revision: 5784 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5784 Log: My Jmicron SATA card depends on the BIOS not clearing AL when setting AH. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/devices/oprom/x86_interrupts.c Modified: trunk/src/devices/oprom/x86_interrupts.c ============================================================================== --- trunk/src/devices/oprom/x86_interrupts.c Wed Sep 8 00:30:15 2010 (r5783) +++ trunk/src/devices/oprom/x86_interrupts.c Wed Sep 8 01:27:59 2010 (r5784) @@ -99,7 +99,8 @@ } if (dev) { unsigned short busdevfn; - regs->eax = 0; + regs->eax &= 0xffff00ff; /* Clear AH */ + regs->eax |= PCIBIOS_SUCCESSFUL; // busnum is an unsigned char; // devfn is an int, so we mask it off. busdevfn = (dev->bus->secondary << 8) @@ -108,7 +109,8 @@ regs->ebx = busdevfn; retval = 0; } else { - regs->eax = PCIBIOS_NODEV; + regs->eax &= 0xffff00ff; /* Clear AH */ + regs->eax |= PCIBIOS_NODEV; retval = -1; } break; @@ -125,7 +127,8 @@ if (!dev) { printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); // Or are we supposed to return PCIBIOS_NODEV? - regs->eax = PCIBIOS_BADREG; + regs->eax &= 0xffff00ff; /* Clear AH */ + regs->eax |= PCIBIOS_BADREG; retval = -1; return retval; } @@ -160,11 +163,14 @@ printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func, bus, devfn, reg, regs->ecx); #endif - regs->eax = 0; + regs->eax &= 0xffff00ff; /* Clear AH */ + regs->eax |= PCIBIOS_SUCCESSFUL; retval = 0; break; default: printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); + regs->eax &= 0xffff00ff; /* Clear AH */ + regs->eax |= PCIBIOS_UNSUPPORTED; retval = -1; break; }

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[commit] r5782 - in trunk/src/mainboard/lippert: . literunner-lx
by repository service 07 Sep '10

07 Sep '10

Author: myles Date: Tue Sep 7 19:33:17 2010 New Revision: 5782 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5782 Log: Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/src/mainboard/lippert/literunner-lx/ - copied from r5781, trunk/src/mainboard/lippert/spacerunner-lx/ Modified: trunk/src/mainboard/lippert/Kconfig trunk/src/mainboard/lippert/literunner-lx/Kconfig trunk/src/mainboard/lippert/literunner-lx/chip.h trunk/src/mainboard/lippert/literunner-lx/devicetree.cb trunk/src/mainboard/lippert/literunner-lx/irq_tables.c trunk/src/mainboard/lippert/literunner-lx/mainboard.c trunk/src/mainboard/lippert/literunner-lx/romstage.c Modified: trunk/src/mainboard/lippert/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/Kconfig Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/Kconfig Tue Sep 7 19:33:17 2010 (r5782) @@ -5,6 +5,8 @@ config BOARD_LIPPERT_FRONTRUNNER bool "Cool Frontrunner" +config BOARD_LIPPERT_LITERUNNER_LX + bool "Cool LiteRunner-LX" config BOARD_LIPPERT_ROADRUNNER_LX bool "Cool RoadRunner-LX" config BOARD_LIPPERT_SPACERUNNER_LX @@ -13,6 +15,7 @@ endchoice source "src/mainboard/lippert/frontrunner/Kconfig" +source "src/mainboard/lippert/literunner-lx/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" Modified: trunk/src/mainboard/lippert/literunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/Kconfig Tue Sep 7 19:33:17 2010 (r5782) @@ -1,4 +1,4 @@ -if BOARD_LIPPERT_SPACERUNNER_LX +if BOARD_LIPPERT_LITERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -18,27 +18,28 @@ config MAINBOARD_DIR string - default lippert/spacerunner-lx + default lippert/literunner-lx config MAINBOARD_PART_NUMBER string - default "Cool SpaceRunner-LX" + default "Cool LiteRunner-LX" config IRQ_SLOT_COUNT int - default 7 + default 5 config ONBOARD_UARTS_RS485 - bool "Switch on-board serial ports to RS485" + bool "Switch on-board serial ports 1 & 2 to RS485" default n help - If selected, both on-board serial ports will operate in RS485 mode - instead of RS232. + If selected, the first two on-board serial ports will operate in RS485 + mode instead of RS232. config ONBOARD_IDE_SLAVE - bool "Make on-board SSD act as Slave" + bool "Make on-board CF socket act as Slave" default n help - If selected, the on-board SSD will act as IDE Slave instead of Master. + If selected, the on-board Compact Flash card socket will act as IDE + Slave instead of Master. -endif # BOARD_LIPPERT_SPACERUNNER_LX +endif # BOARD_LIPPERT_LITERUNNER_LX Modified: trunk/src/mainboard/lippert/literunner-lx/chip.h ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/chip.h Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/chip.h Tue Sep 7 19:33:17 2010 (r5782) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/mainboard/lippert/literunner-lx/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/devicetree.cb Tue Sep 7 19:33:17 2010 (r5782) @@ -8,27 +8,24 @@ # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010 + register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash register "enable_USBP4_device" = "0" # 0:host, 1:device register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" + register "com1_enable" = "1" register "com1_address" = "0x3E8" register "com1_irq" = "6" register "com2_enable" = "0" register "com2_address" = "0x2E8" register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 - register "unwanted_vpci[1]" = "0" # End of list has a zero - device pci 8.0 on end # Slot4 - device pci 9.0 on end # Slot3 - device pci a.0 on end # Slot2 - device pci b.0 on end # Slot1 + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci 8.0 on end # Ethernet 2 device pci c.0 on end # IT8888 - device pci e.0 on end # Ethernet + device pci d.0 on end # Mini-PCI + device pci e.0 on end # Ethernet 1 device pci f.0 on # ISA Bridge chip superio/ite/it8712f device pnp 2e.0 off # Floppy @@ -76,7 +73,7 @@ end end device pci f.2 on end # IDE - device pci f.3 off end # Audio + device pci f.3 on end # Audio device pci f.4 on end # OHCI device pci f.5 on end # EHCI end Modified: trunk/src/mainboard/lippert/literunner-lx/irq_tables.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/irq_tables.c Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/irq_tables.c Tue Sep 7 19:33:17 2010 (r5782) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on irq_tables.c from AMD's DB800 mainboard. */ +/* Based on irq_tables.c from the SpaceRunner-LX mainboard. */ #include <arch/pirq_routing.h> #include <console/console.h> @@ -55,17 +55,15 @@ 0x002B, /* Device */ 0, /* Crap (miniport) */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xB8, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ - {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ - {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ - {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ - {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* Mini-PCI */ } }; Modified: trunk/src/mainboard/lippert/literunner-lx/mainboard.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/mainboard.c Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/mainboard.c Tue Sep 7 19:33:17 2010 (r5782) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on mainboard.c from AMD's DB800 mainboard. */ +/* Based on mainboard.c from the SpaceRunner-LX mainboard. */ #include <stdlib.h> #include <stdint.h> @@ -36,6 +36,9 @@ #define SIO_GP1X_CONFIG 0x01 #endif +/* Bit0 enables COM3's transceiver, bit1 disables the RS485 receiver (e.g. for IR). */ +#define SIO_GP2X_CONFIG 0x00 + static const u16 ec_init_table[] = { /* hi=data, lo=index */ 0x1900, /* Enable monitoring */ 0x3050, /* VIN4,5 enabled */ @@ -49,7 +52,7 @@ static void init(struct device *dev) { unsigned int gpio_base, i; - printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX ENTER %s\n", __func__); + printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX ENTER %s\n", __func__); /* Init CS5536 GPIOs */ gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, @@ -73,8 +76,10 @@ /* bit2 = RS485_EN2, bit1 = RS485_EN1, bit0 = Live LED */ outb(SIO_GP1X_CONFIG, 0x1220); /* Simple-I/O GP17-10 */ + /* bit1 = COM3_RX_EN, bit0 = COM3_TX_EN */ + outb(SIO_GP2X_CONFIG, 0x1221); /* Simple-I/O GP27-20 */ - printk(BIOS_DEBUG, "LiPPERT SpaceRunner-LX EXIT %s\n", __func__); + printk(BIOS_DEBUG, "LiPPERT LiteRunner-LX EXIT %s\n", __func__); } static void enable_dev(struct device *dev) @@ -83,6 +88,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("LiPPERT SpaceRunner-LX Mainboard") + CHIP_NAME("LiPPERT LiteRunner-LX Mainboard") .enable_dev = enable_dev, }; Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Sep 7 11:18:08 2010 (r5781) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Tue Sep 7 19:33:17 2010 (r5782) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 LiPPERT Embedded Computers GmbH + * Copyright (C) 2010 LiPPERT Embedded Computers GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Based on romstage.c from AMD's DB800 and DBM690T mainboards. */ +/* Based on romstage.c from the SpaceRunner-LX mainboard. */ #include <stdlib.h> #include <stdint.h> @@ -40,7 +40,7 @@ #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ +/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 #else @@ -137,9 +137,12 @@ #endif 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins 0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1) - 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN + 0x66B8, 0x0FB9, // enable pullups on SPI, RS485_EN, COM3_R/TX_EN 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED + 0x03C1, // enable Simple-I/O for GP21-20= COM3_RX_EN,TX_EN + 0xFFC2, // enable Simple-I/O for GP37-30 0x07C8, // config GP12-10 as output + 0x03C9, // config GP21-20 as output 0x2DF5, // map Hw Monitor Thermal Output to GP55 0x08F8, // map GP LED Blinking 1 to GP10=LIVE_LED (deactivate Simple I/O to use) };

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Re: [coreboot] [commit] r5778 - trunk/src/mainboard/emulation/qemu-x86
by Jens Rottmann 07 Sep '10

07 Sep '10

Hi, something went wrong with commit r5778, it's the wrong commit description and I definitely never signed off this patch. Regards, Jens

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[commit] r5781 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh mainboard/gi...
by repository service 07 Sep '10

07 Sep '10

Author: oxygene Date: Tue Sep 7 11:18:08 2010 New Revision: 5781 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5781 Log: Remove unused ide0_enable and sata0_enable entries from SB7xx and SB600. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/mahogany/devicetree.cb trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb trunk/src/mainboard/asrock/939a785gmh/devicetree.cb trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb trunk/src/mainboard/jetway/pa78vm5/devicetree.cb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/southbridge/amd/sb600/chip.h trunk/src/southbridge/amd/sb600/sb600_ide.c trunk/src/southbridge/amd/sb700/chip.h Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -106,8 +106,6 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/mainboard/amd/mahogany/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/mahogany/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/amd/mahogany/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -106,10 +106,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/amd/mahogany_fam10/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -97,10 +97,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -68,9 +68,6 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -98,10 +98,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -116,10 +116,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/gigabyte/ma785gmt/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -98,10 +98,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -97,10 +97,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/jetway/pa78vm5/devicetree.cb ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/jetway/pa78vm5/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -97,10 +97,7 @@ end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb700 end # device pci 18.0 Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb ============================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -110,8 +110,6 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "hda_viddid" = "0x10ec0888" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -106,8 +106,6 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb Tue Sep 7 11:18:08 2010 (r5781) @@ -106,8 +106,6 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/southbridge/amd/sb600/chip.h ============================================================================== --- trunk/src/southbridge/amd/sb600/chip.h Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/southbridge/amd/sb600/chip.h Tue Sep 7 11:18:08 2010 (r5781) @@ -22,8 +22,6 @@ struct southbridge_amd_sb600_config { - u32 ide0_enable : 1; - u32 sata0_enable : 1; u32 hda_viddid; }; struct chip_operations; Modified: trunk/src/southbridge/amd/sb600/sb600_ide.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_ide.c Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/southbridge/amd/sb600/sb600_ide.c Tue Sep 7 11:18:08 2010 (r5781) @@ -26,11 +26,9 @@ static void ide_init(struct device *dev) { - struct southbridge_amd_sb600_config *conf; /* Enable ide devices so the linux ide driver will work */ u32 dword; u8 byte; - conf = dev->chip_info; /* RPR10.1 disable MSI */ dword = pci_read_config32(dev, 0x70); Modified: trunk/src/southbridge/amd/sb700/chip.h ============================================================================== --- trunk/src/southbridge/amd/sb700/chip.h Tue Sep 7 09:53:26 2010 (r5780) +++ trunk/src/southbridge/amd/sb700/chip.h Tue Sep 7 11:18:08 2010 (r5781) @@ -22,10 +22,7 @@ struct southbridge_amd_sb700_config { - u32 ide0_enable : 1; - u32 sata0_enable : 1; u32 boot_switch_sata_ide : 1; - u32 hda_viddid; }; struct chip_operations; extern struct chip_operations southbridge_amd_sb700_ops;

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Re: [coreboot] [PATCH 3/4] Reduce TSC calibrations from 20ms to 2ms.
by Patrick Georgi 07 Sep '10

07 Sep '10

Am 07.09.2010 01:24, schrieb Kevin O'Connor: > 2ms is enough time to accurately obtain the clock rate. > > Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> In as r5780 Thanks, Patrick

1 0

[commit] r5780 - trunk/src/cpu/x86/tsc
by repository service 07 Sep '10

07 Sep '10

Author: oxygene Date: Tue Sep 7 09:53:26 2010 New Revision: 5780 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5780 Log: 2ms is enough time to accurately obtain the clock rate. Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/x86/tsc/delay_tsc.c Modified: trunk/src/cpu/x86/tsc/delay_tsc.c ============================================================================== --- trunk/src/cpu/x86/tsc/delay_tsc.c Tue Sep 7 09:43:10 2010 (r5779) +++ trunk/src/cpu/x86/tsc/delay_tsc.c Tue Sep 7 09:53:26 2010 (r5780) @@ -18,8 +18,8 @@ * device. */ -#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ -#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */ +#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */ static unsigned long long calibrate_tsc(void) {

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[commit] r5779 - in trunk/src: cpu/amd/model_lx mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/digitallogic/msm800sev mainboard/iei/pcisa-lx-800-r10 mainboard/lipper...
by repository service 07 Sep '10

07 Sep '10

Author: oxygene Date: Tue Sep 7 09:43:10 2010 New Revision: 5779 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5779 Log: Set up an arbitrary amount of system memory on Geode LX, so coreboot_ram can be unpacked to 1MB. The value is quickly replaced with the real value later, thus causing no harm. Move RAMBASE to the default of 1MB for the affected boards Signed-off-by: Aurelien Guillaume <aurelien(a)iwi.me> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/msrinit.c trunk/src/mainboard/amd/db800/Kconfig trunk/src/mainboard/amd/norwich/Kconfig trunk/src/mainboard/artecgroup/dbe61/Kconfig trunk/src/mainboard/digitallogic/msm800sev/Kconfig trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig trunk/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/src/mainboard/pcengines/alix1c/Kconfig trunk/src/mainboard/pcengines/alix2d/Kconfig trunk/src/mainboard/traverse/geos/Kconfig trunk/src/mainboard/winent/pl6064/Kconfig Modified: trunk/src/cpu/amd/model_lx/msrinit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/msrinit.c Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/cpu/amd/model_lx/msrinit.c Tue Sep 7 09:43:10 2010 (r5779) @@ -39,6 +39,19 @@ {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF + + /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory. + * It doesn't really matter in fact how much, however, because the only usage + * of this extended memory will be to host the coreboot_ram stage at RAMBASE, + * currently 1Mb. + * These registers will be set to their correct value by the Northbridge init code. + * + * WARNING: if coreboot_ram could not be loaded, these registers are probably + * incorrectly set here. You may comment the following two lines and set RAMBASE + * to 0x4000 to revert to the previous behavior for LX-boards. + */ + {MSR_GLIU0_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 + {MSR_GLIU1_SYSMEM, {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000 }; static void msr_init(void) Modified: trunk/src/mainboard/amd/db800/Kconfig ============================================================================== --- trunk/src/mainboard/amd/db800/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/amd/db800/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -25,8 +25,4 @@ int default 4 -config RAMBASE - hex - default 0x4000 - endif # BOARD_AMD_DB800 Modified: trunk/src/mainboard/amd/norwich/Kconfig ============================================================================== --- trunk/src/mainboard/amd/norwich/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/amd/norwich/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -24,8 +24,4 @@ int default 6 -config RAMBASE - hex - default 0x4000 - endif # BOARD_AMD_NORWICH Modified: trunk/src/mainboard/artecgroup/dbe61/Kconfig ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/artecgroup/dbe61/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -24,8 +24,4 @@ int default 3 -#config RAMBASE -# hex -# default 0x4000 - endif # BOARD_ARTECGROUP_DBE61 Modified: trunk/src/mainboard/digitallogic/msm800sev/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/digitallogic/msm800sev/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -25,8 +25,4 @@ int default 9 -config RAMBASE - hex - default 0x4000 - endif # BOARD_DIGITALLOGIC_MSM800SEV Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -24,8 +24,4 @@ int default 9 -config RAMBASE - hex - default 0x4000 - endif # BOARD_IEI_PCISA_LX_800_R10 Modified: trunk/src/mainboard/lippert/roadrunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/lippert/roadrunner-lx/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -27,10 +27,6 @@ int default 7 -config RAMBASE - hex - default 0x4000 - config ONBOARD_UARTS_RS485 bool "Switch on-board serial ports to RS485" default n Modified: trunk/src/mainboard/lippert/spacerunner-lx/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/lippert/spacerunner-lx/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -28,10 +28,6 @@ int default 7 -config RAMBASE - hex - default 0x4000 - config ONBOARD_UARTS_RS485 bool "Switch on-board serial ports to RS485" default n Modified: trunk/src/mainboard/pcengines/alix1c/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/pcengines/alix1c/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -25,8 +25,4 @@ int default 5 -config RAMBASE - hex - default 0x4000 - endif # BOARD_PCENGINES_ALIX1C Modified: trunk/src/mainboard/pcengines/alix2d/Kconfig ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/pcengines/alix2d/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -24,8 +24,4 @@ int default 7 -config RAMBASE - hex - default 0x4000 - endif # BOARD_PCENGINES_ALIX2D Modified: trunk/src/mainboard/traverse/geos/Kconfig ============================================================================== --- trunk/src/mainboard/traverse/geos/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/traverse/geos/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -24,8 +24,4 @@ int default 6 -config RAMBASE - hex - default 0x4000 - endif # BOARD_TRAVERSE_GEOS Modified: trunk/src/mainboard/winent/pl6064/Kconfig ============================================================================== --- trunk/src/mainboard/winent/pl6064/Kconfig Mon Sep 6 22:20:47 2010 (r5778) +++ trunk/src/mainboard/winent/pl6064/Kconfig Tue Sep 7 09:43:10 2010 (r5779) @@ -25,8 +25,4 @@ int default 7 -config RAMBASE - hex - default 0x4000 - endif # BOARD_WINENT_PL6064

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Re: [coreboot] [PATCH] Geode LX and Alix.2 support enhancements
by Jens Rottmann 07 Sep '10

07 Sep '10

Hi, rev 5777 + geode-lx-rambase-at-1m.diff compiles & boots fine for LiPPERT RoadRunner-LX and SpaceRunner-LX. For geode-lx-rambase-at-1m.diff: Tested-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Cheers, Jens

2 1

[PATCH 0/4] Misc speed improvements
by Kevin O'Connor 06 Sep '10

06 Sep '10

These patches reduce the boot time for me on my epia-cn. (From payload launch in 2.273s down to 0.610s.) Where possible, I tried to make the changes apply to other boards. However, I have not tested any other boards. Kevin O'Connor (4): Make initializing PS2 keyboard optional. Enable TSC calibration with timer2 by default. Reduce TSC calibrations from 20ms to 2ms. Don't preload the rom code during the VIA CAR setup. src/Kconfig | 14 ++++++++++++++ src/cpu/via/car/cache_as_ram.inc | 2 ++ src/cpu/x86/Kconfig | 2 +- src/cpu/x86/tsc/delay_tsc.c | 4 ++-- src/pc80/keyboard.c | 2 ++ 5 files changed, 21 insertions(+), 3 deletions(-) -- 1.7.2.2

1 4

Re: [coreboot] [PATCH] Enable qemu memory range 0xc0000-0xfffff automatically.
by Myles Watson 06 Sep '10

06 Sep '10

On Mon, Sep 6, 2010 at 8:37 AM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > Instead of requiring users to modify qemu to allow writes to > 0xc0000-0xfffff, have coreboot qemu support enable the memory range at > startup. > > Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> Should we add a northbridge? It seems too bad to put northbridge code in the mainboard. I like the idea though. Acked-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles > src/mainboard/emulation/qemu-x86/mainboard.c | 41 +++++++++++++++++++++----- > 1 files changed, 33 insertions(+), 8 deletions(-) > > diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c > index 7ab02d9..55fc5c3 100644 > --- a/src/mainboard/emulation/qemu-x86/mainboard.c > +++ b/src/mainboard/emulation/qemu-x86/mainboard.c > @@ -10,15 +10,15 @@ > /* not sure how these are routed in qemu */ > static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; > > -static void qemu_init(device_t dev) > +static void qemu_nb_init(device_t dev) > { > - /* The VGA OPROM already lives at 0xc0000, > - * force coreboot to use it. > - */ > - dev->on_mainboard = 1; > - > - /* Now do the usual initialization */ > - pci_dev_init(dev); > + // Map memory at 0xc0000 - 0xfffff > + int i; > + uint8_t v = pci_read_config8(dev, 0x59); > + v |= 0x30; > + pci_write_config8(dev, 0x59, v); > + for (i=0; i<6; i++) > + pci_write_config8(dev, 0x5a + i, 0x33); > > /* This sneaked in here, because Qemu does not > * emulate a SuperIO chip > @@ -32,6 +32,31 @@ static void qemu_init(device_t dev) > pci_assign_irqs(0, 3, enetIrqs); > } > > +static struct device_operations nb_operations = { > + .read_resources = pci_dev_read_resources, > + .set_resources = pci_dev_set_resources, > + .enable_resources = pci_dev_enable_resources, > + .init = qemu_nb_init, > + .ops_pci = 0, > +}; > + > +static const struct pci_driver nb_driver __pci_driver = { > + .ops = &nb_operations, > + .vendor = 0x8086, > + .device = 0x1237, > +}; > + > +static void qemu_init(device_t dev) > +{ > + /* The VGA OPROM already lives at 0xc0000, > + * force coreboot to use it. > + */ > + dev->on_mainboard = 1; > + > + /* Now do the usual initialization */ > + pci_dev_init(dev); > +} > + > static struct device_operations vga_operations = { > .read_resources = pci_dev_read_resources, > .set_resources = pci_dev_set_resources, > -- > 1.7.2.2 > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot September 2010