coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

Re: [coreboot] Gigabyte GA-6BXE: Missing ACPI support!
by anders＠jenbo.dk 10 Sep '10

10 Sep '10

Hi I did the port to support this board, but I have no experience with ACPI and.still need to port it to CAR first. I was also hoping to at some point fix the ps2 mouse and parallel port although they are low on my priority list. Sadly I'm totally striped of time du to my new job and working on Ubuntu. If some one could help guide me on the way to car and where to start with implementing ACPI it would be much appreciated. - Anders ----- Reply message ----- Fra: "Cristóvão Gomes Ferreira" <crisoagf(a)gmail.com> Dato: fre., sep. 10, 2010 13:30 Emne: [coreboot] Gigabyte GA-6BXE: Missing ACPI support! Til: <coreboot(a)coreboot.org> Hi all! This is my first message to the coreboot mailing list, so I'd like to thank the developers for the excellent job you've done. I'm writing because, although coreboot does work on my board (a Gigabyte GA-6BXE), ACPI doesn't work, and I'd like to help, not being a programmer. What information can I send that can help you?

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coreboot/flashrom flyers (PDF) needed for FrOSCamp
by Carl-Daniel Hailfinger 10 Sep '10

10 Sep '10

Hi, coreboot and flashrom got a nice booth at the FrOSCamp expo at ETH Zurich (Switzerland) Sept. 17-18 2010. It is sort of a Swiss FOSDEM, and FUDCon EMEA will be in the same place so there will be lots of interesting people to meet. http://wiki.froscamp.org/Welcome Not only do we have a nice and spacious booth, I even got two slots to talk about coreboot and flashrom on Saturday. If you have any coreboot/flashrom related flyers/posters in PDF/PS/... format, please send them to me ASAP so I can make sure they can be printed in time. Peter, I think you once created awesome flyers for coreboot. I'd love to reprint them and distribute them amongst FrOSCamp visitors. I would also appreciate PDFs of coreboot related talks. I do have my own slides for a coreboot introduction, but it's always a good idea to cross-check them against other presentations to make sure I don't forget anything. Regards, Carl-Daniel

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Gigabyte GA-6BXE: Missing ACPI support!
by Cristóvão Gomes Ferreira 10 Sep '10

10 Sep '10

Hi all! This is my first message to the coreboot mailing list, so I'd like to thank the developers for the excellent job you've done. I'm writing because, although coreboot does work on my board (a Gigabyte GA-6BXE), ACPI doesn't work, and I'd like to help, not being a programmer. What information can I send that can help you?

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openbiosprog-spi - Open Hardware / Free Software USB-based SPI chip programmer
by Uwe Hermann 10 Sep '10

10 Sep '10

Hi, just a quick announcement I totally forgot to send out to the probably most relevant places (coreboot + flashrom) about a little hardware project I have finished a while ago: openbiosprog-spi. It's a USB-based SPI chip flasher hardware based on the FTDI FT2232H chip, all the gory details (including lots of photos) are at: http://randomprojects.org/wiki/Openbiosprog-spi http://hermann-uwe.de/blog/openbiosprog-spi-a-diy-open-hardware-and-free-so… The device is already supported by flashrom out of the box. It has a small DIP-8 socket to allow flashing DIP-8 SPI chips from newer mainboards externally (if they're in a socket). As an alternative you can also solder an 8-pin pin-header instead of the socket in order to connect to a soldered SO-8 chip on a mainboard directly using some wires. The hardware schematics and layouts were done using the open-source Kicad suite and they're CC-BY-SA 3.0 licensed. All hardware files are available from here: git clone git://gitorious.org/openbiosprog/openbiosprog-spi.git Flashrom usage of the device looks like this: flashrom -p ft2232_spi:type=2232H,port=A -w foo.bin Have fun, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r5799 - trunk/src/cpu/x86/tsc
by repository service 09 Sep '10

09 Sep '10

Author: oxygene Date: Fri Sep 10 00:12:40 2010 New Revision: 5799 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5799 Log: Adapt comment, too. (trivial) Noticed-by: Uwe Hermann Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/x86/tsc/delay_tsc.c Modified: trunk/src/cpu/x86/tsc/delay_tsc.c ============================================================================== --- trunk/src/cpu/x86/tsc/delay_tsc.c Thu Sep 9 22:37:00 2010 (r5798) +++ trunk/src/cpu/x86/tsc/delay_tsc.c Fri Sep 10 00:12:40 2010 (r5799) @@ -138,7 +138,7 @@ } -#endif /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2*/ +#endif /* CONFIG_TSC_CALIBRATE_WITH_IO */ void init_timer(void) {

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[PATCH] filo: trivial compilation fix and a remark about USB support
by Aurélien 09 Sep '10

09 Sep '10

Hi, Below is a trivial patch for filo. filo does not compile with the grub interface right out of the SVN: coreboot/payloads/filo/build/main/grub/completions.o: In function `print_completions': completions.c:(.text+0x2f2): undefined reference to `IS_PC_SLICE_TYPE_BSD' This patch defines this macro to 0 (false), like what is done in fs/filesys.h, which fixes the problem. However, this may not be the right way to fix it. Please do check before applying. --- I also have a remark about USB support in filo: The default configuration for filo enables support for USB, although the default configuration for libpayload does not. There's no harm done, since you have to configure both, but it appears more logical to have USB disabled in both config. Anyways, that's not really a problem :) --- Signed-off-by: Aurelien Guillaume <aurelien(a)iwi.me> Index: main/grub/completions.c =================================================================== --- main/grub/completions.c (revision 138) +++ main/grub/completions.c (working copy) @@ -23,6 +23,7 @@ #include <config.h> #include <grub/shared.h> #define current_slice 0 +#define IS_PC_SLICE_TYPE_BSD(type) 0 static int do_completion; static int unique; -- Aurélien Guillaume

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[PATCH] timeout during PS/2 keyboard init
by Scott Duplichan 09 Sep '10

09 Sep '10

Thanks Marc. This patch avoids a timeout during PS/2 keyboard initialization. It can reduce KBC init time by up to 400 ms on real hardware, and by a minute or so on AMD simnow. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/pc80/keyboard.c =================================================================== --- src/pc80/keyboard.c (revision 5788) +++ src/pc80/keyboard.c (working copy) @@ -242,7 +242,7 @@ outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) return; outb(0x61, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ - if (kbc_output_buffer_full()) { + if (kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during final keyboard enable\n"); return; }

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[commit] r5798 - trunk/src/pc80
by repository service 09 Sep '10

09 Sep '10

Author: mjones Date: Thu Sep 9 22:37:00 2010 New Revision: 5798 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5798 Log: This patch avoids a timeout during PS/2 keyboard initialization. It can reduce KBC init time by up to 400 ms on real hardware, and by a minute or so on AMD simnow. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/pc80/keyboard.c Modified: trunk/src/pc80/keyboard.c ============================================================================== --- trunk/src/pc80/keyboard.c Thu Sep 9 18:00:20 2010 (r5797) +++ trunk/src/pc80/keyboard.c Thu Sep 9 22:37:00 2010 (r5798) @@ -244,7 +244,7 @@ outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) return; outb(0x61, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ - if (kbc_output_buffer_full()) { + if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during final keyboard enable\n"); return; }

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[commit] r5797 - trunk/src/devices/oprom/yabel
by repository service 09 Sep '10

09 Sep '10

Author: myles Date: Thu Sep 9 18:00:20 2010 New Revision: 5797 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5797 Log: Make huge macros inline functions for readability. Remove warnings. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/devices/oprom/yabel/mem.c trunk/src/devices/oprom/yabel/vbe.c Modified: trunk/src/devices/oprom/yabel/mem.c ============================================================================== --- trunk/src/devices/oprom/yabel/mem.c Thu Sep 9 16:54:07 2010 (r5796) +++ trunk/src/devices/oprom/yabel/mem.c Thu Sep 9 18:00:20 2010 (r5797) @@ -19,149 +19,177 @@ #include "mem.h" #include "compat/time.h" +#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) + // define a check for access to certain (virtual) memory regions (interrupt handlers, BIOS Data Area, ...) #if CONFIG_X86EMU_DEBUG static u8 in_check = 0; // to avoid recursion... -u16 ebda_segment; -u32 ebda_size; -//TODO: these macros have grown so large, that they should be changed to an inline function, -//just for the sake of readability... +static inline void DEBUG_CHECK_VMEM_READ(u32 _addr, u32 _rval) +{ + u16 ebda_segment; + u32 ebda_size; + if (!((debug_flags & DEBUG_CHECK_VMEM_ACCESS) && (in_check == 0))) + return; + in_check = 1; + /* determine ebda_segment and size + * since we are using my_rdx calls, make sure, this is after setting in_check! */ + /* offset 03 in BDA is EBDA segment */ + ebda_segment = my_rdw(0x40e); + /* first value in ebda is size in KB */ + ebda_size = my_rdb(ebda_segment << 4) * 1024; + /* check Interrupt Vector Access (0000:0000h - 0000:0400h) */ + if (_addr < 0x400) { + DEBUG_PRINTF_CS_IP("%s: read from Interrupt Vector %x --> %x\n", + __func__, _addr / 4, _rval); + } + /* access to BIOS Data Area (0000:0400h - 0000:0500h)*/ + else if ((_addr >= 0x400) && (_addr < 0x500)) { + DEBUG_PRINTF_CS_IP("%s: read from BIOS Data Area: addr: %x --> %x\n", + __func__, _addr, _rval); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* access to first 64k of memory... */ + else if (_addr < 0x10000) { + DEBUG_PRINTF_CS_IP("%s: read from segment 0000h: addr: %x --> %x\n", + __func__, _addr, _rval); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* read from PMM_CONV_SEGMENT */ + else if ((_addr <= ((PMM_CONV_SEGMENT << 4) | 0xffff)) && (_addr >= (PMM_CONV_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: read from PMM Segment %04xh: addr: %x --> %x\n", + __func__, PMM_CONV_SEGMENT, _addr, _rval); + /* HALT_SYS(); */ + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* read from PNP_DATA_SEGMENT */ + else if ((_addr <= ((PNP_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (PNP_DATA_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: read from PnP Data Segment %04xh: addr: %x --> %x\n", + __func__, PNP_DATA_SEGMENT, _addr, _rval); + /* HALT_SYS(); */ + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* read from EBDA Segment */ + else if ((_addr <= ((ebda_segment << 4) | (ebda_size - 1))) && (_addr >= (ebda_segment << 4))) { + DEBUG_PRINTF_CS_IP("%s: read from Extended BIOS Data Area %04xh, size: %04x: addr: %x --> %x\n", + __func__, ebda_segment, ebda_size, _addr, _rval); + } + /* read from BIOS_DATA_SEGMENT */ + else if ((_addr <= ((BIOS_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (BIOS_DATA_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: read from BIOS Data Segment %04xh: addr: %x --> %x\n", + __func__, BIOS_DATA_SEGMENT, _addr, _rval); + /* for PMM debugging */ + /*if (_addr == BIOS_DATA_SEGMENT << 4) { + X86EMU_trace_on(); + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + }*/ + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + in_check = 0; +} -#define DEBUG_CHECK_VMEM_READ(_addr, _rval) \ - if ((debug_flags & DEBUG_CHECK_VMEM_ACCESS) && (in_check == 0)) { \ - in_check = 1; \ - /* determine ebda_segment and size \ - * since we are using my_rdx calls, make sure, this is after setting in_check! */ \ - /* offset 03 in BDA is EBDA segment */ \ - ebda_segment = my_rdw(0x40e); \ - /* first value in ebda is size in KB */ \ - ebda_size = my_rdb(ebda_segment << 4) * 1024; \ - /* check Interrupt Vector Access (0000:0000h - 0000:0400h) */ \ - if (_addr < 0x400) { \ - DEBUG_PRINTF_CS_IP("%s: read from Interrupt Vector %x --> %x\n", \ - __func__, _addr / 4, _rval); \ - } \ - /* access to BIOS Data Area (0000:0400h - 0000:0500h)*/ \ - else if ((_addr >= 0x400) && (addr < 0x500)) { \ - DEBUG_PRINTF_CS_IP("%s: read from BIOS Data Area: addr: %x --> %x\n", \ - __func__, _addr, _rval); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* access to first 64k of memory... */ \ - else if (_addr < 0x10000) { \ - DEBUG_PRINTF_CS_IP("%s: read from segment 0000h: addr: %x --> %x\n", \ - __func__, _addr, _rval); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* read from PMM_CONV_SEGMENT */ \ - else if ((_addr <= ((PMM_CONV_SEGMENT << 4) | 0xffff)) && (_addr >= (PMM_CONV_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: read from PMM Segment %04xh: addr: %x --> %x\n", \ - __func__, PMM_CONV_SEGMENT, _addr, _rval); \ - /* HALT_SYS(); */ \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* read from PNP_DATA_SEGMENT */ \ - else if ((_addr <= ((PNP_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (PNP_DATA_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: read from PnP Data Segment %04xh: addr: %x --> %x\n", \ - __func__, PNP_DATA_SEGMENT, _addr, _rval); \ - /* HALT_SYS(); */ \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* read from EBDA Segment */ \ - else if ((_addr <= ((ebda_segment << 4) | (ebda_size - 1))) && (_addr >= (ebda_segment << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: read from Extended BIOS Data Area %04xh, size: %04x: addr: %x --> %x\n", \ - __func__, ebda_segment, ebda_size, _addr, _rval); \ - } \ - /* read from BIOS_DATA_SEGMENT */ \ - else if ((_addr <= ((BIOS_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (BIOS_DATA_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: read from BIOS Data Segment %04xh: addr: %x --> %x\n", \ - __func__, BIOS_DATA_SEGMENT, _addr, _rval); \ - /* for PMM debugging */ \ - /*if (_addr == BIOS_DATA_SEGMENT << 4) { \ - X86EMU_trace_on(); \ - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; \ - }*/ \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - in_check = 0; \ - } -#define DEBUG_CHECK_VMEM_WRITE(_addr, _val) \ - if ((debug_flags & DEBUG_CHECK_VMEM_ACCESS) && (in_check == 0)) { \ - in_check = 1; \ - /* determine ebda_segment and size \ - * since we are using my_rdx calls, make sure, this is after setting in_check! */ \ - /* offset 03 in BDA is EBDA segment */ \ - ebda_segment = my_rdw(0x40e); \ - /* first value in ebda is size in KB */ \ - ebda_size = my_rdb(ebda_segment << 4) * 1024; \ - /* check Interrupt Vector Access (0000:0000h - 0000:0400h) */ \ - if (_addr < 0x400) { \ - DEBUG_PRINTF_CS_IP("%s: write to Interrupt Vector %x <-- %x\n", \ - __func__, _addr / 4, _val); \ - } \ - /* access to BIOS Data Area (0000:0400h - 0000:0500h)*/ \ - else if ((_addr >= 0x400) && (addr < 0x500)) { \ - DEBUG_PRINTF_CS_IP("%s: write to BIOS Data Area: addr: %x <-- %x\n", \ - __func__, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* access to first 64k of memory...*/ \ - else if (_addr < 0x10000) { \ - DEBUG_PRINTF_CS_IP("%s: write to segment 0000h: addr: %x <-- %x\n", \ - __func__, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* write to PMM_CONV_SEGMENT... */ \ - else if ((_addr <= ((PMM_CONV_SEGMENT << 4) | 0xffff)) && (_addr >= (PMM_CONV_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: write to PMM Segment %04xh: addr: %x <-- %x\n", \ - __func__, PMM_CONV_SEGMENT, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* write to PNP_DATA_SEGMENT... */ \ - else if ((_addr <= ((PNP_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (PNP_DATA_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: write to PnP Data Segment %04xh: addr: %x <-- %x\n", \ - __func__, PNP_DATA_SEGMENT, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* write to EBDA Segment... */ \ - else if ((_addr <= ((ebda_segment << 4) | (ebda_size - 1))) && (_addr >= (ebda_segment << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: write to Extended BIOS Data Area %04xh, size: %04x: addr: %x <-- %x\n", \ - __func__, ebda_segment, ebda_size, _addr, _val); \ - } \ - /* write to BIOS_DATA_SEGMENT... */ \ - else if ((_addr <= ((BIOS_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (BIOS_DATA_SEGMENT << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: write to BIOS Data Segment %04xh: addr: %x <-- %x\n", \ - __func__, BIOS_DATA_SEGMENT, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - /* write to current CS segment... */ \ - else if ((_addr < ((M.x86.R_CS << 4) | 0xffff)) && (_addr > (M.x86.R_CS << 4))) { \ - DEBUG_PRINTF_CS_IP("%s: write to CS segment %04xh: addr: %x <-- %x\n", \ - __func__, M.x86.R_CS, _addr, _val); \ - /* dump registers */ \ - /* x86emu_dump_xregs(); */ \ - } \ - in_check = 0; \ - } +static inline void DEBUG_CHECK_VMEM_WRITE(u32 _addr, u32 _val) +{ + u16 ebda_segment; + u32 ebda_size; + if (!((debug_flags & DEBUG_CHECK_VMEM_ACCESS) && (in_check == 0))) + return; + in_check = 1; + /* determine ebda_segment and size + * since we are using my_rdx calls, make sure that this is after + * setting in_check! */ + /* offset 03 in BDA is EBDA segment */ + ebda_segment = my_rdw(0x40e); + /* first value in ebda is size in KB */ + ebda_size = my_rdb(ebda_segment << 4) * 1024; + /* check Interrupt Vector Access (0000:0000h - 0000:0400h) */ + if (_addr < 0x400) { + DEBUG_PRINTF_CS_IP("%s: write to Interrupt Vector %x <-- %x\n", + __func__, _addr / 4, _val); + } + /* access to BIOS Data Area (0000:0400h - 0000:0500h)*/ + else if ((_addr >= 0x400) && (_addr < 0x500)) { + DEBUG_PRINTF_CS_IP("%s: write to BIOS Data Area: addr: %x <-- %x\n", + __func__, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* access to first 64k of memory...*/ + else if (_addr < 0x10000) { + DEBUG_PRINTF_CS_IP("%s: write to segment 0000h: addr: %x <-- %x\n", + __func__, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* write to PMM_CONV_SEGMENT... */ + else if ((_addr <= ((PMM_CONV_SEGMENT << 4) | 0xffff)) && (_addr >= (PMM_CONV_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: write to PMM Segment %04xh: addr: %x <-- %x\n", + __func__, PMM_CONV_SEGMENT, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* write to PNP_DATA_SEGMENT... */ + else if ((_addr <= ((PNP_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (PNP_DATA_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: write to PnP Data Segment %04xh: addr: %x <-- %x\n", + __func__, PNP_DATA_SEGMENT, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* write to EBDA Segment... */ + else if ((_addr <= ((ebda_segment << 4) | (ebda_size - 1))) && (_addr >= (ebda_segment << 4))) { + DEBUG_PRINTF_CS_IP("%s: write to Extended BIOS Data Area %04xh, size: %04x: addr: %x <-- %x\n", + __func__, ebda_segment, ebda_size, _addr, _val); + } + /* write to BIOS_DATA_SEGMENT... */ + else if ((_addr <= ((BIOS_DATA_SEGMENT << 4) | 0xffff)) && (_addr >= (BIOS_DATA_SEGMENT << 4))) { + DEBUG_PRINTF_CS_IP("%s: write to BIOS Data Segment %04xh: addr: %x <-- %x\n", + __func__, BIOS_DATA_SEGMENT, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + /* write to current CS segment... */ + else if ((_addr < ((M.x86.R_CS << 4) | 0xffff)) && (_addr > (M.x86.R_CS << 4))) { + DEBUG_PRINTF_CS_IP("%s: write to CS segment %04xh: addr: %x <-- %x\n", + __func__, M.x86.R_CS, _addr, _val); + /* dump registers */ + /* x86emu_dump_xregs(); */ + } + in_check = 0; +} #else -#define DEBUG_CHECK_VMEM_READ(_addr, _rval) -#define DEBUG_CHECK_VMEM_WRITE(_addr, _val) +static inline void DEBUG_CHECK_VMEM_READ(u32 _addr, u32 _rval) {}; +static inline void DEBUG_CHECK_VMEM_WRITE(u32 _addr, u32 _val) {}; #endif -void update_time(u32); +//update time in BIOS Data Area +//DWord at offset 0x6c is the timer ticks since midnight, timer is running at 18Hz +//byte at 0x70 is timer overflow (set if midnight passed since last call to interrupt 1a function 00 +//cur_val is the current value, of offset 6c... +static void +update_time(u32 cur_val) +{ + //for convenience, we let the start of timebase be at midnight, we currently dont support + //real daytime anyway... + u64 ticks_per_day = tb_freq * 60 * 24; + // at 18Hz a period is ~55ms, converted to ticks (tb_freq is ticks/second) + u32 period_ticks = (55 * tb_freq) / 1000; + u64 curr_time = get_time(); + u64 ticks_since_midnight = curr_time % ticks_per_day; + u32 periods_since_midnight = ticks_since_midnight / period_ticks; + // if periods since midnight is smaller than last value, set overflow + // at BDA Offset 0x70 + if (periods_since_midnight < cur_val) { + my_wrb(0x470, 1); + } + // store periods since midnight at BDA offset 0x6c + my_wrl(0x46c, periods_since_midnight); +} -#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) // read byte from memory u8 my_rdb(u32 addr) @@ -467,27 +495,3 @@ wrl(addr, val); } #endif - -//update time in BIOS Data Area -//DWord at offset 0x6c is the timer ticks since midnight, timer is running at 18Hz -//byte at 0x70 is timer overflow (set if midnight passed since last call to interrupt 1a function 00 -//cur_val is the current value, of offset 6c... -void -update_time(u32 cur_val) -{ - //for convenience, we let the start of timebase be at midnight, we currently dont support - //real daytime anyway... - u64 ticks_per_day = tb_freq * 60 * 24; - // at 18Hz a period is ~55ms, converted to ticks (tb_freq is ticks/second) - u32 period_ticks = (55 * tb_freq) / 1000; - u64 curr_time = get_time(); - u64 ticks_since_midnight = curr_time % ticks_per_day; - u32 periods_since_midnight = ticks_since_midnight / period_ticks; - // if periods since midnight is smaller than last value, set overflow - // at BDA Offset 0x70 - if (periods_since_midnight < cur_val) { - my_wrb(0x470, 1); - } - // store periods since midnight at BDA offset 0x6c - my_wrl(0x46c, periods_since_midnight); -} Modified: trunk/src/devices/oprom/yabel/vbe.c ============================================================================== --- trunk/src/devices/oprom/yabel/vbe.c Thu Sep 9 16:54:07 2010 (r5796) +++ trunk/src/devices/oprom/yabel/vbe.c Thu Sep 9 18:00:20 2010 (r5797) @@ -154,7 +154,7 @@ return 0; // successfull init } -#if CONFIG_BOOTSPLASH || CONFIG_EXPERT +#if CONFIG_BOOTSPLASH // VBE Function 00h static u8 vbe_info(vbe_info_t * info) @@ -301,9 +301,7 @@ } return 0; } -#endif -#if CONFIG_EXPERT //VBE Function 08h static u8 vbe_set_palette_format(u8 format) @@ -766,9 +764,7 @@ } return 0; } -#endif -#if CONFIG_BOOTSPLASH vbe_mode_info_t mode_info; void vbe_set_graphics(void) @@ -798,7 +794,7 @@ vbe_get_mode_info(&mode_info); unsigned char *framebuffer = (unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr); - DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%08x\n", framebuffer); + DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer); vbe_set_mode(&mode_info); struct jpeg_decdata *decdata; @@ -813,7 +809,7 @@ DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; } - DEBUG_PRINTF_VBE("Splash at %08x ...\n", jpeg); + DEBUG_PRINTF_VBE("Splash at %p ...\n", jpeg); dump(jpeg, 64); int ret = 0;

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[commit] r5796 - in trunk/src: arch/i386/include/arch arch/i386/lib cpu/amd/model_10xxx mainboard/tyan/s2912_fam10 northbridge/amd/amdfam10 northbridge/amd/amdmct/mct southbridge/nvidia/mcp55
by repository service 09 Sep '10

09 Sep '10

Author: myles Date: Thu Sep 9 16:54:07 2010 New Revision: 5796 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5796 Log: Please find appended. This patch gets rid of the %gs magic altogether, fixes a few alignment wrinkles and sets up and registers the MMCONF area for AMD Fam10h CPUs (where selected by mainboard configuration). It removes a bit of code that proved troublesome in MMCONF setups from mcp55_early_setup_car.c, as per earlier discussion. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/arch/i386/include/arch/mmio_conf.h trunk/src/arch/i386/include/arch/romcc_io.h trunk/src/arch/i386/lib/pci_ops_mmconf.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdfam10/early_ht.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/arch/i386/include/arch/mmio_conf.h ============================================================================== --- trunk/src/arch/i386/include/arch/mmio_conf.h Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/arch/i386/include/arch/mmio_conf.h Thu Sep 9 16:54:07 2010 (r5796) @@ -2,13 +2,13 @@ #define ARCH_MMIO_H 1 -//extended read, GS is already set +// Extended read, constrain to use registers as mandated by AMD MMCONFIG mechanism. static inline __attribute__((always_inline)) uint8_t read8x(uint32_t addr) { uint8_t value; __asm__ volatile ( - "movb %%gs:(%1), %0\n\t" + "movb (%1), %%al\n\t" :"=a"(value): "b" (addr) ); return value; @@ -18,7 +18,7 @@ { uint16_t value; __asm__ volatile ( - "movw %%gs:(%1), %0\n\t" + "movw (%1), %%ax\n\t" :"=a"(value): "b" (addr) ); @@ -30,7 +30,7 @@ { uint32_t value; __asm__ volatile ( - "movl %%gs:(%1), %0\n\t" + "movl (%1), %%eax\n\t" :"=a"(value): "b" (addr) ); @@ -41,7 +41,7 @@ static inline __attribute__((always_inline)) void write8x(uint32_t addr, uint8_t value) { __asm__ volatile ( - "movb %1, %%gs:(%0)\n\t" + "movb %%al, (%0)\n\t" :: "b" (addr), "a" (value) ); @@ -50,7 +50,7 @@ static inline __attribute__((always_inline)) void write16x(uint32_t addr, uint16_t value) { __asm__ volatile ( - "movw %1, %%gs:(%0)\n\t" + "movw %%ax, (%0)\n\t" :: "b" (addr), "a" (value) ); @@ -59,7 +59,7 @@ static inline __attribute__((always_inline)) void write32x(uint32_t addr, uint32_t value) { __asm__ volatile ( - "movl %1, %%gs:(%0)\n\t" + "movl %%eax, (%0)\n\t" :: "b" (addr), "a" (value) ); } Modified: trunk/src/arch/i386/include/arch/romcc_io.h ============================================================================== --- trunk/src/arch/i386/include/arch/romcc_io.h Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/arch/i386/include/arch/romcc_io.h Thu Sep 9 16:54:07 2010 (r5796) @@ -107,7 +107,7 @@ static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) { unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); return read16x(addr); } #endif @@ -138,7 +138,7 @@ static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); return read32x(addr); } #endif @@ -199,7 +199,7 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) { unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); write16x(addr, value); } #endif @@ -230,7 +230,7 @@ static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) { unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; + addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); write32x(addr, value); } #endif Modified: trunk/src/arch/i386/lib/pci_ops_mmconf.c ============================================================================== --- trunk/src/arch/i386/lib/pci_ops_mmconf.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/arch/i386/lib/pci_ops_mmconf.c Thu Sep 9 16:54:07 2010 (r5796) @@ -27,12 +27,12 @@ static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) { - return (read16x(PCI_MMIO_ADDR(bus, devfn, where))); + return (read16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1)); } static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) { - return (read32x(PCI_MMIO_ADDR(bus, devfn, where))); + return (read32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3)); } static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) @@ -42,12 +42,12 @@ static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) { - write8x(PCI_MMIO_ADDR(bus, devfn, where), value); + write16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); } static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) { - write8x(PCI_MMIO_ADDR(bus, devfn, where), value); + write32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Sep 9 16:54:07 2010 (r5796) @@ -57,32 +57,28 @@ static void set_EnableCf8ExtCfg(void) { } #endif -/*[39:8] */ -#define PCI_MMIO_BASE 0xfe000000 -/* because we will use gs to store hi, so need to make sure lo can start - from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/ + +#define _ULLx(x) x ## ULL +#define _ULL(x) _ULLx(x) + +/*[63:0] */ +#define PCI_MMIO_BASE _ULL(CONFIG_MMCONF_BASE_ADDRESS) static void set_pci_mmio_conf_reg(void) { #if CONFIG_MMCONF_SUPPORT +# if PCI_MMIO_BASE > 0xffffffff +# error CONFIG_MMCONF_BASE_ADDRESS must currently fit in 32 bits! +# endif msr_t msr; msr = rdmsr(0xc0010058); msr.lo &= ~(0xfff00000 | (0xf << 2)); - // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space - msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0); + // 256 buses, one segment. Total 256M address space. + msr.lo |= (PCI_MMIO_BASE & 0xfff00000) | (8 << 2) | (1 << 0); msr.hi &= ~(0x0000ffff); - msr.hi |= (PCI_MMIO_BASE >> (32 - 8)); - wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg - - //mtrr for that range? - // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); - - set_wrap32dis(); - - msr.hi = (PCI_MMIO_BASE >> (32 - 8)); - msr.lo = 0; - wrmsr(0xc0000101, msr); //GS_Base Reg + msr.hi |= (PCI_MMIO_BASE >> (32)); + wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg #endif } Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Sep 9 16:54:07 2010 (r5796) @@ -18,6 +18,7 @@ select ENABLE_APIC_EXT_ID select AMDMCT select TINY_BOOTBLOCK + select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR string Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Thu Sep 9 16:54:07 2010 (r5796) @@ -23,6 +23,7 @@ select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select MMCONF_SUPPORT config AGP_APERTURE_SIZE hex @@ -54,6 +55,16 @@ default n depends on NORTHBRIDGE_AMD_AMDFAM10 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config MMCONF_BUS_NUMBER + int + default 256 + depends on NORTHBRIDGE_AMD_AMDFAM10 + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdfam10/bootblock.c" Modified: trunk/src/northbridge/amd/amdfam10/early_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/early_ht.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/northbridge/amd/amdfam10/early_ht.c Thu Sep 9 16:54:07 2010 (r5796) @@ -129,7 +129,7 @@ PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; do { - ctrl = pci_read_config16(devx, pos + ctrl_off); + ctrl = pci_io_read_config16(devx, pos + ctrl_off); /* Is this the end of the hypertransport chain? */ if (ctrl & (1 << 6)) { goto out; @@ -144,8 +144,8 @@ * if its transient */ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_write_config16(devx, pos + ctrl_off, ctrl); - ctrl = pci_read_config16(devx, pos + ctrl_off); + pci_io_write_config16(devx, pos + ctrl_off, ctrl); + ctrl = pci_io_read_config16(devx, pos + ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { // can not clear the error break; Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Sep 9 16:54:07 2010 (r5796) @@ -1440,9 +1440,29 @@ { } +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); +} + static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, .enable_resources = cpu_bus_noop, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Thu Sep 9 16:54:07 2010 (r5796) @@ -1970,7 +1970,7 @@ reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/ val = Get_NB32(dev, reg); if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */ - reg = 0x60 + (q << 1) + reg_off; /*Mask[q] reg.*/ + reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/ val = Get_NB32(dev, reg); val >>= 19; val++; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Thu Sep 9 16:51:17 2010 (r5795) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Thu Sep 9 16:54:07 2010 (r5796) @@ -267,8 +267,13 @@ RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, + /* The following operation hangs when performed via MMCFG: + pci_read_config32(romcc): 00010000:0078: 20040000 + setup_resource_map_x_offset: 10000, 78: 20040000 + pci_write_config32(romcc): 00010000:0078: 19040000 + (hang) + Response missing? */ + /* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */ #if MCP55_USE_AZA == 1 RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,

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coreboot September 2010