coreboot September 2010

coreboot@coreboot.org

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324 discussions

[PATCH]Use __DATE__ and __TIME__ instead of date(1)
by Patrick Georgi 25 Sep '10

25 Sep '10

Hi, attached patch uses the __DATE__ and __TIME__ macros instead of date(1) calls. User visible results are: - different date format (no timezone included) - different time stamps in a single build - less calls to tools from make (and it also slightly helps ccache do its magic) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

3 8

[commit] r5841 - trunk/src/arch/i386/init
by repository service 25 Sep '10

25 Sep '10

Author: oxygene Date: Sat Sep 25 16:15:41 2010 New Revision: 5841 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5841 Log: Make globals in romstage break the build, so we don't have to wonder why variables in .data or .bss (both somewhere in ROM space) are wrong. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb ============================================================================== --- trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Sat Sep 25 14:37:33 2010 (r5840) +++ trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Sat Sep 25 16:15:41 2010 (r5841) @@ -49,4 +49,5 @@ *(.comment.*) *(.note.*) } + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); }

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[PATCH]Avoid globals in romstage
by Patrick Georgi 25 Sep '10

25 Sep '10

Hi, attached patch makes globals in romstage a build breaking condition, given that .bss and .data are allocated in ROM areas (ie. non-writable) this is provides some protection against certain coding errors. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[commit] r5840 - in trunk/src/cpu/intel: model_106cx model_6ex model_6fx
by repository service 25 Sep '10

25 Sep '10

Author: uwe Date: Sat Sep 25 14:37:33 2010 New Revision: 5840 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5840 Log: Drop <cpu/amd/mtrr.h> #include from Intel CPUs. Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which is obviously wrong, so drop the #includes. None of their #defines are used in the Intel code. Build-tested with two of the affected boards. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sat Sep 25 12:42:55 2010 (r5839) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sat Sep 25 14:37:33 2010 (r5840) @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sat Sep 25 12:42:55 2010 (r5839) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sat Sep 25 14:37:33 2010 (r5840) @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sat Sep 25 12:42:55 2010 (r5839) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sat Sep 25 14:37:33 2010 (r5840) @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp

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Drop <cpu/amd/mtrr.h> #include from Intel CPUs
by Uwe Hermann 25 Sep '10

25 Sep '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 1

[PATCH] fix option table race (this time for real)
by Stefan Reinauer 25 Sep '10

25 Sep '10

See patch

2 2

[commit] r5839 - in trunk/src: mainboard/dell/s1850 mainboard/intel/jarrell mainboard/supermicro/x6dai_g mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2 mainboard/supermicro/x6dhr_ig mai...
by repository service 25 Sep '10

25 Sep '10

Author: stepan Date: Sat Sep 25 12:42:55 2010 New Revision: 5839 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5839 Log: Keep the mc146818rtc.h include close to the option table include where possible. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7525/raminit.c Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/dell/s1850/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sat Sep 25 12:42:55 2010 (r5839) @@ -5,7 +5,6 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <stdlib.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/northbridge/intel/e7520/raminit.c Sat Sep 25 12:42:55 2010 (r5839) @@ -23,6 +23,7 @@ #include <stdlib.h> #include "raminit.h" #include "e7520.h" +#include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif @@ -626,7 +627,7 @@ if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); - } else + } else #endif { print_debug("ECC on\n"); Modified: trunk/src/northbridge/intel/e7525/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7525/raminit.c Sat Sep 25 12:40:47 2010 (r5838) +++ trunk/src/northbridge/intel/e7525/raminit.c Sat Sep 25 12:42:55 2010 (r5839) @@ -23,6 +23,7 @@ #include <stdlib.h> #include "raminit.h" #include "e7525.h" +#include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif

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[commit] r5838 - in trunk: src/arch/i386 src/cpu/amd/dualcore src/cpu/amd/model_fxx src/cpu/amd/quadcore src/include/pc80 src/mainboard/amd/dbm690t src/mainboard/kontron/986lcd-m src/northbridge/am...
by repository service 25 Sep '10

25 Sep '10

Author: stepan Date: Sat Sep 25 12:40:47 2010 New Revision: 5838 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5838 Log: - Fix race condition in option_table.h generation by moving the include statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/arch/i386/Makefile.inc trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/pc80/mc146818rtc.h trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7525/raminit.c trunk/src/pc80/Makefile.inc trunk/src/pc80/mc146818rtc.c trunk/src/pc80/mc146818rtc_early.c trunk/src/pc80/serial.c trunk/util/options/build_opt_tbl.c Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/arch/i386/Makefile.inc Sat Sep 25 12:40:47 2010 (r5838) @@ -206,11 +206,11 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -I. -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ + $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h @printf " CC romstage.inc\n" - $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -c -S $< -o $@ + $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc @printf " POST romstage.inc\n" Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/cpu/amd/dualcore/dualcore.c Sat Sep 25 12:40:47 2010 (r5838) @@ -7,6 +7,9 @@ #include "cpu/amd/dualcore/dualcore_id.c" #include <pc80/mc146818rtc.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif static inline unsigned get_core_num_in_bsp(unsigned nodeid) { Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Sat Sep 25 12:40:47 2010 (r5838) @@ -1,3 +1,7 @@ +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID #if CONFIG_K8_REV_F_SUPPORT == 0 Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/cpu/amd/quadcore/quadcore.c Sat Sep 25 12:40:47 2010 (r5838) @@ -20,6 +20,9 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> #include <northbridge/amd/amdht/ht_wrapper.c> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #ifndef SET_NB_CFG_54 #define SET_NB_CFG_54 1 Modified: trunk/src/include/pc80/mc146818rtc.h ============================================================================== --- trunk/src/include/pc80/mc146818rtc.h Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/include/pc80/mc146818rtc.h Sat Sep 25 12:40:47 2010 (r5838) @@ -81,14 +81,6 @@ #define PC_CKS_RANGE_END 45 #define PC_CKS_LOC 46 -/* coreboot cmos checksum is usually only built over bytes 49..125 - * LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined - * in option_table.h - */ -#if CONFIG_HAVE_OPTION_TABLE -#include <option_table.h> -#endif - #ifndef UTIL_BUILD_OPTION_TABLE #include <arch/io.h> static inline unsigned char cmos_read(unsigned char addr) Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Sat Sep 25 12:40:47 2010 (r5838) @@ -25,12 +25,6 @@ string default amd/dbm690t -# This is a temporary fix, and should be removed when the race condition for -# building option_table.h is fixed. -config WARNINGS_ARE_ERRORS - bool - default n - config DCACHE_RAM_BASE hex default 0xc8000 Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Sat Sep 25 12:40:47 2010 (r5838) @@ -43,6 +43,7 @@ #include "superio/winbond/w83627thg/w83627thg.h" #include <pc80/mc146818rtc.h> +#include "option_table.h" #include <console/console.h> #include <cpu/x86/bist.h> Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Sat Sep 25 12:40:47 2010 (r5838) @@ -69,6 +69,9 @@ #include <stdlib.h> #include "arch/romcc_io.h" #include <pc80/mc146818rtc.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #include "amdk8.h" Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/northbridge/amd/amdk8/raminit.c Sat Sep 25 12:40:47 2010 (r5838) @@ -10,6 +10,9 @@ #include <reset.h> #include "raminit.h" #include "amdk8.h" +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Sat Sep 25 12:40:47 2010 (r5838) @@ -28,6 +28,9 @@ #include "raminit.h" #include "amdk8_f.h" #include <spd_ddr2.h> +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #ifndef QRANK_DIMM_SUPPORT #define QRANK_DIMM_SUPPORT 0 Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/northbridge/intel/e7520/raminit.c Sat Sep 25 12:40:47 2010 (r5838) @@ -23,6 +23,9 @@ #include <stdlib.h> #include "raminit.h" #include "e7520.h" +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #define BAR 0x40000000 @@ -619,11 +622,13 @@ } ecc = 2; - if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { +#if CONFIG_HAVE_OPTION_TABLE + if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); - } - else { + } else +#endif + { print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ Modified: trunk/src/northbridge/intel/e7525/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7525/raminit.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/northbridge/intel/e7525/raminit.c Sat Sep 25 12:40:47 2010 (r5838) @@ -23,6 +23,9 @@ #include <stdlib.h> #include "raminit.h" #include "e7525.h" +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif #define BAR 0x40000000 @@ -619,11 +622,13 @@ } ecc = 2; +#if CONFIG_HAVE_OPTION_TABLE if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); - } - else { + } else +#endif + { print_debug("ECC on\n"); } drc &= ~(3 << 20); /* clear the ecc bits */ Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/pc80/Makefile.inc Sat Sep 25 12:40:47 2010 (r5838) @@ -8,3 +8,4 @@ subdirs-y += vga $(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H) +$(obj)/pc80/mc146818rtc_early.initobj.o : $(OPTION_TABLE_H) Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/pc80/mc146818rtc.c Sat Sep 25 12:40:47 2010 (r5838) @@ -2,6 +2,9 @@ #include <pc80/mc146818rtc.h> #include <boot/coreboot_tables.h> #include <string.h> +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif /* control registers - Moto names */ Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/pc80/mc146818rtc_early.c Sat Sep 25 12:40:47 2010 (r5838) @@ -1,5 +1,8 @@ #include <pc80/mc146818rtc.h> #include <fallback.h> +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif #ifndef CONFIG_MAX_REBOOT_CNT #error "CONFIG_MAX_REBOOT_CNT not defined" Modified: trunk/src/pc80/serial.c ============================================================================== --- trunk/src/pc80/serial.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/src/pc80/serial.c Sat Sep 25 12:40:47 2010 (r5838) @@ -1,6 +1,9 @@ #include <lib.h> /* Prototypes */ #include <arch/io.h> #include "pc80/mc146818rtc.h" +#if CONFIG_USE_OPTION_TABLE +#include "option_table.h" +#endif /* Base Address */ #ifndef CONFIG_TTYS0_BASE Modified: trunk/util/options/build_opt_tbl.c ============================================================================== --- trunk/util/options/build_opt_tbl.c Sat Sep 25 01:37:25 2010 (r5837) +++ trunk/util/options/build_opt_tbl.c Sat Sep 25 12:40:47 2010 (r5838) @@ -591,6 +591,10 @@ /* Walk through the entry records */ ptr = (struct lb_record *)(cmos_table + hdr->header_length); end = (struct lb_record *)(cmos_table + hdr->size); + fprintf(fp, "/* This file is autogenerated.\n" + " * See mainboard's cmos.layout file.\n */\n\n" + "#ifndef __OPTION_TABLE_H\n#define __OPTION_TABLE_H\n\n"); + for(;ptr < end; ptr = (struct lb_record *)(((char *)ptr) + ptr->size)) { if (ptr->tag != LB_TAG_OPTION) { continue; @@ -620,6 +624,7 @@ unlink(tempfilename); exit(1); } + fprintf(fp, "\n#endif // __OPTION_TABLE_H\n"); fclose(fp); UNLINK_IF_NECESSARY(header);

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[commit] r5837 - in trunk/src/southbridge/amd: rs690 rs780 sb600 sb700
by repository service 25 Sep '10

25 Sep '10

Author: uwe Date: Sat Sep 25 01:37:25 2010 New Revision: 5837 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5837 Log: Make SB600/SB700 more similar for easier diffs (trivial). Also fixes random whitespace issues, typos, etc. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/rs690/chip.h trunk/src/southbridge/amd/rs780/chip.h trunk/src/southbridge/amd/sb600/sb600.c trunk/src/southbridge/amd/sb600/sb600_early_setup.c trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c trunk/src/southbridge/amd/sb600/sb600_hda.c trunk/src/southbridge/amd/sb600/sb600_sm.c trunk/src/southbridge/amd/sb600/sb600_smbus.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c trunk/src/southbridge/amd/sb700/sb700_ide.c trunk/src/southbridge/amd/sb700/sb700_smbus.c Modified: trunk/src/southbridge/amd/rs690/chip.h ============================================================================== --- trunk/src/southbridge/amd/rs690/chip.h Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/rs690/chip.h Sat Sep 25 01:37:25 2010 (r5837) @@ -20,13 +20,13 @@ #ifndef RS690_CHIP_H #define RS690_CHIP_H -/* Member variables are defined in Config.lb. */ +/* Member variables are defined in devicetree.cb. */ struct southbridge_amd_rs690_config { u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ - u8 gfx_dual_slot; /* Is it dual graphics slots */ + u8 gfx_dual_slot; /* Is it dual graphics slots */ u8 gfx_lane_reversal; /* Single/Dual slot lan reversal */ u8 gfx_tmds; /* whether support TMDS? */ u8 gfx_compliance; /* whether support compliance? */ Modified: trunk/src/southbridge/amd/rs780/chip.h ============================================================================== --- trunk/src/southbridge/amd/rs780/chip.h Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/rs780/chip.h Sat Sep 25 01:37:25 2010 (r5837) @@ -20,7 +20,7 @@ #ifndef RS780_CHIP_H #define RS780_CHIP_H -/* Member variables are defined in Config.lb. */ +/* Member variables are defined in devicetree.cb. */ struct southbridge_amd_rs780_config { u8 gppsb_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ Modified: trunk/src/southbridge/amd/sb600/sb600.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600.c Sat Sep 25 01:37:25 2010 (r5837) @@ -120,21 +120,21 @@ printk(BIOS_DEBUG, "sb600_enable()\n"); -/* -* 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 -* 0:13.1 USB-1 bit 2 of sm_dev 0x68 -* 0:13.2 USB-2 bit 3 of sm_dev 0x68 -* 0:13.3 USB-3 bit 4 of sm_dev 0x68 -* 0:13.4 USB-4 bit 5 of sm_dev 0x68 -* 0:13.5 USB2 bit 0 of sm_dev 0x68 : 1 - enable, default -* 0:14.0 SMBUS 0 -* 0:14.1 IDE 1 -* 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 -* 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 -* 0:14.4 PCI 4 -* 0:14.5 ACI bit 0 of pm_io 0x59 : 0 - enable, default -* 0:14.6 MCI bit 1 of pm_io 0x59 : 0 - enable, default -*/ + /* + * 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 + * 0:13.1 USB-1 bit 2 of sm_dev 0x68 + * 0:13.2 USB-2 bit 3 of sm_dev 0x68 + * 0:13.3 USB-3 bit 4 of sm_dev 0x68 + * 0:13.4 USB-4 bit 5 of sm_dev 0x68 + * 0:13.5 USB2 bit 0 of sm_dev 0x68 : 1 - enable, default + * 0:14.0 SMBUS 0 + * 0:14.1 IDE 1 + * 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 + * 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 + * 0:14.4 PCI 4 + * 0:14.5 ACI bit 0 of pm_io 0x59 : 0 - enable, default + * 0:14.6 MCI bit 1 of pm_io 0x59 : 0 - enable, default + */ if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Sat Sep 25 01:37:25 2010 (r5837) @@ -25,7 +25,6 @@ #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ /*SIZE 0x40 */ - static void pmio_write(u8 reg, u8 value) { outb(reg, PM_INDEX); @@ -38,7 +37,7 @@ return inb(PM_INDEX + 1); } -/* Get SB ASIC Revision.*/ +/* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { device_t dev; @@ -131,22 +130,21 @@ return (dev >> 15) & 0x1f; } - static u8 dual_core(void) { return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0; } /* -SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default. -RPR 2.3.3 C-state and VID/FID change for the K8 platform. + * SB600 VFSMAF (VID/FID System Management Action Field) is 010b by default. + * RPR 2.3.3 C-state and VID/FID change for the K8 platform. */ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) { u8 byte; byte = pmio_read(0x9a); byte &= ~0x34; - if(dual_core()) + if (dual_core()) byte |= 0x34; else byte |= 0x04; @@ -170,11 +168,11 @@ byte |= 0x01; pmio_write(0x7c, byte); - /*Must be 0 for K8 platform.*/ + /* Must be 0 for K8 platform. */ byte = pmio_read(0x68); byte &= ~0x01; pmio_write(0x68, byte); - /*Must be 0 for K8 platform.*/ + /* Must be 0 for K8 platform. */ byte = pmio_read(0x8d); byte &= ~(1<<6); pmio_write(0x8d, byte); @@ -187,7 +185,7 @@ byte &= ~0x04; pmio_write(0x42, byte); - if(get_sb600_revision() == 0x14) { + if (get_sb600_revision() == 0x14) { pmio_write(0x89, 0x10); byte = pmio_read(0x52); @@ -196,7 +194,6 @@ } } - void hard_reset(void) { set_bios_reset(); @@ -277,7 +274,6 @@ pci_write_config8(dev, 0x4a, byte); } - /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Sat Sep 25 01:37:25 2010 (r5837) @@ -20,14 +20,12 @@ #include <usbdebug.h> #ifndef SB600_DEVN_BASE - #define SB600_DEVN_BASE 0 - #endif -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 -#define EHCI_DEBUG_OFFSET 0xE0 +#define EHCI_BAR_INDEX 0x10 +#define EHCI_BAR 0xFEF00000 +#define EHCI_DEBUG_OFFSET 0xE0 /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -39,5 +37,5 @@ set_debug_port(port); pci_write_config32(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ } Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_hda.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600_hda.c Sat Sep 25 01:37:25 2010 (r5837) @@ -151,6 +151,7 @@ 0x01f71ec4, 0x01f71f01, }; + static u32 find_verb(u32 viddid, u32 ** verb) { device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); @@ -171,7 +172,6 @@ * Wait 50usec for for the codec to indicate it is ready * no response would imply that the codec is non-operative */ - static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the @@ -194,7 +194,6 @@ * the previous command. No response would imply that the code * is non-operative */ - static int wait_for_valid(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the @@ -301,7 +300,7 @@ if (!res) return; - base = ((u32)res->base); + base = (u32)res->base; printk(BIOS_DEBUG, "base = 0x%x\n", base); codec_mask = codec_detect(base); Modified: trunk/src/southbridge/amd/sb600/sb600_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sm.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600_sm.c Sat Sep 25 01:37:25 2010 (r5837) @@ -327,10 +327,10 @@ res->gran = 8; res->flags = IORESOURCE_IO | IORESOURCE_FIXED; - compact_resources(dev); } + static void sb600_sm_set_resources(struct device *dev) { struct resource *res; @@ -338,7 +338,6 @@ pci_dev_set_resources(dev); - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ byte = pm_ioread(0x52); byte |= 1 << 6; @@ -357,6 +356,7 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; + static struct device_operations smbus_ops = { .read_resources = sb600_sm_read_resources, .set_resources = sb600_sm_set_resources, @@ -367,6 +367,7 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_ATI, Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.c Sat Sep 25 01:37:25 2010 (r5837) @@ -114,8 +114,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -145,8 +144,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -176,8 +174,7 @@ return 0; } -static void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) +static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp; Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sat Sep 25 01:37:25 2010 (r5837) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB700_EARLY_SETUP_C_ -#define _SB700_EARLY_SETUP_C_ +#ifndef _SB700_EARLY_SETUP_C_ +#define _SB700_EARLY_SETUP_C_ #include <reset.h> #include <arch/cpu.h> @@ -40,7 +40,7 @@ return inb(PM_INDEX + 1); } -/* RPR 2.28 Get SB ASIC Revision.*/ +/* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { device_t dev; @@ -195,11 +195,11 @@ byte |= 0x03; pmio_write(0x7c, byte); - /*Must be 0 for K8 platform.*/ + /* Must be 0 for K8 platform. */ byte = pmio_read(0x68); byte &= ~0x01; pmio_write(0x68, byte); - /*Must be 0 for K8 platform.*/ + /* Must be 0 for K8 platform. */ byte = pmio_read(0x8d); byte &= ~(1<<6); pmio_write(0x8d, byte); Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sat Sep 25 01:37:25 2010 (r5837) @@ -20,14 +20,12 @@ #include <usbdebug.h> #ifndef SB700_DEVN_BASE - #define SB700_DEVN_BASE 0 - #endif -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 -#define EHCI_DEBUG_OFFSET 0xE0 +#define EHCI_BAR_INDEX 0x10 +#define EHCI_BAR 0xFEF00000 +#define EHCI_DEBUG_OFFSET 0xE0 /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -39,5 +37,5 @@ set_debug_port(port); pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ } Modified: trunk/src/southbridge/amd/sb700/sb700_ide.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_ide.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb700/sb700_ide.c Sat Sep 25 01:37:25 2010 (r5837) @@ -51,7 +51,7 @@ pci_write_config16(dev, 0x4, dword); /* set ide as primary, if you want to boot from IDE, you'd better set it - * in mainboard/Config.lb */ + * in $vendor/$mainboard/devicetree.cb */ if (conf->boot_switch_sata_ide == 1) { byte = pci_read_config8(dev, 0xAD); byte |= 1 << 4; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.c Sat Sep 25 00:15:54 2010 (r5836) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Sat Sep 25 01:37:25 2010 (r5837) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB700_SMBUS_C_ -#define _SB700_SMBUS_C_ +#ifndef _SB700_SMBUS_C_ +#define _SB700_SMBUS_C_ #include "sb700_smbus.h" @@ -90,8 +90,7 @@ return byte; } -int do_smbus_send_byte(u32 smbus_io_base, u32 device, - u8 val) +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; @@ -118,8 +117,7 @@ return 0; } -int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) { u8 byte; @@ -149,8 +147,7 @@ return byte; } -int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) { u8 byte; @@ -180,8 +177,7 @@ return 0; } -static void alink_ab_indx(u32 reg_space, u32 reg_addr, - u32 mask, u32 val) +static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp;

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[commit] r5836 - trunk
by repository service 25 Sep '10

25 Sep '10

Author: oxygene Date: Sat Sep 25 00:15:54 2010 New Revision: 5836 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5836 Log: Fix CCACHE handling, and make use of ccache's BASEDIR feature Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Sep 24 20:42:56 2010 (r5835) +++ trunk/Makefile Sat Sep 25 00:15:54 2010 (r5836) @@ -88,7 +88,7 @@ else -include $(top)/.config +include $(HAVE_DOTCONFIG) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) @@ -98,10 +98,11 @@ endif ifeq ($(CONFIG_CCACHE),y) -CCACHE:=CCACHE_COMPILERCHECK=content $(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH)))) +CCACHE:=$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH)))) ifeq ($(CCACHE),) $(error ccache selected, but not found in PATH) endif +CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_BASEDIR=$(top) $(CCACHE) CC := $(CCACHE) $(CC) HOSTCC := $(CCACHE) $(HOSTCC) HOSTCXX := $(CCACHE) $(HOSTCXX)

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coreboot September 2010