coreboot September 2010

coreboot@coreboot.org

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324 discussions

[PATCH]Improve ccache handling
by Patrick Georgi 25 Sep '10

25 Sep '10

Hi, attached patch improves ccache handling (and requires ccache 3.1 to work properly, at least in my tests). coreboot file names are now normalized to the base directory before hashing, allowing multiple trees to share the same cache more efficiently. This will greatly benefit the build bot. It also fixes a bug ($(CCACHE) was never empty, so the test for the existence of ccache never failed) While we're at it, remove a redundant explicit use of ".config", to allow to use config files of a different name slightly more easily in the future. The only thing that's accountable for cache misses on a seeded cache is now the date/time values in config.h - I tested that by replacing them with bogus values, but the runtime benefit was negligible. I also found that we might be able to use __DATE__ and __TIME__ (preprocessor macros) instead of calling date(1). Any opinion on that? Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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build service results for r5834
by repository service 24 Sep '10

24 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5834 to the coreboot repository. This caused the following changes: Change Log: Undo stupid mistake in r5832 Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of hp:dl165_g6_fam10 has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5833
by repository service 24 Sep '10

24 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 5833 to the coreboot repository. This caused the following changes: Change Log: Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of hp:dl165_g6_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5833&device=dl165_g6_fam10… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5835 - in trunk/src/mainboard: tyan/s2735 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s4880 tyan/s4882 via/epia-n via/pc2500e via/vt8454c
by repository service 24 Sep '10

24 Sep '10

Author: oxygene Date: Fri Sep 24 20:42:56 2010 New Revision: 5835 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5835 Log: Automatically fetch bus information for mptable from the device tree, instead of using hardcoded values. If this changes behaviour, this is either - a bug in mptable_write_buses(), or - a bug in the old mptable or device config, that is they were inconsistent. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/tyan/s2735/mptable.c trunk/src/mainboard/tyan/s2850/mptable.c trunk/src/mainboard/tyan/s2875/mptable.c trunk/src/mainboard/tyan/s2880/mptable.c trunk/src/mainboard/tyan/s4880/mptable.c trunk/src/mainboard/tyan/s4882/mptable.c trunk/src/mainboard/via/epia-n/mptable.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/mainboard/via/vt8454c/mptable.c Modified: trunk/src/mainboard/tyan/s2735/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s2735/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -10,6 +10,7 @@ static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2735 "; struct mp_config_table *mc; + int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -29,15 +30,7 @@ mc->reserved = 0; smp_write_processors(mc); - - -/*Bus: Bus ID Type*/ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 3, "PCI "); - smp_write_bus(mc, 4, "PCI "); - smp_write_bus(mc, 5, "ISA "); + mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, 0xfec00000); { @@ -58,7 +51,7 @@ } } } - mptable_add_isa_interrupts(mc, 0x5, 0x8, 0); + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ Modified: trunk/src/mainboard/tyan/s2850/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s2850/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -50,8 +50,7 @@ static const char productid[12] = "S2850 "; struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned apicid_base; @@ -88,23 +87,15 @@ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8111_1 = 2; - bus_isa = 3; } } /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/tyan/s2875/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s2875/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -48,8 +48,7 @@ static const char productid[12] = "S2875 "; struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_chain_0; unsigned char bus_8111_1; unsigned char bus_8151_1; @@ -89,15 +88,11 @@ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 3; - bus_isa = 4; } /* 8151 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); @@ -116,11 +111,7 @@ } /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/tyan/s2880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s2880/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -50,8 +50,7 @@ static const char productid[12] = "S2880 "; struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; @@ -94,14 +93,11 @@ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; - bus_isa = 5; } /* 8131-1 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); @@ -128,12 +124,7 @@ } /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/tyan/s4880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s4880/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -48,8 +48,7 @@ static const char productid[12] = "S4880 "; struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; @@ -93,14 +92,11 @@ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; - bus_isa = 5; } /* 8131-1 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); @@ -127,12 +123,7 @@ } /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/tyan/s4882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/tyan/s4882/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -49,8 +49,7 @@ static const char productid[12] = "S4882 "; struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; @@ -94,14 +93,11 @@ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); bus_8111_1 = 4; - bus_isa = 5; } /* 8131-1 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); @@ -128,12 +124,7 @@ } /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/via/epia-n/mptable.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/via/epia-n/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -12,6 +12,7 @@ static const char oem[8] = "COREBOOT"; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; + int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -31,12 +32,8 @@ mc->reserved = 0; smp_write_processors(mc); + mptable_write_buses(mc, NULL, &isa_bus); - -/*Bus: Bus ID Type*/ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { @@ -71,7 +68,7 @@ } } } - mptable_add_isa_interrupts(mc, 0x2, 0x2, 0); + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/via/pc2500e/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -29,9 +29,6 @@ #include <stdint.h> #include "../../../southbridge/via/vt8237r/vt8237r.h" - -#define bus_isa 2 - static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -39,7 +36,7 @@ static const char productid[12] = "PC2500 "; struct mp_config_table *mc; - int bus_num; + int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -59,21 +56,13 @@ mc->reserved = 0; smp_write_processors(mc); - - -/* Bus: Bus ID Type*/ - /* define numbers for pci and isa bus */ - for (bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); - + mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE); /* Now, assemble the table. */ - mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \ Modified: trunk/src/mainboard/via/vt8454c/mptable.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/mptable.c Fri Sep 24 20:28:50 2010 (r5834) +++ trunk/src/mainboard/via/vt8454c/mptable.c Fri Sep 24 20:42:56 2010 (r5835) @@ -33,6 +33,7 @@ static const char oem[8] = "COREBOOT"; static const char productid[12] = "VIA VT8454C "; struct mp_config_table *mc; + int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -52,18 +53,12 @@ mc->reserved = 0; smp_write_processors(mc); - - /*Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 128, "PCI "); - smp_write_bus(mc, 129, "ISA "); + mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, 2, 17, 0xfec00000); - mptable_add_isa_interrupts(mc, 0x81, 0x2, 0); + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x14);

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[commit] r5832 - trunk/src/mainboard/hp/dl165_g6_fam10
by repository service 24 Sep '10

24 Sep '10

Author: oxygene Date: Fri Sep 24 20:12:46 2010 New Revision: 5832 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5832 Log: Fix hp/dl165_g6_fam10 build. Failed to take r5800 and another recent change into account. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Modified: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri Sep 24 19:35:32 2010 (r5831) +++ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri Sep 24 20:12:46 2010 (r5832) @@ -9,6 +9,8 @@ select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 select SUPERIO_NSC_PC87417 + select DIMM_DDR2 + select DIMM_REGISTERED select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Sep 24 19:35:32 2010 (r5831) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Sep 24 20:12:46 2010 (r5832) @@ -54,6 +54,7 @@ #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h"

3 2

build service results for r5832
by repository service 24 Sep '10

24 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5832 to the coreboot repository. This caused the following changes: Change Log: Fix hp/dl165_g6_fam10 build. Failed to take r5800 and another recent change into account. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of hp:dl165_g6_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5832&device=dl165_g6_fam10… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5834 - trunk/src/mainboard/hp/dl165_g6_fam10
by repository service 24 Sep '10

24 Sep '10

Author: oxygene Date: Fri Sep 24 20:28:50 2010 New Revision: 5834 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5834 Log: Undo stupid mistake in r5832 Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Sep 24 20:18:20 2010 (r5833) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Sep 24 20:28:50 2010 (r5834) @@ -54,7 +54,6 @@ #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h"

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[commit] r5833 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh mainboard/as...
by repository service 24 Sep '10

24 Sep '10

Author: uwe Date: Fri Sep 24 20:18:20 2010 New Revision: 5833 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5833 Log: Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure. Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -123,6 +128,12 @@ /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/amd/mahogany/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -52,6 +52,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -122,6 +127,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/amd/pistachio/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -46,6 +46,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -117,8 +122,14 @@ sb600_lpc_init(); /* Pistachio used a FPGA to enable serial debug instead of a SIO - * and it doens't require any special setup. */ + * and it doesn't require any special setup. */ uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); post_code(0x03); Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -176,6 +181,12 @@ sio_init(); w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8712f/it8712f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -139,6 +145,12 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */ uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -56,6 +56,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -134,6 +140,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -60,6 +60,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -138,6 +144,12 @@ it8718f_enable_serial(0, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -63,6 +63,12 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/fintek/f71859/f71859_early_serial.c" + +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -141,6 +147,12 @@ f71859_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -67,6 +67,11 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -146,6 +151,12 @@ f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb700_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); printk(BIOS_DEBUG, "\n"); Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/kontron/kt690/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -54,6 +54,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -125,6 +130,12 @@ dev=PNP_DEV(0x2e, W83627DHG_SP1); w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -130,6 +135,12 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Fri Sep 24 20:18:20 2010 (r5833) @@ -53,6 +53,11 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -124,6 +129,12 @@ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Fri Sep 24 20:18:20 2010 (r5833) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <usbdebug.h> + #ifndef SB600_DEVN_BASE #define SB600_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb600_enable_usbdebug(u32 port) { set_debug_port(port); Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Fri Sep 24 20:12:46 2010 (r5832) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Fri Sep 24 20:18:20 2010 (r5833) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <usbdebug.h> + #ifndef SB700_DEVN_BASE #define SB700_DEVN_BASE 0 @@ -27,6 +29,11 @@ #define EHCI_BAR 0xFEF00000 #define EHCI_DEBUG_OFFSET 0xE0 +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ +} + static void sb700_enable_usbdebug(u32 port) { set_debug_port(port);

1 0

build service results for r5831
by repository service 24 Sep '10

24 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5831 to the coreboot repository. This caused the following changes: Change Log: Add support for HP DL165-G6 with Fam10 CPU. Original patch was Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Updates to accomodate changes in coreboot are Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of hp:dl165_g6_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5831&device=dl165_g6_fam10… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH]some more bus entry in mptables derived from device tree
by Patrick Georgi 24 Sep '10

24 Sep '10

Hi, attached patch derives coreboot create bus data in the mptable automatically from the device tree for a couple more boards. It's build tested, but not run tested. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 2

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coreboot September 2010