coreboot September 2010

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[commit] r5850 - trunk/util/dump_mmcr
by repository service 26 Sep '10

26 Sep '10

Author: stepan Date: Sun Sep 26 17:04:14 2010 New Revision: 5850 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5850 Log: update license header for dumpmmcr utility according to svn history. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/dump_mmcr/dumpmmcr.c Modified: trunk/util/dump_mmcr/dumpmmcr.c ============================================================================== --- trunk/util/dump_mmcr/dumpmmcr.c Sun Sep 26 12:34:36 2010 (r5849) +++ trunk/util/dump_mmcr/dumpmmcr.c Sun Sep 26 17:04:14 2010 (r5850) @@ -1,24 +1,25 @@ /* * dump mmcr of Elan520 uController (incomplete, see 22005b pg23+). * + * Copyright 2005 Ronald G. Minnich * Copyright 2006 coresystems GmbH - * Stefan Reinauer <stepan(a)coresystems.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + #include <errno.h> #include <fcntl.h> #include <sys/mman.h>

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build service results for r5849
by repository service 26 Sep '10

26 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 5849 to the coreboot repository. This caused the following changes: Change Log: Fix the build, CONFIG_USBDEBUG must always be defined (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of advantech:pcm-5820 has been fixed Compilation of amd:db800 has been fixed Compilation of amd:norwich has been fixed Compilation of amd:rumba has been fixed Compilation of amd:serengeti_cheetah has been fixed Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of arima:hdama has been fixed Compilation of artecgroup:dbe61 has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of axus:tc320 has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of bcom:winnet100 has been fixed Compilation of bcom:winnetp680 has been fixed Compilation of biostar:m6tba has been fixed Compilation of broadcom:blast has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of digitallogic:msm800sev has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of ecs:p6iwp-fe has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of gigabyte:ga-6bxe has been fixed Compilation of hp:dl145_g1 has been fixed Compilation of hp:dl145_g3 has been fixed Compilation of hp:dl165_g6_fam10 has been fixed Compilation of hp:e_vectra_p2706t has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of iei:pcisa-lx-800-r10 has been fixed Compilation of intel:d810e2cb has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of jetway:j7f24 has been fixed Compilation of lanner:em8510 has been fixed Compilation of lippert:frontrunner has been fixed Compilation of lippert:hurricane-lx has been fixed Compilation of lippert:literunner-lx has been fixed Compilation of lippert:roadrunner-lx has been fixed Compilation of lippert:spacerunner-lx has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms9185 has been fixed Compilation of nec:powermate2000 has been fixed Compilation of newisys:khepri has been fixed Compilation of nokia:ip530 has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of pcengines:alix1c has been fixed Compilation of pcengines:alix2d has been fixed Compilation of rca:rm4100 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of thomson:ip1000 has been fixed Compilation of traverse:geos has been fixed Compilation of tyan:s1846 has been fixed Compilation of tyan:s2735 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-m700 has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed Compilation of via:vt8454c has been fixed Compilation of winent:pl6064 has been fixed Compilation of wyse:s50 has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5849 - trunk/src/console
by repository service 26 Sep '10

26 Sep '10

Author: uwe Date: Sun Sep 26 12:34:36 2010 New Revision: 5849 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5849 Log: Fix the build, CONFIG_USBDEBUG must always be defined (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/console/Kconfig Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Sun Sep 26 09:35:55 2010 (r5848) +++ trunk/src/console/Kconfig Sun Sep 26 12:34:36 2010 (r5849) @@ -89,6 +89,9 @@ def_bool n config USBDEBUG + def_bool n + +config USBDEBUG bool "USB 2.0 EHCI debug dongle support" default n depends on HAVE_USBDEBUG

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[PATCH] Move HAVE_HARD_RESET from mainboard config to i82801bx southbridge config.
by Warren Turkal 26 Sep '10

26 Sep '10

The intel/d810e2cb is the only board using the i82801bx southbridge. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/mainboard/intel/d810e2cb/Kconfig | 1 - src/southbridge/intel/i82801bx/Kconfig | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 3031a30..8c6c76b 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801BX select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE - select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 0c9089a..4b307d5 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,4 +19,5 @@ config SOUTHBRIDGE_INTEL_I82801BX bool + select HAVE_HARD_RESET -- 1.7.1

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[PATCH] Remove hard reset config from some mainboard configs
by Warren Turkal 26 Sep '10

26 Sep '10

Most of the mainboards with i82801gx SBs seem to use the HAVE_HARD_RESET, which is already selected in the i82801gx SB config. Removing it from some of those boards should be a functional no-op. Thanks, wt Warren Turkal (1): Remove HAVE_HARD_RESET from boards with i82801gx southbridge. src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - 4 files changed, 0 insertions(+), 4 deletions(-)

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[PATCH] fix cpu config option name
by Warren Turkal 26 Sep '10

26 Sep '10

All Intel CPU models appear to be identified with the form INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form. A side effect is that the CPU doesn't need to be listed on the boards that support it since the socket identifies the CPUs it supports. Thanks, wt Warren Turkal (1): Normalize the config option for the Intel Atom CPU. src/cpu/intel/model_106cx/Kconfig | 2 +- src/mainboard/intel/d945gclf/Kconfig | 1 - 2 files changed, 1 insertions(+), 2 deletions(-)

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build service results for r5848
by repository service 26 Sep '10

26 Sep '10

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[commit] r5848 - in trunk/src: console southbridge/amd/sb600 southbridge/amd/sb700 southbridge/intel/i82801gx southbridge/nvidia/mcp55 southbridge/sis/sis966
by repository service 26 Sep '10

26 Sep '10

Author: uwe Date: Sun Sep 26 09:35:55 2010 New Revision: 5848 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5848 Log: Only show the USB Debug Port kconfig option to the user if a mainboard is selected that uses a chipset which actually has that functionality _and_ we have code to initialize the Debug Port in coreboot (for that chipset). Also, remove the duplicate list of PCI IDs and just link to the wiki page at: http://www.coreboot.org/EHCI_Debug_Port The list is now less useful in the kconfig help as this option will only appear for those boards where it's actually supported. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/console/Kconfig trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb700/Kconfig trunk/src/southbridge/intel/i82801gx/Kconfig trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/sis/sis966/Kconfig Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/console/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -84,38 +84,30 @@ default 3 depends on CONSOLE_SERIAL8250 -# TODO: FIX DEPENDENCY HERE +# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. +config HAVE_USBDEBUG + def_bool n + config USBDEBUG bool "USB 2.0 EHCI debug dongle support" default n + depends on HAVE_USBDEBUG help This option allows you to use a so-called USB EHCI Debug device + (such as the Ajays NET20DC, AMIDebug RX, or a system using the + Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port). This feature is NOT supported on all chipsets in coreboot! It also requires a USB2 controller which supports the EHCI - Debug Port capability. Controllers which are known to work: + Debug Port capability. - * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) - * 8086:24cd Intel ICH4/ICH4-M - * 8086:24dd Intel ICH5 - * 8086:265c Intel ICH6 - * 8086:268c Intel 631xESB/632xESB/3100 - * 8086:27cc Intel ICH7 - * 8086:2836 Intel ICH8 - * 8086:283a Intel ICH8 - * 8086:293a Intel ICH9 - * 10de:0088 NVIDIA MCP2A - * 10de:005b NVIDIA CK804 - * 10de:026e NVIDIA MCP51 - * 10de:036d NVIDIA MCP55 - * 10de:03f2 NVIDIA MCP61 - * 1002:4386 ATI/AMD SB600 - * 1106:3104 VIA VX800 + See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list + of supported controllers. - See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list. + If unsure, say N. config CONSOLE_VGA bool "Use VGA console once initialized" Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/southbridge/amd/sb600/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -20,3 +20,5 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC + select HAVE_USBDEBUG + Modified: trunk/src/southbridge/amd/sb700/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb700/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/southbridge/amd/sb700/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -20,6 +20,7 @@ config SOUTHBRIDGE_AMD_SB700 bool select IOAPIC + select HAVE_USBDEBUG config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -21,5 +21,6 @@ bool select IOAPIC select HAVE_HARD_RESET + select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -1,6 +1,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select IOAPIC + select HAVE_USBDEBUG config ID_SECTION_OFFSET hex Modified: trunk/src/southbridge/sis/sis966/Kconfig ============================================================================== --- trunk/src/southbridge/sis/sis966/Kconfig Sun Sep 26 01:47:15 2010 (r5847) +++ trunk/src/southbridge/sis/sis966/Kconfig Sun Sep 26 09:35:55 2010 (r5848) @@ -1,6 +1,7 @@ config SOUTHBRIDGE_SIS_SIS966 bool select IOAPIC + select HAVE_USBDEBUG config ID_SECTION_OFFSET hex

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[commit] r5847 - in trunk/src/southbridge: amd/sb600 amd/sb700 intel/i82801gx nvidia/mcp55 sis/sis966
by repository service 26 Sep '10

26 Sep '10

Author: uwe Date: Sun Sep 26 01:47:15 2010 New Revision: 5847 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5847 Log: Various Debug Port southbridge implementation fixes / cosmetics. - Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of hardcoding their values. - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE. - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC. - s/uint32_t/u32/. - Cosmetics, whitespace, coding style fixes and added code comments. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Sat Sep 25 19:24:10 2010 (r5846) +++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Sun Sep 26 01:47:15 2010 (r5847) @@ -17,25 +17,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <usbdebug.h> +#include <device/pci_def.h> -#ifndef SB600_DEVN_BASE -#define SB600_DEVN_BASE 0 -#endif - -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 -#define EHCI_DEBUG_OFFSET 0xE0 +#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ +#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ +#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { + /* TODO: Allow changing the physical USB port used as Debug Port. */ } -static void sb600_enable_usbdebug(u32 port) +static void sb600_enable_usbdebug(unsigned int port) { + device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ + + /* Select the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); - pci_write_config32(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), - EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB600_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sat Sep 25 19:24:10 2010 (r5846) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sun Sep 26 01:47:15 2010 (r5847) @@ -17,25 +17,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <usbdebug.h> +#include <device/pci_def.h> -#ifndef SB700_DEVN_BASE -#define SB700_DEVN_BASE 0 -#endif - -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 -#define EHCI_DEBUG_OFFSET 0xE0 +#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ +#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ +#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { + /* TODO: Allow changing the physical USB port used as Debug Port. */ } -static void sb700_enable_usbdebug(u32 port) +static void sb700_enable_usbdebug(unsigned int port) { + device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ + + /* Select the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); - pci_write_config32(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), - EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB700_DEVN_BASE + 0x13, 5), 0x04, 0x2); /* mem space enable */ + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Sat Sep 25 19:24:10 2010 (r5846) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Sun Sep 26 01:47:15 2010 (r5847) @@ -17,16 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <usbdebug.h> +#include <device/pci_def.h> -// An arbitrary address for the BAR -#define EHCI_BAR 0xFEF00000 -// These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit) -#define EHCI_BAR_INDEX 0x10 - -#define EHCI_CONFIG_FLAG 0x40 -#define EHCI_PORTSC 0x44 -#define EHCI_DEBUG_OFFSET 0xA0 +#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ +#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */ +#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */ /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -37,13 +34,17 @@ static void i82801gx_enable_usbdebug(unsigned int port) { u32 dbgctl; + device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ - pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of the Debug Port to the EHCI controller. */ printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); } - Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Sat Sep 25 19:24:10 2010 (r5846) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Sun Sep 26 01:47:15 2010 (r5847) @@ -21,32 +21,42 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include <usbdebug.h> +#include <device/pci_def.h> + #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 +#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ +#define EHCI_BAR_INDEX 0x10 #define EHCI_DEBUG_OFFSET 0x98 -#include <usbdebug.h> - -void set_debug_port(unsigned port) +void set_debug_port(unsigned int port) { - uint32_t dword; - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74); - dword &= ~(0xf<<12); - dword |= (port<<12); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x74, dword); + u32 dword; + device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + /* Write the port number to 0x74[15:12]. */ + dword = pci_read_config32(dev, 0x74); + dword &= ~(0xf << 12); + dword |= (port << 12); + pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned port) +static void mcp55_enable_usbdebug(unsigned int port) { + device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ + + /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe -} + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); +} Modified: trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Sat Sep 25 19:24:10 2010 (r5846) +++ trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Sun Sep 26 01:47:15 2010 (r5847) @@ -21,32 +21,44 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* TODO: Check whether this actually works (might be copy-paste leftover). */ + +#include <stdint.h> +#include <usbdebug.h> +#include <device/pci_def.h> + #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE - #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE #else - #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR_INDEX 0x10 -#define EHCI_BAR 0xFEF00000 +#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ +#define EHCI_BAR_INDEX 0x10 #define EHCI_DEBUG_OFFSET 0x98 -#include <usbdebug.h> - -void set_debug_port(unsigned port) +void set_debug_port(unsigned int port) { - uint32_t dword; - dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x74); - dword &= ~(0xf<<12); - dword |= (port<<12); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x74, dword); + u32 dword; + device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + /* Write the port number to 0x74[15:12]. */ + dword = pci_read_config32(dev, 0x74); + dword &= ~(0xf << 12); + dword |= (port << 12); + pci_write_config32(dev, 0x74, dword); } -static void sis966_enable_usbdebug(unsigned port) +static void sis966_enable_usbdebug(unsigned int port) { + device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ + + /* Mark the requested physical USB port (1-15) as the Debug Port. */ set_debug_port(port); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+2, 1), 0x04, 0x2); // mem space enabe -} + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); +}

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build service results for r5846
by repository service 25 Sep '10

25 Sep '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5846 to the coreboot repository. This caused the following changes: Change Log: Mark read-only data as read-only, so the global vars test doesn't fail on it. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been fixed Compilation of hp:dl165_g6_fam10 has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of tyan:s2912_fam10 has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot September 2010