coreboot September 2010

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[PATCH] Factor out hardcoded USB Debug port defines to kconfig
by Uwe Hermann 27 Sep '10

27 Sep '10

This fixes issue #161: http://tracker.coreboot.org/trac/coreboot/ticket/161 Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r5860 - in trunk/src: console mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/msi/ms7260 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv mainboard/tyan/s2912 mainboa...
by repository service 27 Sep '10

27 Sep '10

Author: uwe Date: Mon Sep 27 20:03:18 2010 New Revision: 5860 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5860 Log: Add a kconfig option to allow the user to select a specific physical USB port for use as Debug Port (on chipsets which support that). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/console/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/console/Kconfig Mon Sep 27 20:03:18 2010 (r5860) @@ -112,6 +112,27 @@ If unsure, say N. +# Note: This option doesn't make sense on Intel ICH southbridges as those +# hardcode the physical USB port to be used as Debug Port to 1. It cannot +# be changed by coreboot. +config USBDEBUG_DEFAULT_PORT + int "Default USB port to use as Debug Port" + default 1 + depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX + help + This option selects which physical USB port coreboot will try to + use as EHCI Debug Port first (valid values are: 1-15). + + If coreboot doesn't detect an EHCI Debug Port dongle on this port, + it will try all the other ports one after the other. This will take + a few seconds of time though, and thus slow down the booting process. + + Hence, if you select the correct port here, you can speed up + your boot time. Which USB port number (1-15) refers to which + actual port on your mainboard (potentially also USB pin headers + on your mainboard) is highly board-specific, and you'll likely + have to find out by trial-and-error. + config CONSOLE_VGA bool "Use VGA console once initialized" default n Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -40,8 +40,6 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -196,7 +194,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - sis966_enable_usbdebug(DBGP_DEFAULT); + sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -38,8 +38,6 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -212,7 +210,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/msi/ms7260/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -42,8 +42,6 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -181,7 +179,7 @@ uart_init(); report_bist_failure(bist); /* Halt upon BIST failure. */ #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -33,8 +33,6 @@ #define SET_FIDVID 1 #define SET_FIDVID_CORE_RANGE 0 -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -185,7 +183,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -38,8 +38,6 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -198,7 +196,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/tyan/s2912/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -38,8 +38,6 @@ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -192,7 +190,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Sep 27 19:53:17 2010 (r5859) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Sep 27 20:03:18 2010 (r5860) @@ -33,8 +33,6 @@ #define SET_FIDVID 1 #define SET_FIDVID_CORE_RANGE 0 -#define DBGP_DEFAULT 7 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -180,7 +178,7 @@ report_bist_failure(bist); #if CONFIG_USBDEBUG - mcp55_enable_usbdebug(DBGP_DEFAULT); + mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif

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[commit] r5859 - trunk/src/cpu/x86
by repository service 27 Sep '10

27 Sep '10

Author: uwe Date: Mon Sep 27 19:53:17 2010 New Revision: 5859 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5859 Log: Add a few missing license headers based on svn logs, and also add a few more code comments to src/cpu/x86/*.inc files. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/x86/fpu_enable.inc trunk/src/cpu/x86/mmx_disable.inc trunk/src/cpu/x86/sse_disable.inc trunk/src/cpu/x86/sse_enable.inc Modified: trunk/src/cpu/x86/fpu_enable.inc ============================================================================== --- trunk/src/cpu/x86/fpu_enable.inc Mon Sep 27 13:11:09 2010 (r5858) +++ trunk/src/cpu/x86/fpu_enable.inc Mon Sep 27 19:53:17 2010 (r5859) @@ -1,10 +1,39 @@ - /* preserve BIST in %eax */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + __fpu_start: - movl %eax, %ebp + /* Preserve BIST. */ + movl %eax, %ebp - /* Disable floating point emulation */ + /* + * Clear the CR0[2] bit (the "Emulation" flag, EM). + * + * This indicates that the processor has an (internal or external) + * x87 FPU, i.e. floating point operations will be executed by the + * hardware (and not emulated in software). + * + * Additionally, if this bit is not cleared, MMX/SSE instructions won't + * work, i.e., they will trigger an invalid opcode exception (#UD). + */ movl %cr0, %eax - andl $~(1<<2), %eax + andl $~(1 << 2), %eax movl %eax, %cr0 - movl %ebp, %eax + /* Restore BIST. */ + movl %ebp, %eax Modified: trunk/src/cpu/x86/mmx_disable.inc ============================================================================== --- trunk/src/cpu/x86/mmx_disable.inc Mon Sep 27 13:11:09 2010 (r5858) +++ trunk/src/cpu/x86/mmx_disable.inc Mon Sep 27 19:53:17 2010 (r5859) @@ -1,2 +1,24 @@ - /* Clear out an mmx state */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* + * Execute the EMMS (Empty MMX Technology State) instruction. + */ emms + Modified: trunk/src/cpu/x86/sse_disable.inc ============================================================================== --- trunk/src/cpu/x86/sse_disable.inc Mon Sep 27 13:11:09 2010 (r5858) +++ trunk/src/cpu/x86/sse_disable.inc Mon Sep 27 19:53:17 2010 (r5859) @@ -1,8 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* * Put the processor back into a reset state - * with respect to the xmm registers. + * with respect to the XMM registers. */ - xorps %xmm0, %xmm0 xorps %xmm1, %xmm1 xorps %xmm2, %xmm2 @@ -12,7 +30,15 @@ xorps %xmm6, %xmm6 xorps %xmm7, %xmm7 - /* Disable sse instructions */ + /* + * Disable SSE instructions. + * + * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the + * processor can no longer execute SSE instructions, and unmasked + * SIMD floating point exceptions will generate an invalid opcode + * exception (#UD). + */ movl %cr4, %eax - andl $~(3<<9), %eax + andl $~(3 << 9), %eax movl %eax, %cr4 + Modified: trunk/src/cpu/x86/sse_enable.inc ============================================================================== --- trunk/src/cpu/x86/sse_enable.inc Mon Sep 27 13:11:09 2010 (r5858) +++ trunk/src/cpu/x86/sse_enable.inc Mon Sep 27 19:53:17 2010 (r5859) @@ -1,14 +1,30 @@ - /* preserve BIST in %eax */ - movl %eax, %ebp +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ - /* - * Enable the use of the xmm registers - */ + /* Preserve BIST. */ + movl %eax, %ebp - /* Enable sse instructions */ + /* Enable SSE instructions. */ movl %cr4, %eax - orl $(1<<9), %eax + orl $(1 << 9), %eax movl %eax, %cr4 + /* Restore BIST. */ movl %ebp, %eax

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coreboot support for Tyan S2915-E
by John Peter Stevenson 27 Sep '10

27 Sep '10

I am interested in using coreboot on a Tyan S2915-E: http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=541&SKU=600000… Quick disclaimer: I don't actually have the system setup yet, so it is impossible to run, e.g., "lspci -tvnn", etc. With that aside, here are the details, as per the FAQ, and to the best of my ability to provide them: CPU: AMD Opteron, presumably would acquire most recent socket F variant Northbridge: integrated into CPU Southbridge: NVIDIA NFP3600 / NFP3050 SuperIO: SMSC SCH5307 BIOS: Phoenix BIOS on 8Mbit LPC Flash ROM Thank you, Pete Stevenson

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Trac reminder: list of new ticket(s)
by coreboot tracker 27 Sep '10

27 Sep '10

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[PATCH] Move CAR config from mainboard to CPU config for AMD LX boards.
by Warren Turkal 27 Sep '10

27 Sep '10

All these boards already had the CACHE_AS_RAM option in their individual configs. I just moved it the the CPU that they all use. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/model_lx/Kconfig | 14 ++++++++------ src/mainboard/amd/db800/Kconfig | 1 - src/mainboard/amd/norwich/Kconfig | 1 - src/mainboard/artecgroup/dbe61/Kconfig | 1 - src/mainboard/digitallogic/msm800sev/Kconfig | 1 - src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 1 - src/mainboard/lippert/hurricane-lx/Kconfig | 1 - src/mainboard/lippert/literunner-lx/Kconfig | 1 - src/mainboard/lippert/roadrunner-lx/Kconfig | 1 - src/mainboard/lippert/spacerunner-lx/Kconfig | 1 - src/mainboard/pcengines/alix1c/Kconfig | 1 - src/mainboard/pcengines/alix2d/Kconfig | 1 - src/mainboard/traverse/geos/Kconfig | 1 - src/mainboard/winent/pl6064/Kconfig | 1 - 14 files changed, 8 insertions(+), 19 deletions(-) diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig index 07bbce4..742ef69 100644 --- a/src/cpu/amd/model_lx/Kconfig +++ b/src/cpu/amd/model_lx/Kconfig @@ -1,25 +1,27 @@ config CPU_AMD_LX bool +if CPU_AMD_LX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + config DCACHE_RAM_BASE hex default 0xc8000 - depends on CPU_AMD_LX config DCACHE_RAM_SIZE hex default 0x8000 - depends on CPU_AMD_LX config GEODE_VSA bool default y - depends on CPU_AMD_LX select PCI_OPTION_ROM_RUN_REALMODE config GEODE_VSA_FILE bool "Add a VSA image" - depends on CPU_AMD_LX help Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM. @@ -29,9 +31,9 @@ config GEODE_VSA_FILE config VSA_FILENAME string "AMD Geode LX VSA path and filename" - depends on GEODE_VSA_FILE && CPU_AMD_LX + depends on GEODE_VSA_FILE default "gpl_vsa_lx_102.bin" help The path and filename of the file to use as VSA. - +endif # CPU_AMD_LX diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig index b973c9d..e1b94e9 100644 --- a/src/mainboard/amd/db800/Kconfig +++ b/src/mainboard/amd/db800/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index 6c65f4d..3dc214f 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig index 9dfb0ca..5266929 100644 --- a/src/mainboard/artecgroup/dbe61/Kconfig +++ b/src/mainboard/artecgroup/dbe61/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig index f98101b..a082b1f 100644 --- a/src/mainboard/digitallogic/msm800sev/Kconfig +++ b/src/mainboard/digitallogic/msm800sev/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index 7bef792..a6f5126 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select PIRQ_ROUTE - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index b30b8bb..027988f 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 4f4b289..482f571 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index ef6171f..44326d1 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Standard chip is a 512 KB FWH. Replacing it with a 1 MB # SST 49LF008A is possible. select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index 89a52ae..7526d1e 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM # Board is equipped with a 1 MB SPI flash, however, due to limitations # of the IT8712F Super I/O, only the top 512 KB are directly mapped. select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 395df75..b10095c 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index bd363f3..bb54d1c 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index c1d1af4..1c85149 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig index df6db01..1ec5692 100644 --- a/src/mainboard/winent/pl6064/Kconfig +++ b/src/mainboard/winent/pl6064/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC - select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR -- 1.7.1

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[PATCH] Move CAR config from mainboard to CPU config for AMD GX2 boards.
by Warren Turkal 27 Sep '10

27 Sep '10

Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/model_gx2/Kconfig | 13 ++++++++----- src/mainboard/wyse/s50/Kconfig | 1 - 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/model_gx2/Kconfig index 23c0ac7..4515a71 100644 --- a/src/cpu/amd/model_gx2/Kconfig +++ b/src/cpu/amd/model_gx2/Kconfig @@ -20,25 +20,27 @@ config CPU_AMD_GX2 bool +if CPU_AMD_GX2 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select CACHE_AS_RAM + config DCACHE_RAM_BASE hex default 0xc8000 - depends on CPU_AMD_GX2 config DCACHE_RAM_SIZE hex default 0x04000 - depends on CPU_AMD_GX2 config GEODE_VSA bool default y - depends on CPU_AMD_GX2 select PCI_OPTION_ROM_RUN_REALMODE config GEODE_VSA_FILE bool "Add a VSA image" - depends on CPU_AMD_GX2 help Select this option if you have an AMD Geode GX2 vsa that you would like to add to your ROM. @@ -48,9 +50,10 @@ config GEODE_VSA_FILE config VSA_FILENAME string "AMD Geode GX2 VSA path and filename" - depends on GEODE_VSA_FILE && CPU_AMD_GX2 + depends on GEODE_VSA_FILE default "gpl_vsa_gx_102.bin" help The path and filename of the file to use as VSA. +endif # CPU_AMD_GX2 diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig index 805748a..9c7e12c 100644 --- a/src/mainboard/wyse/s50/Kconfig +++ b/src/mainboard/wyse/s50/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC - select CACHE_AS_RAM select HAVE_PIRQ_TABLE select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 -- 1.7.1

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[commit] r5858 - trunk/src/cpu/intel/model_f2x
by repository service 27 Sep '10

27 Sep '10

Author: stepan Date: Mon Sep 27 13:11:09 2010 New Revision: 5858 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5858 Log: drop double include (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/model_f2x/model_f2x_init.c Modified: trunk/src/cpu/intel/model_f2x/model_f2x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f2x/model_f2x_init.c Sun Sep 26 18:01:08 2010 (r5857) +++ trunk/src/cpu/intel/model_f2x/model_f2x_init.c Mon Sep 27 13:11:09 2010 (r5858) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -30,7 +29,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_f2x_init(device_t cpu) { /* Turn on caching if we haven't already */

1 0

[PATCH] Fix abuild option parsing.
by Warren Turkal 27 Sep '10

27 Sep '10

The commandline parsing for abuild doing a couple of buggy things: * Long options of the form --opt=arg were not having the arg stripped off into a another argument in the output. As a result, all long options with args had to be written like "--opt arg" on the command line to be recognized. * The --remove option was shifting too many times. As a bonus, I also added some logic to make "make distclean" cleanup the default abuild build dir. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- Makefile | 7 +++++-- util/abuild/abuild | 6 +++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index a5cba2b..3754ab9 100644 --- a/Makefile +++ b/Makefile @@ -358,10 +358,13 @@ clean-for-update: doxygen-clean clean: clean-for-update rm -f $(obj)/coreboot* .ccwrap +clean-abuild: + rm -rf coreboot_builds + clean-cscope: rm -f cscope.out -distclean: clean-cscope +distclean: clean-cscope clean-abuild rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile @@ -390,5 +393,5 @@ $(objutil)/romcc/romcc: $(top)/util/romcc/romcc.c @# http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html $(HOSTCC) -g $(STACK) -Wall -o $@ $< -.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy coreboot .xcompile +.PHONY: $(PHONY) clean clean-abuild clean-cscope cscope distclean doxygen doxy coreboot .xcompile diff --git a/util/abuild/abuild b/util/abuild/abuild index f2f5665..5a17e5e 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -570,8 +570,8 @@ test "$ROOT" = "" && ROOT=$( cd ../..; pwd ) getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache Vvhat:bp:Tc:sxCl:rP:uy -- "$@"` - eval set "$args" + args=`getopt -l version,verbose,help,all,target:,broken,payloads:,test,cpus:,silent,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache -o Vvhat:bp:Tc:sxCl:rP:uy -- "$@"` + eval set -- $args else # Detected non-GNU getopt args=`getopt Vvhat:bp:Tc:sxCl:rP:uy $*` @@ -589,7 +589,7 @@ while true ; do -t|--target) shift; target="$1"; shift;; -a|--all) shift; buildall=true;; -b|--broken) shift; buildbroken=true;; - -r|--remove) shift; remove=true; shift;; + -r|--remove) shift; remove=true;; -v|--verbose) shift; verbose=true; silent='V=1';; -V|--version) shift; myversion; exit 0;; -h|--help) shift; myversion; myhelp; exit 0;; -- 1.7.1

1 0

[PATCH] RFC - move CAR config to socket config
by Warren Turkal 27 Sep '10

27 Sep '10

This patch moves one of the CAR configs to the socket from the single mainboard that uses it. Would this be a reasonable cleanup to perform across the tree? Thanks, wt Warren Turkal (1): Move CAR config from mainboard config to socket config. src/cpu/intel/socket_441/Kconfig | 16 ++++++++++++++++ src/mainboard/intel/d945gclf/Kconfig | 9 --------- 2 files changed, 16 insertions(+), 9 deletions(-)

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coreboot September 2010