coreboot September 2010

coreboot@coreboot.org

58 participants
324 discussions

[commit] r5831 - in trunk/src: mainboard/hp mainboard/hp/dl165_g6_fam10 superio/serverengines/pilot
by repository service 24 Sep '10

24 Sep '10

Author: oxygene Date: Fri Sep 24 19:35:32 2010 New Revision: 5831 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5831 Log: Add support for HP DL165-G6 with Fam10 CPU. Original patch was Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Updates to accomodate changes in coreboot are Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/mainboard/hp/dl165_g6_fam10/ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig trunk/src/mainboard/hp/dl165_g6_fam10/bootblock.c trunk/src/mainboard/hp/dl165_g6_fam10/chip.h trunk/src/mainboard/hp/dl165_g6_fam10/cmos.layout trunk/src/mainboard/hp/dl165_g6_fam10/devicetree.cb trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c trunk/src/mainboard/hp/dl165_g6_fam10/irq_tables.c trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h Modified: trunk/src/mainboard/hp/Kconfig trunk/src/superio/serverengines/pilot/pilot_early_init.c Modified: trunk/src/mainboard/hp/Kconfig ============================================================================== --- trunk/src/mainboard/hp/Kconfig Thu Sep 23 20:48:27 2010 (r5830) +++ trunk/src/mainboard/hp/Kconfig Fri Sep 24 19:35:32 2010 (r5831) @@ -7,6 +7,8 @@ bool "ProLiant DL145 G1" config BOARD_HP_DL145_G3 bool "ProLiant DL145 G3" +config BOARD_HP_DL165_G6_FAM10 + bool "ProLiant DL165 G6 Fam10" config BOARD_HP_E_VECTRA_P2706T bool "e-Vectra P2706T" @@ -14,6 +16,7 @@ source "src/mainboard/hp/dl145_g1/Kconfig" source "src/mainboard/hp/dl145_g3/Kconfig" +source "src/mainboard/hp/dl165_g6_fam10/Kconfig" source "src/mainboard/hp/e_vectra_p2706t/Kconfig" config MAINBOARD_VENDOR Added: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,104 @@ +if BOARD_HP_DL165_G6_FAM10 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_BROADCOM_BCM21000 + select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_NSC_PC87417 + select HAVE_OPTION_TABLE + select HAVE_BUS_CONFIG + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select CACHE_AS_RAM + select HAVE_HARD_RESET + select LIFT_BSP_APIC_ID + select BOARD_ROMSIZE_KB_1024 + select ENABLE_APIC_EXT_ID + select AMDMCT + select TINY_BOOTBLOCK + +config MAINBOARD_DIR + string + default hp/dl165_g6_fam10 + +config DCACHE_RAM_BASE + hex + default 0xc4000 + +config DCACHE_RAM_SIZE + hex + default 0x0c000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x04000 + +config APIC_ID_OFFSET + hex + default 0 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config MAINBOARD_PART_NUMBER + string + default "ProLiant DL165 G6 (Fam10)" + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config MAX_CPUS + int + default 12 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x6 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + +config IRQ_SLOT_COUNT + int + default 15 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + +config RAMBASE + hex + default 0x200000 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "mainboard/hp/dl165_g6_fam10/bootblock.c" + +config MMCONF_SUPPORT_DEFAULT + bool + default y + +endif # BOARD_HP_DL165_G6_FAM10 Added: trunk/src/mainboard/hp/dl165_g6_fam10/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/bootblock.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,48 @@ +#include <device/pnp_def.h> + +#define SCH4307_CONFIG_PORT 0x162e +static inline void shc4307_enter_ext_func_mode(device_t dev) +{ + unsigned port = dev >> 8; + outb(0x55, port); +} + +static inline void shc4307_exit_ext_func_mode(device_t dev) +{ + unsigned port = dev >> 8; + outb(0xaa, port); +} + +#define CMOS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x6) +#define KBD_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x7) +#define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) +#define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) + +void shc4307_init(void) +{ + shc4307_enter_ext_func_mode(CMOS_DEV); + pnp_set_logical_device(CMOS_DEV); /* CMOS/RTC */ + pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70); + pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72); + pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8); + /* pnp_set_enable(CMOS_DEV, 3); */ + pnp_write_config(CMOS_DEV, 0x30, 3); + + pnp_set_logical_device(KBD_DEV); /* Keyboard */ + pnp_set_irq(KBD_DEV, PNP_IDX_IRQ0, 1); + pnp_set_enable(KBD_DEV, 1); + + pnp_set_logical_device(DBG_DEV); /* Debug */ + pnp_set_iobase(DBG_DEV, PNP_IDX_IO0, 0x80); + pnp_set_enable(DBG_DEV, 1); + + pnp_set_logical_device(REGS_DEV); + pnp_set_iobase(REGS_DEV, PNP_IDX_IO0, 0x600); + pnp_set_enable(REGS_DEV, 1); + + shc4307_exit_ext_func_mode(CMOS_DEV); +} + +static void bootblock_southbridge_init(void) { + shc4307_init(); +} Added: trunk/src/mainboard/hp/dl165_g6_fam10/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/chip.h Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.de> for University of Mannheim. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; + Added: trunk/src/mainboard/hp/dl165_g6_fam10/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/cmos.layout Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/src/mainboard/hp/dl165_g6_fam10/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/devicetree.cb Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,90 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_F_1207 + device lapic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdfam10 # northbridge + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # devices on link 2 + chip southbridge/broadcom/bcm21000 # HT2100 + device pci 0.0 on + end # bridge to slot PCI-E 4x ?? + device pci 1.0 on + end + device pci 2.0 on + end # unused + device pci 3.0 on # bridge to slot PCI-E 16x ?? + end + device pci 4.0 on + end # unused + device pci 5.0 on + device pci 4.0 on end # BCM5715 NIC + device pci 4.1 on end # BCM5715 NIC + end + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PCI/PCI-X bridge 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on end # Legacy pci main 0x0205 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.3 off # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.4 off end # SWC + device pnp 4e.5 off end # Mouse + device pnp 4e.6 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.f off end # XBUS + device pnp 4e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end # end superio + end # end pci 1.2 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # VGA + end + end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # amdfam10 + + end #pci_domain +end + + Added: trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,145 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdfam10_sysconf.h> + +#include <stdlib.h> +#include "mb_sysconf.h" + +// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables +struct mb_sysconf_t mb_sysconf; + +/* Here you only need to set value in pci1234 for HT-IO that could be + installed or not You may need to preset pci1234 for HTIO board, please + refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */ +static u32 pci1234x[] = { + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, + 0x0000ffc, 0x0000ffc, +}; + + +/* HT Chain device num, actually it is unit id base of every ht device + in chain, assume every chain only have 4 ht device at most */ + +static unsigned hcdnx[] = { + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020, + 0x20202020, 0x20202020, +}; + +extern void get_pci1234(void); + +static unsigned get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + + unsigned apicid_base; + + device_t dev; + int i; + struct mb_sysconf_t *m; + + if(get_bus_conf_done==1) return; //do it only once + + get_bus_conf_done = 1; + + sysconf.mb = &mb_sysconf; + + m = sysconf.mb; + memset(m, 0, sizeof(struct mb_sysconf_t)); + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + + for(i=0;i<sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; + m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780 + + m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff; + m->bus_bcm5780[0] = m->bus_bcm5785_0; + + /* bcm5785 */ + printk(BIOS_DEBUG, "search for def %d.0 on bus %d\n",sysconf.sbdn,m->bus_bcm5785_0); + dev = dev_find_slot(m->bus_bcm5785_0, PCI_DEVFN(sysconf.sbdn,0)); + if (dev) { + printk(BIOS_DEBUG, "found dev %s...\n",dev_path(dev)); + m->bus_bcm5785_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + printk(BIOS_DEBUG, "secondary is %d...\n",m->bus_bcm5785_1); + dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0)); + printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev)); + if(dev) { + m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + printk(BIOS_DEBUG, "bus_isa 1=%d\n",m->bus_isa); +#endif + } + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5785_0, sysconf.sbdn); + } + + /* bcm5780 */ + for(i = 1; i < 6; i++) { + dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0)); + if(dev) { + m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE + m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + m->bus_isa++; + printk(BIOS_DEBUG, "bus_isa 2=%d\n",m->bus_isa); +#endif + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1); + } + } + +/*I/O APICs: APIC ID Version State Address*/ + apicid_base = 0x10; + for(i=0;i<3;i++) + m->apicid_bcm5785[i] = apicid_base+i; +} Added: trunk/src/mainboard/hp/dl165_g6_fam10/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/irq_tables.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,51 @@ +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * + * Contains the IRQ Routing Table dumped directly from your + * memory, which BIOS sets up. + * + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ + +#ifdef GETPIR +#include "pirq_routing.h" +#else +#include <arch/pirq_routing.h> +#endif + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 11, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x02 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1166, /* Vendor */ + 0x36, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xe9, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x01, (0x0e << 3) | 0x0, {{0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}}, 0x0, 0x0}, /* 1166:024a */ + {0x00, (0x03 << 3) | 0x0, {{0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}}, 0x0, 0x0}, /* 1166:0223 */ + {0x00, (0x06 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x0, 0x0}, /* 1166:0140 */ + {0x00, (0x07 << 3) | 0x0, {{0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}, {0x23, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ + {0x00, (0x08 << 3) | 0x0, {{0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}, {0x22, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ + {0x00, (0x09 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x0, 0x0}, /* 1166:0142 */ + {0x00, (0x0a << 3) | 0x0, {{0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}, {0x20, 0xdac0}}, 0x0, 0x0}, /* 1166:0144 */ + {0x02, (0x02 << 3) | 0x0, {{0x28, 0xdac0}, {0x27, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 14e4:1648 */ + {0x06, (0x00 << 3) | 0x0, {{0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}, {0x21, 0xdac0}}, 0x2, 0x0}, + {0x03, (0x00 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x2, 0x0}, + {0x07, (0x00 << 3) | 0x0, {{0x2a, 0xdac0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* 102b:0522 */ + } +}; + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mainboard.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,34 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.de> for Uni of Mannheim. + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("HP DL165 G6 Mainboard (Family 10)") +}; Added: trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.e> for Uni of Mannheim + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-hd.de> for Uni of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_isa; + unsigned char bus_bcm5780[7]; + unsigned char bus_bcm5785_0; + unsigned char bus_bcm5785_1; + unsigned char bus_bcm5785_1_1; + unsigned apicid_bcm5785[3]; + + unsigned sbdn2; + unsigned bus_type[256]; +}; + +#endif + Added: trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2001 Eric W.Biederman<ebiderman(a)lnxi.com> + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)gmail.com> for AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.e> for Uni of Mannheim + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-hd.de> for Uni of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/io.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdfam10_sysconf.h> + +#include "mb_sysconf.h" + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "COREBOOT"; + static const char productid[12] = "HP DL165 G6 "; + struct mp_config_table *mc; + int isa_bus; + + struct mb_sysconf_t *m; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + m = sysconf.mb; + + mptable_write_buses(mc, NULL, &isa_bus); + printk(BIOS_DEBUG, "writing %d as ISA to mptable (%d for real)...\n", isa_bus, m->bus_isa); + + /*I/O APICs: APIC ID Version State Address*/ + { + device_t dev = 0; + int i; + struct resource *res; + for(i=0; i<3; i++) { + dev = dev_find_device(0x1166, 0x0235, dev); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base); + smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); + } + } + } + + } + + /* IRQ routing as factory BIOS */ + outb(0x00, 0xc00); outb(0x09, 0xc01); + outb(0x01, 0xc00); outb(0x0a, 0xc01); + outb(0x02, 0xc00); outb(0x0e, 0xc01); + outb(0x03, 0xc00); outb(0x07, 0xc01); + outb(0x07, 0xc00); outb(0x05, 0xc01); + + // 8259 registers... + outb(0xa0, 0x4d0); + outb(0x0e, 0x4d1); + + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x64); + dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 + pci_write_config32(dev, 0x64, dword); + } + // set GEVENT pins to NO OP + /* outb(0x33, 0xcd6); outb(0x00, 0xcd7); + outb(0x34, 0xcd6); outb(0x00, 0xcd7); + outb(0x35, 0xcd6); outb(0x00, 0xcd7); */ + } + + // hide XIOAPIC PCI configuration space + { + device_t dev; + dev = dev_find_device(0x1166, 0x205, 0); + if (dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x64); + dword |= (1<<26); + pci_write_config32(dev, 0x64, dword); + } + } + + mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0); + + /* I/O Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0, m->apicid_bcm5785[0], 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0, m->apicid_bcm5785[0], 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0, m->apicid_bcm5785[2], 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1, m->apicid_bcm5785[2], 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0, m->apicid_bcm5785[2], 0xa); + + /* enable int */ + /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x6c); + dword |= (1<<4); // enable interrupts + printk(BIOS_DEBUG, "6ch: %x\n",dword); + pci_write_config32(dev, 0x6c, dword); + } + } + + /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + + //extended table entries + smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80); + smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f); + smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006); + smp_write_bus_hierarchy(mc, 8, 0x01, 0); + smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0); + smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1); + + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Tyan + * Copyright (C) 2006 AMD + * Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan and AMD. + * + * Copyright (C) 2007 University of Mannheim + * Written by Philipp Degler <pdegler(a)rumms.uni-mannheim.de> for University of Mannheim + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define RAMINIT_SYSINFO 1 + +#define FAM10_SCAN_PCI_BUS 0 +#define FAM10_ALLOCATE_IO_RANGE 1 + +#define QRANK_DIMM_SUPPORT 1 + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 + +#define DBGP_DEFAULT 7 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include <console/console.h> +#include "lib/ramtest.c" +#include <cpu/amd/model_10xxx_rev.h> +#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "northbridge/amd/amdfam10/raminit.h" +#include "northbridge/amd/amdfam10/amdfam10.h" + +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdfam10/reset_test.c" + +#include "superio/serverengines/pilot/pilot_early_serial.c" +#include "superio/serverengines/pilot/pilot_early_init.c" +#include "superio/nsc/pc87417/pc87417_early_serial.c" + +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdfam10/debug.c" + +#include "cpu/x86/mtrr/earlymtrr.c" + +//#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) +#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) + +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + u8 val; + outb(0x3d, 0x0cd6); + outb(0x87, 0x0cd7); + + outb(0x44, 0xcd6); + val = inb(0xcd7); + outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdfam10/amdfam10.h" + +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/amdfam10_pci.c" + +#include "cpu/amd/quadcore/quadcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" +#include "cpu/amd/model_10xxx/init_cpus.c" + +#include "northbridge/amd/amdfam10/early_ht.c" + +#include "spd_addr.h" + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + + u32 bsp_apicid = 0; + u32 val; + msr_t msr; + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + bcm5785_enable_rom(); + bcm5785_enable_lpc(); + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + + post_code(0x30); + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + uart_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + console_init(); + pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); + + update_microcode(val); + post_code(0x33); + + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ + + wait_all_core0_started(); + +#if CONFIG_LOGICAL_CPUS==1 + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); +#endif + +#if SET_FIDVID == 1 + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); +#endif + + init_timer(); + + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + /* It's the time to set ctrl in sysinfo now; */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + enable_smbus(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + + bcm5785_early_setup(); + + post_cache_as_ram(); +} Added: trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h Fri Sep 24 19:35:32 2010 (r5831) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * This file defines the SPD addresses for the mainboard. Must be included in + * romstage.c + */ + +#define RC00 0 +#define RC01 1 +#define RC02 2 +#define RC03 3 +#define RC04 4 +#define RC05 5 +#define RC06 6 +#define RC07 7 +#define RC08 8 +#define RC09 9 +#define RC10 10 +#define RC11 11 +#define RC12 12 +#define RC13 13 +#define RC14 14 +#define RC15 15 +#define RC16 16 +#define RC17 17 +#define RC18 18 +#define RC19 19 +#define RC20 20 +#define RC21 21 +#define RC22 22 +#define RC23 23 +#define RC24 24 +#define RC25 25 +#define RC26 26 +#define RC27 27 +#define RC28 28 +#define RC29 29 +#define RC30 30 +#define RC31 31 + +#define RC32 32 +#define RC33 33 +#define RC34 34 +#define RC35 35 +#define RC36 36 +#define RC37 37 +#define RC38 38 +#define RC39 39 +#define RC40 40 +#define RC41 41 +#define RC42 42 +#define RC43 43 +#define RC44 44 +#define RC45 45 +#define RC46 46 +#define RC47 47 +#define RC48 48 +#define RC49 49 +#define RC50 50 +#define RC51 51 +#define RC52 52 +#define RC53 53 +#define RC54 54 +#define RC55 55 +#define RC56 56 +#define RC57 57 +#define RC58 58 +#define RC59 59 +#define RC60 60 +#define RC61 61 +#define RC62 62 +#define RC63 63 + + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + + +static const u8 spd_addr[] = { + // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +}; + Modified: trunk/src/superio/serverengines/pilot/pilot_early_init.c ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot_early_init.c Thu Sep 23 20:48:27 2010 (r5830) +++ trunk/src/superio/serverengines/pilot/pilot_early_init.c Fri Sep 24 19:35:32 2010 (r5831) @@ -37,6 +37,16 @@ pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\n"); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0x0b00); + pnp_set_iobase(dev, 0x62, 0x0b80); + pnp_set_iobase(dev, 0x64, 0x0b84); + pnp_set_iobase(dev, 0x66, 0x0b86); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); @@ -58,14 +68,27 @@ pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); -/* + pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x6)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, PNP_IDX_IRQ0, 1); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port, 0x6), 0); + pnp_set_logical_device(PNP_DEV(port, 0xe)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); + pnp_set_irq(dev, PNP_IDX_IRQ0, 8); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); -*/ + pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev);

1 0

[commit] r5830 - in trunk: . documentation src src/arch/i386 src/cpu/amd/model_gx2 src/cpu/amd/model_lx src/cpu/x86/32bit src/include/boot src/pc80
by repository service 23 Sep '10

23 Sep '10

Author: uwe Date: Thu Sep 23 20:48:27 2010 New Revision: 5830 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5830 Log: Whitespace/typo/cosmetic fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/README trunk/documentation/POSTCODES trunk/src/Kconfig.deprecated_options trunk/src/arch/i386/Kconfig trunk/src/cpu/amd/model_gx2/cache_as_ram.inc trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/cpu/x86/32bit/entry32.inc trunk/src/include/boot/coreboot_tables.h trunk/src/pc80/usbdebug_serial.c Modified: trunk/README ============================================================================== --- trunk/README Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/README Thu Sep 23 20:48:27 2010 (r5830) @@ -51,7 +51,7 @@ Testing coreboot Without Modifying Your Hardware -------------------------------------------------- +------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run Modified: trunk/documentation/POSTCODES ============================================================================== --- trunk/documentation/POSTCODES Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/documentation/POSTCODES Thu Sep 23 20:48:27 2010 (r5830) @@ -2,13 +2,13 @@ coreboot POST Codes ------------------------------------------------------------------------------- -This is an (incomplete) list of POST codes emitted by coreboot v2. +This is an (incomplete) list of POST codes emitted by coreboot v4. 0x10 Entry into protected mode 0x01 Entry into 'crt0.s' reset code jumps to here -0x11 Start copying LinuxBIOS to RAM with decompression if compressed +0x11 Start copying coreboot to RAM with decompression if compressed 0x12 Copy/decompression finished jumping to RAM -0x80 Entry into LinuxBIOS in RAM +0x80 Entry into coreboot in RAM 0x13 Entry into c_start 0xfe Pre call to hardwaremain() 0x39 Console is initialized Modified: trunk/src/Kconfig.deprecated_options ============================================================================== --- trunk/src/Kconfig.deprecated_options Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/Kconfig.deprecated_options Thu Sep 23 20:48:27 2010 (r5830) @@ -4,45 +4,48 @@ # It might be possible to consolidate hard_reset() to southbridges, # given that it (usually) uses its registers. -# The long term goal would be to eliminate hard_reset from boards. +# The long term goal would be to eliminate hard_reset() from boards. config BOARD_HAS_HARD_RESET - bool - default n - help - This variable specifies whether a given board has a reset.c - file containing a hard_reset() function. + bool + default n + help + This variable specifies whether a given board has a reset.c + file containing a hard_reset() function. # It might be possible to consolidate FADTs to southbridges. This would # improve code reuse in the tree. config BOARD_HAS_FADT - bool - default n - help - This variable specifies whether a given board has a board-local - FADT in fadt.c. Long-term, those should be moved to appropriate - chipset components (eg. southbridge) + bool + default n + help + This variable specifies whether a given board has a board-local + FADT in fadt.c. Long-term, those should be moved to appropriate + chipset components (eg. southbridge). # There ought to be a better place to put data than code. Also, make this # (or a similar) framework more universally usable, so all boards benefit # from sharing data between the various tables. config HAVE_BUS_CONFIG - bool - default n + bool + default n help This variable specifies whether a given board has a get_bus_conf.c file containing information about bus routing. -# Will be removed (alongside with the PS2 init code) once payloads -# reliably support PS2 init themselves. +# Will be removed (alongside with the PS/2 init code) once payloads +# reliably support PS/2 init themselves. config DRIVERS_PS2_KEYBOARD - bool "PS2 Keyboard init" + bool "PS/2 keyboard init" default y help - Enable this option to initialize PS2 keyboards found connected - to the PS2 port. Some payloads (eg, filo) require this - option. Other payloads (eg, SeaBIOS, Linux) do not require - it. Initializing a PS2 keyboard can take several hundred - milliseconds. + Enable this option to initialize PS/2 keyboards found connected + to the PS/2 port. + + Some payloads (eg, filo) require this option. Other payloads + (eg, SeaBIOS, Linux) do not require it. + Initializing a PS/2 keyboard can take several hundred milliseconds. + If you know you will only use a payload which does not require - this option, then you can say "n" here to speed up boot time. - Otherwise say "y". + this option, then you can say N here to speed up boot time. + Otherwise say Y. + Modified: trunk/src/arch/i386/Kconfig ============================================================================== --- trunk/src/arch/i386/Kconfig Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/arch/i386/Kconfig Thu Sep 23 20:48:27 2010 (r5830) @@ -76,10 +76,10 @@ default n depends on TINY_BOOTBLOCK help - If this option is activate, no new coreboot.rom file - is created. Instead it is expected that there already - is a suitable file for further processing. - The bootblock will not be modified. + If this option is enabled, no new coreboot.rom file + is created. Instead it is expected that there already + is a suitable file for further processing. + The bootblock will not be modified. config ROMCC bool Modified: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Thu Sep 23 20:48:27 2010 (r5830) @@ -184,7 +184,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) /* post 11 */ + post_code(0x11) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +201,7 @@ call copy_and_run .Lhlt: - post_code(0xee) /* post fail ee */ + post_code(0xee) hlt jmp .Lhlt Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Thu Sep 23 20:48:27 2010 (r5830) @@ -210,7 +210,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) /* post 11 */ + post_code(0x11) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +227,7 @@ call copy_and_run .Lhlt: - post_code(0xee) /* post fail ee */ + post_code(0xee) hlt jmp .Lhlt Modified: trunk/src/cpu/x86/32bit/entry32.inc ============================================================================== --- trunk/src/cpu/x86/32bit/entry32.inc Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/cpu/x86/32bit/entry32.inc Thu Sep 23 20:48:27 2010 (r5830) @@ -51,7 +51,7 @@ /* Save the BIST value */ movl %eax, %ebp - post_code(0x10) /* post 10 */ + post_code(0x10) movw $ROM_DATA_SEG, %ax movw %ax, %ds Modified: trunk/src/include/boot/coreboot_tables.h ============================================================================== --- trunk/src/include/boot/coreboot_tables.h Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/include/boot/coreboot_tables.h Thu Sep 23 20:48:27 2010 (r5830) @@ -74,10 +74,10 @@ uint32_t table_entries; }; -/* Every entry in the boot enviroment list will correspond to a boot +/* Every entry in the boot environment list will correspond to a boot * info record. Encoding both type and size. The type is obviously * so you can tell what it is. The size allows you to skip that - * boot enviroment record if you don't know what it easy. This allows + * boot environment record if you don't know what it easy. This allows * forward compatibility with records not yet defined. */ struct lb_record { @@ -85,9 +85,9 @@ uint32_t size; /* size of record (in bytes) */ }; -#define LB_TAG_UNUSED 0x0000 +#define LB_TAG_UNUSED 0x0000 -#define LB_TAG_MEMORY 0x0001 +#define LB_TAG_MEMORY 0x0001 struct lb_memory_range { struct lb_uint64 start; @@ -108,7 +108,7 @@ struct lb_memory_range map[0]; }; -#define LB_TAG_HWRPB 0x0002 +#define LB_TAG_HWRPB 0x0002 struct lb_hwrpb { uint32_t tag; uint32_t size; Modified: trunk/src/pc80/usbdebug_serial.c ============================================================================== --- trunk/src/pc80/usbdebug_serial.c Thu Sep 23 20:29:40 2010 (r5829) +++ trunk/src/pc80/usbdebug_serial.c Thu Sep 23 20:48:27 2010 (r5830) @@ -1,6 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License.

1 0

[commit] r5829 - in trunk/src: boot console include/device lib mainboard/via/epia-n/acpi
by repository service 23 Sep '10

23 Sep '10

Author: stepan Date: Thu Sep 23 20:29:40 2010 New Revision: 5829 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5829 Log: Fix some wrong capitalizations, reformat comments, fix a typo. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/boot/selfboot.c trunk/src/console/Kconfig trunk/src/include/device/resource.h trunk/src/lib/lzma.c trunk/src/mainboard/via/epia-n/acpi/irq_links.asl trunk/src/mainboard/via/epia-n/acpi/pata_methods.asl Modified: trunk/src/boot/selfboot.c ============================================================================== --- trunk/src/boot/selfboot.c Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/boot/selfboot.c Thu Sep 23 20:29:40 2010 (r5829) @@ -175,7 +175,7 @@ break; } if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) { - printk(BIOS_ERR, "Payload is overwriting Coreboot tables.\n"); + printk(BIOS_ERR, "Payload is overwriting coreboot tables.\n"); break; } } Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/console/Kconfig Thu Sep 23 20:29:40 2010 (r5829) @@ -156,10 +156,10 @@ config CONSOLE_NE2K_SRC_IP depends on CONSOLE_NE2K - string "IP adress of Coreboot system" + string "IP address of coreboot system" default "10.0.1.253" help - This is the IP of the Coreboot system + This is the IP of the coreboot system config CONSOLE_NE2K_IO_PORT depends on CONSOLE_NE2K Modified: trunk/src/include/device/resource.h ============================================================================== --- trunk/src/include/device/resource.h Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/include/device/resource.h Thu Sep 23 20:29:40 2010 (r5829) @@ -20,7 +20,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ -#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the Coreboot table */ +#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ #define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */ Modified: trunk/src/lib/lzma.c ============================================================================== --- trunk/src/lib/lzma.c Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/lib/lzma.c Thu Sep 23 20:29:40 2010 (r5829) @@ -1,14 +1,13 @@ /* - -Coreboot interface to memory-saving variant of LZMA decoder - -(C)opyright 2006 Carl-Daniel Hailfinger -Released under the GNU GPL v2 or later - -Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA -SDK 4.42, which is written and distributed to public domain by Igor Pavlov. - -*/ + * coreboot interface to memory-saving variant of LZMA decoder + * + * Copyright (C) 2006 Carl-Daniel Hailfinger + * Released under the GNU GPL v2 or later + * + * Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA + * SDK 4.42, which is written and distributed to public domain by Igor Pavlov. + * + */ #include "lzmadecode.c" #include <console/console.h> Modified: trunk/src/mainboard/via/epia-n/acpi/irq_links.asl ============================================================================== --- trunk/src/mainboard/via/epia-n/acpi/irq_links.asl Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/mainboard/via/epia-n/acpi/irq_links.asl Thu Sep 23 20:29:40 2010 (r5829) @@ -16,7 +16,7 @@ /* Status - always return ready */ Method (_STA, 0, NotSerialized) { - /* See If Coreboot has allocated INTA# */ + /* See if coreboot has allocated INTA# */ And (PIRA, 0xF0, Local0) If (LEqual (Local0, 0x00)) { @@ -94,7 +94,7 @@ Name (_UID, 0x02) Method (_STA, 0, NotSerialized) { - /* See If Coreboot has allocated INTB# */ + /* See if coreboot has allocated INTB# */ And (PIBC, 0x0F, Local0) If (LEqual (Local0, 0x00)) { @@ -172,7 +172,7 @@ Name (_UID, 0x03) Method (_STA, 0, NotSerialized) { - /* See If Coreboot has allocated INTC# */ + /* See if coreboot has allocated INTC# */ And (PIBC, 0xF0, Local0) If (LEqual (Local0, 0x00)) { @@ -251,7 +251,7 @@ Name (_UID, 0x04) Method (_STA, 0, NotSerialized) { - /* See If Coreboot has allocated INTD# */ + /* See if coreboot has allocated INTD# */ And (PIRD, 0xF0, Local0) If (LEqual (Local0, 0x00)) { Modified: trunk/src/mainboard/via/epia-n/acpi/pata_methods.asl ============================================================================== --- trunk/src/mainboard/via/epia-n/acpi/pata_methods.asl Thu Sep 23 20:16:46 2010 (r5828) +++ trunk/src/mainboard/via/epia-n/acpi/pata_methods.asl Thu Sep 23 20:29:40 2010 (r5829) @@ -47,13 +47,14 @@ }) -/* This method sets up the PATA Timing Control*/ -/* Note that a lot of this is done in the */ -/* Coreboot VT8237R Init code, but this is */ -/* already getting very cluttered with board */ -/* specific code. Using ACPI will allow this */ -/* to be de-cluttered a bit (so long as we're */ -/* running a ACPI Capable OS !!!) */ +/* This method sets up the PATA Timing Control. + * Note that a lot of this is done in the + * coreboot VT8237R init code, but this is + * already getting very cluttered with board + * specific code. Using ACPI will allow this + * to be de-cluttered a bit (so long as we're + * running a ACPI capable OS!) + */ Method (PMEX, 0, Serialized) {

1 0

[commit] r5828 - in trunk/src: console include lib
by repository service 23 Sep '10

23 Sep '10

Author: uwe Date: Thu Sep 23 20:16:46 2010 New Revision: 5828 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5828 Log: USB Debug Port related license header fixes (trivial). - Add missing license headers, or missing (C) lines to various files. (most are from AMD / Yinghai Lu, based on svn logs) - src/include/ehci.h was taken from the Linux kernel. Updating it to the latest version from git HEAD while I'm at it (build-tested with one board). It also sports some new EHCI 1.1 addendum #defines which we may or may not need. This new file also already has a proper GPL header. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/console/usbdebug_console.c trunk/src/include/ehci.h trunk/src/include/usb_ch9.h trunk/src/include/usbdebug.h trunk/src/lib/usbdebug.c Modified: trunk/src/console/usbdebug_console.c ============================================================================== --- trunk/src/console/usbdebug_console.c Thu Sep 23 17:38:55 2010 (r5827) +++ trunk/src/console/usbdebug_console.c Thu Sep 23 20:16:46 2010 (r5828) @@ -1,6 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. Modified: trunk/src/include/ehci.h ============================================================================== --- trunk/src/include/ehci.h Thu Sep 23 17:38:55 2010 (r5827) +++ trunk/src/include/ehci.h Thu Sep 23 20:16:46 2010 (r5828) @@ -1,132 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * It was taken from the Linux kernel (include/linux/usb/ehci_def.h). + * + * Copyright (C) 2001-2002 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + #ifndef EHCI_H #define EHCI_H +/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ + +/* Section 2.2 Host Controller Capability Registers */ struct ehci_caps { - /* these fields are specified as 8 and 16 bit registers, - * but some hosts can't perform 8 or 16 bit PCI accesses. - */ - u32 hc_capbase; -#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ -#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ - u32 hcs_params; /* HCSPARAMS - offset 0x4 */ -#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ -#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ -#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ -#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ -#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ -#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ -#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ + /* these fields are specified as 8 and 16 bit registers, + * but some hosts can't perform 8 or 16 bit PCI accesses. + */ + u32 hc_capbase; +#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ +#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ + u32 hcs_params; /* HCSPARAMS - offset 0x4 */ +#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ +#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ +#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ +#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ +#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ +#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ +#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ + + u32 hcc_params; /* HCCPARAMS - offset 0x8 */ +/* EHCI 1.1 addendum */ +#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) +#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) +#define HCC_LPM(p) ((p)&(1 << 17)) +#define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) - u32 hcc_params; /* HCCPARAMS - offset 0x8 */ -#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ +#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ -#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ +#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ - u8 portroute [8]; /* nibbles for routing - offset 0xC */ + u8 portroute[8]; /* nibbles for routing - offset 0xC */ } __attribute__ ((packed)); + /* Section 2.3 Host Controller Operational Registers */ struct ehci_regs { - /* USBCMD: offset 0x00 */ - u32 command; + /* USBCMD: offset 0x00 */ + u32 command; + +/* EHCI 1.1 addendum */ +#define CMD_HIRD (0xf<<24) /* host initiated resume duration */ +#define CMD_PPCEE (1<<15) /* per port change event enable */ +#define CMD_FSP (1<<14) /* fully synchronized prefetch */ +#define CMD_ASPE (1<<13) /* async schedule prefetch enable */ +#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */ /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ -#define CMD_PARK (1<<11) /* enable "park" on async qh */ -#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ -#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ -#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ -#define CMD_ASE (1<<5) /* async schedule enable */ -#define CMD_PSE (1<<4) /* periodic schedule enable */ +#define CMD_PARK (1<<11) /* enable "park" on async qh */ +#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ +#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ +#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ +#define CMD_ASE (1<<5) /* async schedule enable */ +#define CMD_PSE (1<<4) /* periodic schedule enable */ /* 3:2 is periodic frame list size */ -#define CMD_RESET (1<<1) /* reset HC not bus */ -#define CMD_RUN (1<<0) /* start/stop HC */ +#define CMD_RESET (1<<1) /* reset HC not bus */ +#define CMD_RUN (1<<0) /* start/stop HC */ - /* USBSTS: offset 0x04 */ - u32 status; -#define STS_ASS (1<<15) /* Async Schedule Status */ -#define STS_PSS (1<<14) /* Periodic Schedule Status */ -#define STS_RECL (1<<13) /* Reclamation */ -#define STS_HALT (1<<12) /* Not running (any reason) */ + /* USBSTS: offset 0x04 */ + u32 status; +#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */ +#define STS_ASS (1<<15) /* Async Schedule Status */ +#define STS_PSS (1<<14) /* Periodic Schedule Status */ +#define STS_RECL (1<<13) /* Reclamation */ +#define STS_HALT (1<<12) /* Not running (any reason) */ /* some bits reserved */ - /* these STS_* flags are also intr_enable bits (USBINTR) */ -#define STS_IAA (1<<5) /* Interrupted on async advance */ -#define STS_FATAL (1<<4) /* such as some PCI access errors */ -#define STS_FLR (1<<3) /* frame list rolled over */ -#define STS_PCD (1<<2) /* port change detect */ -#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ -#define STS_INT (1<<0) /* "normal" completion (short, ...) */ - - /* USBINTR: offset 0x08 */ - u32 intr_enable; - - /* FRINDEX: offset 0x0C */ - u32 frame_index; /* current microframe number */ - /* CTRLDSSEGMENT: offset 0x10 */ - u32 segment; /* address bits 63:32 if needed */ - /* PERIODICLISTBASE: offset 0x14 */ - u32 frame_list; /* points to periodic list */ - /* ASYNCLISTADDR: offset 0x18 */ - u32 async_next; /* address of next async queue head */ - - u32 reserved [9]; - - /* CONFIGFLAG: offset 0x40 */ - u32 configured_flag; -#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + /* these STS_* flags are also intr_enable bits (USBINTR) */ +#define STS_IAA (1<<5) /* Interrupted on async advance */ +#define STS_FATAL (1<<4) /* such as some PCI access errors */ +#define STS_FLR (1<<3) /* frame list rolled over */ +#define STS_PCD (1<<2) /* port change detect */ +#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ +#define STS_INT (1<<0) /* "normal" completion (short, ...) */ + + /* USBINTR: offset 0x08 */ + u32 intr_enable; + + /* FRINDEX: offset 0x0C */ + u32 frame_index; /* current microframe number */ + /* CTRLDSSEGMENT: offset 0x10 */ + u32 segment; /* address bits 63:32 if needed */ + /* PERIODICLISTBASE: offset 0x14 */ + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ + + u32 reserved[9]; + + /* CONFIGFLAG: offset 0x40 */ + u32 configured_flag; +#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + + /* PORTSC: offset 0x44 */ + u32 port_status[0]; /* up to N_PORTS */ +/* EHCI 1.1 addendum */ +#define PORTSC_SUSPEND_STS_ACK 0 +#define PORTSC_SUSPEND_STS_NYET 1 +#define PORTSC_SUSPEND_STS_STALL 2 +#define PORTSC_SUSPEND_STS_ERR 3 - /* PORTSC: offset 0x44 */ - u32 port_status [0]; /* up to N_PORTS */ +#define PORT_DEV_ADDR (0x7f<<25) /* device address */ +#define PORT_SSTS (0x3<<23) /* suspend status */ /* 31:23 reserved */ -#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ -#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ -#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ +#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ +#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ +#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ /* 19:16 for port testing */ -#define PORT_LED_OFF (0<<14) -#define PORT_LED_AMBER (1<<14) -#define PORT_LED_GREEN (2<<14) -#define PORT_LED_MASK (3<<14) -#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ -#define PORT_POWER (1<<12) /* true: has power (see PPC) */ -#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ +#define PORT_TEST_PKT (0x4<<16) /* Port Test Control - packet test */ +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ +#define PORT_POWER (1<<12) /* true: has power (see PPC) */ +#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ /* 9 reserved */ -#define PORT_RESET (1<<8) /* reset port */ -#define PORT_SUSPEND (1<<7) /* suspend port */ -#define PORT_RESUME (1<<6) /* resume it */ -#define PORT_OCC (1<<5) /* over current change */ -#define PORT_OC (1<<4) /* over current active */ -#define PORT_PEC (1<<3) /* port enable change */ -#define PORT_PE (1<<2) /* port enable */ -#define PORT_CSC (1<<1) /* connect status change */ -#define PORT_CONNECT (1<<0) /* device connected */ +#define PORT_LPM (1<<9) /* LPM transaction */ +#define PORT_RESET (1<<8) /* reset port */ +#define PORT_SUSPEND (1<<7) /* suspend port */ +#define PORT_RESUME (1<<6) /* resume it */ +#define PORT_OCC (1<<5) /* over current change */ +#define PORT_OC (1<<4) /* over current active */ +#define PORT_PEC (1<<3) /* port enable change */ +#define PORT_PE (1<<2) /* port enable */ +#define PORT_CSC (1<<1) /* connect status change */ +#define PORT_CONNECT (1<<0) /* device connected */ #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) } __attribute__ ((packed)); +#define USBMODE 0x68 /* USB Device mode */ +#define USBMODE_SDIS (1<<3) /* Stream disable */ +#define USBMODE_BE (1<<2) /* BE/LE endianness select */ +#define USBMODE_CM_HC (3<<0) /* host controller mode */ +#define USBMODE_CM_IDLE (0<<0) /* idle state */ + +/* Moorestown has some non-standard registers, partially due to the fact that + * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to + * PORTSCx + */ +#define HOSTPC0 0x84 /* HOSTPC extension */ +#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ +#define HOSTPC_PSPD (3<<25) /* Port speed detection */ +#define USBMODE_EX 0xc8 /* USB Device mode extension */ +#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ +#define USBMODE_EX_HC (3<<0) /* host controller mode */ +#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */ +#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ + /* Appendix C, Debug port ... intended for use with special "debug devices" * that can help if there's no serial console. (nonstandard enumeration.) */ struct ehci_dbg_port { - u32 control; -#define DBGP_OWNER (1<<30) -#define DBGP_ENABLED (1<<28) -#define DBGP_DONE (1<<16) -#define DBGP_INUSE (1<<10) -#define DBGP_ERRCODE(x) (((x)>>7)&0x07) -# define DBGP_ERR_BAD 1 -# define DBGP_ERR_SIGNAL 2 -#define DBGP_ERROR (1<<6) -#define DBGP_GO (1<<5) -#define DBGP_OUT (1<<4) -#define DBGP_LEN(x) (((x)>>0)&0x0f) - u32 pids; -#define DBGP_PID_GET(x) (((x)>>16)&0xff) -#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) - u32 data03; - u32 data47; - u32 address; -#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) + u32 control; +#define DBGP_OWNER (1<<30) +#define DBGP_ENABLED (1<<28) +#define DBGP_DONE (1<<16) +#define DBGP_INUSE (1<<10) +#define DBGP_ERRCODE(x) (((x)>>7)&0x07) +# define DBGP_ERR_BAD 1 +# define DBGP_ERR_SIGNAL 2 +#define DBGP_ERROR (1<<6) +#define DBGP_GO (1<<5) +#define DBGP_OUT (1<<4) +#define DBGP_LEN(x) (((x)>>0)&0x0f) + u32 pids; +#define DBGP_PID_GET(x) (((x)>>16)&0xff) +#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) + u32 data03; + u32 data47; + u32 address; +#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) } __attribute__ ((packed)); #endif Modified: trunk/src/include/usb_ch9.h ============================================================================== --- trunk/src/include/usb_ch9.h Thu Sep 23 17:38:55 2010 (r5827) +++ trunk/src/include/usb_ch9.h Thu Sep 23 20:16:46 2010 (r5828) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + #ifndef USB_CH9_H #define USB_CH9_H Modified: trunk/src/include/usbdebug.h ============================================================================== --- trunk/src/include/usbdebug.h Thu Sep 23 17:38:55 2010 (r5827) +++ trunk/src/include/usbdebug.h Thu Sep 23 20:16:46 2010 (r5828) @@ -1,6 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. Modified: trunk/src/lib/usbdebug.c ============================================================================== --- trunk/src/lib/usbdebug.c Thu Sep 23 17:38:55 2010 (r5827) +++ trunk/src/lib/usbdebug.c Thu Sep 23 20:16:46 2010 (r5828) @@ -16,9 +16,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ -/* - * 2006.12.10 yhlu moved it to corbeoot and use struct instead - */ + #if !defined(__ROMCC__) #include <console/console.h> #else

1 0

[PATCH] Updated HP DL165 G6 (Fam10) support
by Patrick Georgi 23 Sep '10

23 Sep '10

Hi, attached you'll find an updated patch to support HP DL165 G6 with Fam10 CPU. It's derived from Arne Gleditsch's code which you can find on http://patchwork.coreboot.org/patch/1387/ Given that its supporting patch is integrated now, I tried to bring it up to date with the various changes we did to the tree (as listed on http://www.coreboot.org/Flag_Days) I can't test it due to lack of such a board, but well, here it is, build-tested only. Originally Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Changes are Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Regards, Patrick

2 1

[patch] generate debug symbols
by Marc Jones 23 Sep '10

23 Sep '10

This patch is for source level debugging with the Sage SmartProbe. ( a little self plug there :) ) Generate and extract debug sysmbols for coreboot. *.debug files can be used for source level debug. Signed-off-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

2 2

[commit] r5827 - in trunk: . src/arch/i386
by repository service 23 Sep '10

23 Sep '10

Author: mjones Date: Thu Sep 23 17:38:55 2010 New Revision: 5827 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5827 Log: Generate and extract debug sysmbols for coreboot. *.debug files can be used for source level debug. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/Makefile trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.bootblock.inc trunk/src/arch/i386/Makefile.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Sep 23 01:42:32 2010 (r5826) +++ trunk/Makefile Thu Sep 23 17:38:55 2010 (r5827) @@ -287,7 +287,7 @@ # abspath is a workaround for romcc INCLUDES += -include $(abspath $(obj)/config.h) -CFLAGS = $(INCLUDES) -Os -nostdinc -pipe +CFLAGS = $(INCLUDES) -Os -nostdinc -pipe -g CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Sep 23 01:42:32 2010 (r5826) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Sep 23 17:38:55 2010 (r5827) @@ -32,4 +32,7 @@ @printf " LINK $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs) $(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map + $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ Modified: trunk/src/arch/i386/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bootblock.inc Thu Sep 23 01:42:32 2010 (r5826) +++ trunk/src/arch/i386/Makefile.bootblock.inc Thu Sep 23 17:38:55 2010 (r5827) @@ -75,6 +75,9 @@ @printf " LINK $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map + $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ ####################################################################### # Build the romstage @@ -89,6 +92,9 @@ printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(initobjs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map + $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug + $(OBJCOPY) --strip-debug $(obj)/romstage.elf + $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ $(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Thu Sep 23 01:42:32 2010 (r5826) +++ trunk/src/arch/i386/Makefile.inc Thu Sep 23 17:38:55 2010 (r5827) @@ -107,6 +107,9 @@ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map + $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ram.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ram.debug $@ $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $$(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" @@ -125,6 +128,9 @@ $(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/init/ldscript_apc.lb $^ + $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ap.debug + $(OBJCOPY) --strip-debug $@ + $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ap.debug $@ $(NM) -n $(obj)/coreboot_ap | sort > $(obj)/coreboot_ap.map

1 0

[commit] r5826 - trunk/src/lib
by repository service 23 Sep '10

23 Sep '10

Author: uwe Date: Thu Sep 23 01:42:32 2010 New Revision: 5826 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5826 Log: Fix a compiler warning in src/lib/usbdebug.c (trivial). The 'delay' variable shadows the global 'delay()' function, yielding this compiler warning/error: src/pc80/../lib/usbdebug.c: In function `ehci_reset_port': src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration src/lib/delay.c:9: error: shadowed declaration is here This fixes the issue by renaming the 'delay' variable to 'delay_ms'. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/lib/usbdebug.c Modified: trunk/src/lib/usbdebug.c ============================================================================== --- trunk/src/lib/usbdebug.c Thu Sep 23 00:46:47 2010 (r5825) +++ trunk/src/lib/usbdebug.c Thu Sep 23 01:42:32 2010 (r5826) @@ -278,7 +278,7 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) { unsigned portsc; - unsigned delay_time, delay; + unsigned delay_time, delay_ms; int loop; /* Reset the usb debug port */ @@ -287,10 +287,10 @@ portsc |= PORT_RESET; write32((unsigned long)&ehci_regs->port_status[port - 1], portsc); - delay = HUB_ROOT_RESET_TIME; + delay_ms = HUB_ROOT_RESET_TIME; for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT; - delay_time += delay) { - dbgp_mdelay(delay); + delay_time += delay_ms) { + dbgp_mdelay(delay_ms); portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); if (portsc & PORT_RESET) { @@ -299,9 +299,9 @@ write32((unsigned long)&ehci_regs->port_status[port - 1], portsc & ~(PORT_RWC_BITS | PORT_RESET)); do { - dbgp_mdelay(delay); + dbgp_mdelay(delay_ms); portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]); - delay_time += delay; + delay_time += delay_ms; } while ((portsc & PORT_RESET) && (--loop > 0)); if (!loop) { printk(BIOS_DEBUG, "ehci_reset_port forced done");

1 0

[commit] r5825 - in trunk/src: mainboard/asrock/939a785gmh southbridge/amd/sb700
by repository service 23 Sep '10

23 Sep '10

Author: ruik Date: Thu Sep 23 00:46:47 2010 New Revision: 5825 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5825 Log: Here is a proposed way how to handle the SATA PHY settings on SB700. It consits of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/939a785gmh/mainboard.c trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb700/sb700_sata.c Modified: trunk/src/mainboard/asrock/939a785gmh/mainboard.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mainboard.c Wed Sep 22 01:53:47 2010 (r5824) +++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c Thu Sep 23 00:46:47 2010 (r5825) @@ -147,3 +147,25 @@ CHIP_NAME("Asrock 939A785GMH/128M Mainboard") .enable_dev = mb_enable, }; + +/* override the default SATA PHY setup */ +void sb700_setup_sata_phys(struct device *dev) { + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01B48016); + pci_write_config32(dev, 0x8c, 0x01B48016); + pci_write_config32(dev, 0x90, 0x01B48016); + pci_write_config32(dev, 0x94, 0x01B48016); + pci_write_config32(dev, 0x98, 0x01B48016); + pci_write_config32(dev, 0x9C, 0x01B48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xA0, 0xA07A); + pci_write_config16(dev, 0xA2, 0xA07A); + pci_write_config16(dev, 0xA4, 0xA07A); + pci_write_config16(dev, 0xA6, 0xA07A); + pci_write_config16(dev, 0xA8, 0xA07A); + pci_write_config16(dev, 0xAA, 0xA0FF); +} Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Wed Sep 22 01:53:47 2010 (r5824) +++ trunk/src/southbridge/amd/sb700/sb700.h Thu Sep 23 00:46:47 2010 (r5825) @@ -52,6 +52,11 @@ #ifdef __PRE_RAM__ void sb700_lpc_port80(void); void sb700_pci_port80(void); +#else +#include <device/pci.h> +/* allow override in mainboard.c */ +void sb700_setup_sata_phys(struct device *dev); + #endif #endif /* SB700_H */ Modified: trunk/src/southbridge/amd/sb700/sb700_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sata.c Wed Sep 22 01:53:47 2010 (r5824) +++ trunk/src/southbridge/amd/sb700/sb700_sata.c Thu Sep 23 00:46:47 2010 (r5825) @@ -53,6 +53,29 @@ return 0; } + /* This function can be overloaded in mainboard.c */ + +void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) { + /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ + pci_write_config16(dev, 0x86, 0x2c00); + + /* RPR7.6.2 SATA GENI PHY ports setting */ + pci_write_config32(dev, 0x88, 0x01B48017); + pci_write_config32(dev, 0x8c, 0x01B48019); + pci_write_config32(dev, 0x90, 0x01B48016); + pci_write_config32(dev, 0x94, 0x01B48016); + pci_write_config32(dev, 0x98, 0x01B48016); + pci_write_config32(dev, 0x9C, 0x01B48016); + + /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ + pci_write_config16(dev, 0xA0, 0xA09A); + pci_write_config16(dev, 0xA2, 0xA09F); + pci_write_config16(dev, 0xA4, 0xA07A); + pci_write_config16(dev, 0xA6, 0xA07A); + pci_write_config16(dev, 0xA8, 0xA07A); + pci_write_config16(dev, 0xAA, 0xA07A); +} + static void sata_init(struct device *dev) { u8 byte; @@ -161,27 +184,7 @@ /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); - - /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ - word = 0x2c00; - pci_write_config16(dev, 0x86, word); - - /* RPR7.6.2 SATA GENI PHY ports setting */ - pci_write_config32(dev, 0x88, 0x01B48017); - pci_write_config32(dev, 0x8c, 0x01B48019); - pci_write_config32(dev, 0x90, 0x01B48016); - pci_write_config32(dev, 0x94, 0x01B48016); - pci_write_config32(dev, 0x98, 0x01B48016); - pci_write_config32(dev, 0x9C, 0x01B48016); - - /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ - pci_write_config16(dev, 0xA0, 0xA09A); - pci_write_config16(dev, 0xA2, 0xA09F); - pci_write_config16(dev, 0xA4, 0xA07A); - pci_write_config16(dev, 0xA6, 0xA07A); - pci_write_config16(dev, 0xA8, 0xA07A); - pci_write_config16(dev, 0xAA, 0xA07A); - + sb700_setup_sata_phys(dev); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0;

1 0

[PATCH] [RFC] sata PHY settings callback on SB700
by Rudolf Marek 22 Sep '10

22 Sep '10

Hi from Fort Worth, Here is a proposed way how to handle the SATA PHY settings on SB700. It consists of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Please tell if it is ok this way. I suggest all people who ported SB700 should have a look on their SATA PHY settings too because it is most likely PCB/MB dependent. This patch is not tested but it could work. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> My holiday ends soonish but I temped to do bit of stuff during El Paso - Forth Worth ride ;) Thanks, Rudolf

4 7

← Newer
1
...
12
13
14
15
16
17
18
...
33
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2010