coreboot June 2010

coreboot@coreboot.org

60 participants
222 discussions

SuperIO PNP resource allocation help
by Joseph Smith 16 Jun '10

16 Jun '10

Hello, Need some help understanding how the SuperIO PNP resource allocation works. Particularly src/superio/smsc/smscsuperio pnp_dev_info. I need to reserve 128 bytes for device { &ops, LD_PME, } but I am not really sure how the magic behind this works. Anyone that could shed a light I would be much appreciated. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[PATCH]libpayload: libc-style headers, some more functions
by Patrick Georgi 16 Jun '10

16 Jun '10

Hi, attached patch moves functions out of the huge libpayload.h into headers according to libc/posix traditions, to simplify porting applications to payloads. It also adds a couple of functions: strcasecmp, strncasecmp, strcat, strtol, strspn, strcspn, strtok_r, strtok, perror, exit, getpagesize baiyin cai, I added you to the recipients, as marc indicated that this might overlap with your summer of code effort. Comments are appreciated. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 2

Winflashrom plans
by Darmawan Salihun 15 Jun '10

15 Jun '10

Hello guys, Sorry, I haven't been able to update Winflashrom for more than 3 years now. I'm planning to add Windows 7 support next month. Therefore, I'm looking for suggestions. A bit of Winflashrom background of the currently available Winflashrom (at flashrom.org): The programming model: a. User mode application: - Mostly "pure" flashrom source code recompiled with MinGW. - libpci recompiled with MinGW (for PCI access logic). This is required because the PCI access functions in the Windows API is not guaranteed (marked as obsolete), in Windows XP SP2 and Windows 2003 server back then. b. Device driver: - Provides POSIX mmap() implementation in the kernel, i.e. provides an entrypoint for mmap() function to user mode application. - Provides direct I/O port access for libpci. Well, the reason for these programming model is to reduce the burden when moving to newer flash chip support because this programming model "preserves" the POSIX API in the user mode application (the device driver is generic enough). Therefore, "only" the user mode application need to be recompiled to support new flash chip. Any suggestions on what to change from the current programming model? Thanks, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Serial Console only starts after reset
by Joseph Smith 15 Jun '10

15 Jun '10

Hello, I have a strange thing happening on the i810 port I am working on. When I power the board on i do not get any serial console from coreboot. VGA turns on and works fine, but no serial output. The strange part is if I push the reset button, serial console comes up and works fine until the next power off. The SuperIO is SMSC LPC47M102 and I am using superio/smsc/smscsuperio. Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [coreboot] PATCH: Add support for Virtensys 2uRack and Napoli
by Myles Watson 15 Jun '10

15 Jun '10

On Mon, Jun 14, 2010 at 8:23 AM, Edwin Beasant <edwin_beasant(a)virtensys.com> wrote: > Add Virtensys as a Manufacturer to the build sytem, and add their products. > > Virtensys products use AMD Geode LX in configuration very similar to AMD > Norwich designs. > > Virtensys boards differ in the following ways from the reference > implementation. > > No PCI Physical Slots. > Intel 1Gig Ethernet onboard. > Pericom PCI->PCIe bridge onboard. > Napoli represents the Blade range of products > 2uRack represents the 2u Rackable products. > > Signed-off-by: Edwin Beasant edwin_beasant(a)virtensys.com A couple of questions: 1. Does this support make them both work perfectly? Is there anything left to fix? 2. Why do we need a cmos.layout file if HAVE_OPTION_TABLE is N? 3. Can we get rid of the commented out lines in the cmos.layout file if it needs to stay? Sorry I don't have the hardware to test, so I have to have more information about how it's working before wanting to Ack. Thanks, Myles

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unable to boot linux with coreboot
by mbertens 15 Jun '10

15 Jun '10

Hi all, i have a strong problem that im not able to boot any os wit coreboot, it starts (linux) ut it hangs after 128 sec. http://pastebin.com/uBT8JdH4 Anyone any ideas Marc

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Indtast Bcc problems with M2V-MX SE + VGA
by anders＠jenbo.dk 14 Jun '10

14 Jun '10

Worked for me on a system with an onboard card based on i810th chipset. Mvh Anders ----- Reply message ----- Fra: "Andrew Morgan" <ziltro(a)ziltro.com> Dato: man., jun. 14, 2010 17:27 Emne: [coreboot] problems with M2V-MX SE + VGA Til: <coreboot(a)coreboot.org> Just a thought, have you tried with no VGA BIOS? You won't get any screen output until X loads, but after that point it should work fine, while in X. On a plug-in card that's how it works but I don't know if the onboard chip will be enabled by default, enabled by Coreboot or disabled because the VGA BIOS isn't run. I don't know exactly what this might prove but it is something to try anyway. -- Andrew. -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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problems with M2V-MX SE + VGA
by Nathan Owens 14 Jun '10

14 Jun '10

Hello Everyone, I'm trying to compile Coreboot+SeaBIOS+VGA on an ASUS M2V-MX SE, using the VGA BIOS I extracted from the vendor BIOS. The result is that I can get to the bootloader menu (GRUB2, Debian Squeeze), but after 5-7 seconds the video dies and or turns to random junk on the screen. Only on one occasion did it get past trying to start GDM (GNOME Display Manager). On that occasion I had deselected "set up bridges on path to VGA adapter" in kconfig. The video was very low resolution (about 600X400) and it allowed me to log in to a desktop, but after the usual 5-7 seconds the video turned to random junk. I have been working on this since the beginning of May and have tried many, many combinations of settings in kconfig, including of course the recommended settings from the SeaBIOS page. Here are a few of the things I've tried: I'm reasonably sure I have a good VGA BIOS image, since the one I extracted matches bit for bit another one provided to me by Ruik. I've compiled my own SeaBIOS and tried the pre-compiled one provided on the SeaBIOS page. I've compiled and tried FILO as well, but more or less the same thing happens. The motherboard and video work just fine with the vendor BIOS. I also tried installing a video card (Radeon X300SE) in the PCI-e 16x slot, but Coreboot doesn't even work when I do that. I've tried many combinations of kconfig settings for this, but no luck. This card works with the vendor BIOS. Here are couple of questions I have: Is anyone having similar problems with this board? I'd like to send some debugging info to the list (i.e, the boot log), but I'm not quite sure how to obtain this. Can someone point me to some documentation for obtaining the boot log from this board. I assume it's going to require some hardware. Does anyone have any suggestions for kconfig settings that I should use? Thanks, Nate

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ottawa linux symposium
by Joe Korty 14 Jun '10

14 Jun '10

Hi Everyone, My company is sending me to OLS this year. I'd like to meet up with any of you that might also be going. Regards, Joe

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PATCH: Add support for Virtensys 2uRack and Napoli
by Edwin Beasant 14 Jun '10

14 Jun '10

Add Virtensys as a Manufacturer to the build sytem, and add their products. Virtensys products use AMD Geode LX in configuration very similar to AMD Norwich designs. Virtensys boards differ in the following ways from the reference implementation. No PCI Physical Slots. Intel 1Gig Ethernet onboard. Pericom PCI->PCIe bridge onboard. Napoli represents the Blade range of products 2uRack represents the 2u Rackable products. Signed-off-by: Edwin Beasant edwin_beasant(a)virtensys.com<mailto:edwin_beasant@virtensys.com> Edwin Beasant

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coreboot June 2010