coreboot June 2010

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build service results for r5626
by repository service 10 Jun '10

10 Jun '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5626 to the coreboot repository. This caused the following changes: Change Log: Same conversion as with resources from static arrays to lists, except there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5626&device=rumba&vendor=a… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5626 - in trunk: src/arch/i386/boot src/cpu/amd/sc520 src/devices src/devices/oprom/yabel src/drivers/generic/debug src/drivers/i2c/i2cmux src/drivers/i2c/i2cmux2 src/include/device src/m...
by repository service 10 Jun '10

10 Jun '10

Author: myles Date: Thu Jun 10 00:41:35 2010 New Revision: 5626 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5626 Log: Same conversion as with resources from static arrays to lists, except there is no free list. Converting resource arrays to lists reduced the size of each device struct from 1092 to 228 bytes. Converting link arrays to lists reduced the size of each device struct from 228 to 68 bytes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/boot/mpspec.c trunk/src/cpu/amd/sc520/sc520.c trunk/src/devices/cardbus_device.c trunk/src/devices/device.c trunk/src/devices/device_util.c trunk/src/devices/oprom/yabel/device.c trunk/src/devices/pci_device.c trunk/src/devices/pcix_device.c trunk/src/devices/root_device.c trunk/src/devices/smbus_ops.c trunk/src/drivers/generic/debug/debug_dev.c trunk/src/drivers/i2c/i2cmux/i2cmux.c trunk/src/drivers/i2c/i2cmux2/i2cmux2.c trunk/src/include/device/device.h trunk/src/mainboard/emulation/qemu-x86/northbridge.c trunk/src/mainboard/ibase/mb899/mptable.c trunk/src/mainboard/kontron/986lcd-m/mptable.c trunk/src/mainboard/tyan/s2881/mainboard.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/gx1/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/intel/e7501/northbridge.c trunk/src/northbridge/intel/e7520/northbridge.c trunk/src/northbridge/intel/e7525/northbridge.c trunk/src/northbridge/intel/i3100/northbridge.c trunk/src/northbridge/intel/i3100/pciexp_porta_ep80579.c trunk/src/northbridge/intel/i440bx/northbridge.c trunk/src/northbridge/intel/i440lx/northbridge.c trunk/src/northbridge/intel/i82810/northbridge.c trunk/src/northbridge/intel/i82830/northbridge.c trunk/src/northbridge/intel/i855/northbridge.c trunk/src/northbridge/intel/i945/northbridge.c trunk/src/northbridge/via/cn400/northbridge.c trunk/src/northbridge/via/cn700/northbridge.c trunk/src/northbridge/via/cx700/northbridge.c trunk/src/northbridge/via/vt8601/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/northbridge.c trunk/src/southbridge/amd/amd8131/amd8131_bridge.c trunk/src/southbridge/amd/amd8132/amd8132_bridge.c trunk/src/southbridge/amd/sb600/sb600_lpc.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c trunk/src/southbridge/intel/pxhd/pxhd_bridge.c trunk/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/src/southbridge/nvidia/ck804/ck804_smbus.c trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c trunk/src/southbridge/sis/sis966/sis966_lpc.c trunk/util/sconfig/main.c Modified: trunk/src/arch/i386/boot/mpspec.c ============================================================================== --- trunk/src/arch/i386/boot/mpspec.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/arch/i386/boot/mpspec.c Thu Jun 10 00:41:35 2010 (r5626) @@ -190,7 +190,6 @@ { struct device *child; - int linkn; int i; int srcbus; int slot; @@ -198,9 +197,8 @@ struct bus *link; unsigned char dstirq_x[4]; - for (linkn = 0; linkn < dev->links; linkn++) { + for (link = dev->link_list; link; link = link->next) { - link = &dev->link[linkn]; child = link->children; srcbus = link->secondary; Modified: trunk/src/cpu/amd/sc520/sc520.c ============================================================================== --- trunk/src/cpu/amd/sc520/sc520.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/cpu/amd/sc520/sc520.c Thu Jun 10 00:41:35 2010 (r5626) @@ -130,8 +130,8 @@ device_t mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; // unsigned char rambits; @@ -168,7 +168,7 @@ idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } #if 0 Modified: trunk/src/devices/cardbus_device.c ============================================================================== --- trunk/src/devices/cardbus_device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/cardbus_device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -158,7 +158,7 @@ { uint16_t ctrl; ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); - ctrl |= (dev->link[0].bridge_ctrl & ( + ctrl |= (dev->link_list->bridge_ctrl & ( PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_NO_ISA | @@ -178,8 +178,8 @@ .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, + .init = 0, + .scan_bus = pci_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, }; Modified: trunk/src/devices/device.c ============================================================================== --- trunk/src/devices/device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -66,7 +66,6 @@ device_t alloc_dev(struct bus *parent, struct device_path *path) { device_t dev, child; - int link; spin_lock(&dev_lock); @@ -82,12 +81,6 @@ memset(dev, 0, sizeof(*dev)); memcpy(&dev->path, path, sizeof(*path)); - /* Initialize the back pointers in the link fields. */ - for (link = 0; link < MAX_LINKS; link++) { - dev->link[link].dev = dev; - dev->link[link].link = link; - } - /* By default devices are enabled. */ dev->enabled = 1; @@ -132,11 +125,11 @@ struct device *curdev; printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), __func__, - bus->secondary, bus->link); + bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { - int i; + struct bus *link; if (!curdev->enabled) { continue; } @@ -148,11 +141,11 @@ curdev->ops->read_resources(curdev); /* Read in the resources behind the current device's links. */ - for (i = 0; i < curdev->links; i++) - read_resources(&curdev->link[i]); + for (link = curdev->link_list; link; link = link->next) + read_resources(link); } printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link_num); } struct pick_largest_state { @@ -257,13 +250,13 @@ for (dev = bus->children; dev; dev = dev->sibling) { struct resource *child_bridge; - if (!dev->links) + if (!dev->link_list) continue; /* Find the resources with matching type flags. */ for (child_bridge = dev->resource_list; child_bridge; child_bridge = child_bridge->next) { - unsigned link; + struct bus* link; if (!(child_bridge->flags & IORESOURCE_BRIDGE) || (child_bridge->flags & type_mask) != type) @@ -275,8 +268,15 @@ * need it separated. Add the PREFETCH flag to the * type_mask and type. */ - link = IOINDEX_LINK(child_bridge->index); - compute_resources(&dev->link[link], child_bridge, + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + if (link == NULL) + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + compute_resources(link, child_bridge, type_mask | IORESOURCE_PREFETCH, type | (child_bridge->flags & IORESOURCE_PREFETCH)); @@ -505,13 +505,13 @@ for (dev = bus->children; dev; dev = dev->sibling) { struct resource *child_bridge; - if (!dev->links) + if (!dev->link_list) continue; /* Find the resources with matching type flags. */ for (child_bridge = dev->resource_list; child_bridge; child_bridge = child_bridge->next) { - unsigned link; + struct bus* link; if (!(child_bridge->flags & IORESOURCE_BRIDGE) || (child_bridge->flags & type_mask) != type) @@ -523,8 +523,15 @@ * need it separated. Add the PREFETCH flag to the * type_mask and type. */ - link = IOINDEX_LINK(child_bridge->index); - allocate_resources(&dev->link[link], child_bridge, + link = dev->link_list; + while (link && link->link_num != + IOINDEX_LINK(child_bridge->index)) + link = link->next; + if (link == NULL) + printk(BIOS_ERR, "link %ld not found on %s\n", + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); + allocate_resources(link, child_bridge, type_mask | IORESOURCE_PREFETCH, type | (child_bridge->flags & IORESOURCE_PREFETCH)); @@ -551,7 +558,7 @@ struct device *child; struct resource *res; struct resource *lim; - int i; + struct bus *link; printk(BIOS_SPEW, "%s: %s\n", __func__, dev_path(dev)); @@ -592,8 +599,8 @@ } /* Descend into every enabled child and look for fixed resources. */ - for (i = 0; i < dev->links; i++) - for (child = dev->link[i].children; child; + for (link = dev->link_list; link; link = link->next) + for (child = link->children; child; child = child->sibling) if (child->enabled) constrain_resources(child, limits); @@ -757,7 +764,7 @@ struct device *curdev; printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) { @@ -771,7 +778,7 @@ curdev->ops->set_resources(curdev); } printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link); + dev_path(bus->dev), bus->secondary, bus->link_num); } /** @@ -846,12 +853,12 @@ do_scan_bus = 1; while (do_scan_bus) { - int link; + struct bus *link; new_max = busdev->ops->scan_bus(busdev, max); do_scan_bus = 0; - for (link = 0; link < busdev->links; link++) { - if (busdev->link[link].reset_needed) { - if (reset_bus(&busdev->link[link])) { + for (link = busdev->link_list; link; link = link->next) { + if (link->reset_needed) { + if (reset_bus(link)) { do_scan_bus = 1; } else { busdev->bus->reset_needed = 1; @@ -940,30 +947,30 @@ /* Read the resources for the entire tree. */ printk(BIOS_INFO, "Reading resources...\n"); - read_resources(&root->link[0]); + read_resources(root->link_list); printk(BIOS_INFO, "Done reading resources.\n"); print_resource_tree(root, BIOS_SPEW, "After reading."); /* Compute resources for all domains. */ - for (child = root->link[0].children; child; child = child->sibling) { + for (child = root->link_list->children; child; child = child->sibling) { if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN)) continue; for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; if (res->flags & IORESOURCE_PREFETCH) { - compute_resources(&child->link[0], + compute_resources(child->link_list, res, MEM_MASK, PREF_TYPE); continue; } if (res->flags & IORESOURCE_MEM) { - compute_resources(&child->link[0], + compute_resources(child->link_list, res, MEM_MASK, MEM_TYPE); continue; } if (res->flags & IORESOURCE_IO) { - compute_resources(&child->link[0], + compute_resources(child->link_list, res, IO_MASK, IO_TYPE); continue; } @@ -971,14 +978,14 @@ } /* For all domains. */ - for (child = root->link[0].children; child; child=child->sibling) + for (child = root->link_list->children; child; child=child->sibling) if (child->path.type == DEVICE_PATH_PCI_DOMAIN) avoid_fixed_resources(child); /* Now we need to adjust the resources. MEM resources need to start at * the highest address managable. */ - for (child = root->link[0].children; child; child = child->sibling) { + for (child = root->link_list->children; child; child = child->sibling) { if (child->path.type != DEVICE_PATH_PCI_DOMAIN) continue; for (res = child->resource_list; res; res = res->next) { @@ -991,30 +998,30 @@ /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); - for (child = root->link[0].children; child; child = child->sibling) { + for (child = root->link_list->children; child; child = child->sibling) { if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN)) continue; for (res = child->resource_list; res; res = res->next) { if (res->flags & IORESOURCE_FIXED) continue; if (res->flags & IORESOURCE_PREFETCH) { - allocate_resources(&child->link[0], + allocate_resources(child->link_list, res, MEM_MASK, PREF_TYPE); continue; } if (res->flags & IORESOURCE_MEM) { - allocate_resources(&child->link[0], + allocate_resources(child->link_list, res, MEM_MASK, MEM_TYPE); continue; } if (res->flags & IORESOURCE_IO) { - allocate_resources(&child->link[0], + allocate_resources(child->link_list, res, IO_MASK, IO_TYPE); continue; } } } - assign_resources(&root->link[0]); + assign_resources(root->link_list); printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); @@ -1055,7 +1062,7 @@ if (dev->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), - dev->bus->link); + dev->bus->link_num); } printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); dev->initialized = 1; Modified: trunk/src/devices/device_util.c ============================================================================== --- trunk/src/devices/device_util.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/device_util.c Thu Jun 10 00:41:35 2010 (r5626) @@ -40,7 +40,7 @@ device_t find_dev_path(struct bus *parent, struct device_path *path) { device_t child; - for(child = parent->children; child; child = child->sibling) { + for (child = parent->children; child; child = child->sibling) { if (path_eq(path, &child->path)) { break; } @@ -213,7 +213,7 @@ const char *bus_path(struct bus *bus) { static char buffer[BUS_PATH_MAX]; - sprintf(buffer, "%s,%d", dev_path(bus->dev), bus->link); + sprintf(buffer, "%s,%d", dev_path(bus->dev), bus->link_num); return buffer; } @@ -303,7 +303,7 @@ { struct resource *res, *next, *prev = NULL; /* Move all of the free resources to the end */ - for(res = dev->resource_list; res; res = next) { + for (res = dev->resource_list; res; res = next) { next = res->next; if (!res->flags) free_resource(dev, res, prev); @@ -323,7 +323,7 @@ { struct resource *res; /* See if there is a resource with the appropriate index */ - for(res = dev->resource_list; res; res = res->next) { + for (res = dev->resource_list; res; res = res->next) { if (res->index == index) break; } @@ -496,9 +496,9 @@ buf[0] = '\0'; if (resource->flags & IORESOURCE_PCI_BRIDGE) { #if CONFIG_PCI_BUS_SEGN_BITS - sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link[0].secondary & 0xff); + sprintf(buf, "bus %04x:%02x ", dev->bus->secondary>>8, dev->link_list->secondary & 0xff); #else - sprintf(buf, "bus %02x ", dev->link[0].secondary); + sprintf(buf, "bus %02x ", dev->link_list->secondary); #endif } printk(BIOS_DEBUG, @@ -518,11 +518,11 @@ resource_search_t search, void *gp) { struct device *curdev; - for(curdev = bus->children; curdev; curdev = curdev->sibling) { + for (curdev = bus->children; curdev; curdev = curdev->sibling) { struct resource *res; /* Ignore disabled devices */ if (!curdev->enabled) continue; - for(res = curdev->resource_list; res; res = res->next) { + for (res = curdev->resource_list; res; res = res->next) { /* If it isn't the right kind of resource ignore it */ if ((res->flags & type_mask) != type) { continue; @@ -530,7 +530,9 @@ /* If it is a subtractive resource recurse */ if (res->flags & IORESOURCE_SUBTRACTIVE) { struct bus * subbus; - subbus = &curdev->link[IOINDEX_SUBTRACTIVE_LINK(res->index)]; + for (subbus = curdev->link_list; subbus; subbus = subbus->next) + if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) + break; search_bus_resources(subbus, type_mask, type, search, gp); continue; } @@ -544,11 +546,11 @@ resource_search_t search, void *gp) { struct device *curdev; - for(curdev = all_devices; curdev; curdev = curdev->next) { + for (curdev = all_devices; curdev; curdev = curdev->next) { struct resource *res; /* Ignore disabled devices */ if (!curdev->enabled) continue; - for(res = curdev->resource_list; res; res = res->next) { + for (res = curdev->resource_list; res; res = res->next) { /* If it isn't the right kind of resource ignore it */ if ((res->flags & type_mask) != type) { continue; @@ -579,10 +581,10 @@ void disable_children(struct bus *bus) { device_t child; - for(child = bus->children; child; child = child->sibling) { - int link; - for(link = 0; link < child->links; link++) { - disable_children(&child->link[link]); + for (child = bus->children; child; child = child->sibling) { + struct bus *link; + for (link = child->link_list; link; link = link->next) { + disable_children(link); } dev_set_enabled(child, 0); } @@ -590,8 +592,9 @@ static void resource_tree(struct device *root, int debug_level, int depth) { - int i = 0, link = 0; + int i = 0; struct device *child; + struct bus *link; struct resource *res; char indent[30]; /* If your tree has more levels, it's wrong. */ @@ -599,10 +602,12 @@ indent[i] = ' '; indent[i] = '\0'; - do_printk(debug_level, "%s%s links %x child on link 0", indent, - dev_path(root), root->links); - do_printk(debug_level, " %s\n", root->link[0].children ? - dev_path(root->link[0].children) : "NULL"); + do_printk(BIOS_DEBUG, "%s%s", indent, dev_path(root)); + if (root->link_list && root->link_list->children) + do_printk(BIOS_DEBUG, " child on link 0 %s", + dev_path(root->link_list->children)); + do_printk(BIOS_DEBUG, "\n"); + for (res = root->resource_list; res; res = res->next) { do_printk(debug_level, "%s%s resource base %llx size %llx align %d gran %d limit %llx flags %lx index %lx\n", @@ -612,9 +617,8 @@ res->flags, res->index); } - for (link = 0; link < root->links; link++) { - for (child = root->link[link].children; child; - child = child->sibling) + for (link = root->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) resource_tree(child, debug_level, depth + 1); } } @@ -640,13 +644,15 @@ char depth_str[20] = ""; int i; struct device *sibling; + struct bus *link; + for (i = 0; i < depth; i++) depth_str[i] = ' '; depth_str[i] = '\0'; do_printk(debug_level, "%s%s: enabled %d\n", depth_str, dev_path(dev), dev->enabled); - for (i = 0; i < dev->links; i++) { - for (sibling = dev->link[i].children; sibling; + for (link = dev->link_list; link; link = link->next) { + for (sibling = link->children; sibling; sibling = sibling->sibling) show_devs_tree(sibling, debug_level, depth + 1, i); } Modified: trunk/src/devices/oprom/yabel/device.c ============================================================================== --- trunk/src/devices/oprom/yabel/device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/oprom/yabel/device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -45,7 +45,7 @@ { int taa_index = 0; struct resource *r; - u8 bus = bios_device.dev->bus->link; + u8 bus = bios_device.dev->bus->link_num; u16 devfn = bios_device.dev->path.pci.devfn; bios_device.bus = bus; Modified: trunk/src/devices/pci_device.c ============================================================================== --- trunk/src/devices/pci_device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/pci_device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -551,15 +551,13 @@ void pci_dev_set_resources(struct device *dev) { struct resource *res; - unsigned link; + struct bus *bus; u8 line; for (res = dev->resource_list; res; res = res->next) { pci_set_resource(dev, res); } - for (link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -614,10 +612,10 @@ /* Enable I/O in command register if there is VGA card * connected with (even it does not claim I/O resource). */ - if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) + if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link[0].bridge_ctrl; + ctrl |= dev->link_list->bridge_ctrl; ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); @@ -1102,9 +1100,17 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); - bus = &dev->link[0]; - bus->dev = dev; - dev->links = 1; + if (dev->link_list == NULL) { + struct bus *link; + link = malloc(sizeof(*link)); + if (link == NULL) + die("Couldn't allocate a link!\n"); + memset(link, 0, sizeof(*link)); + link->dev = dev; + dev->link_list = link; + } + + bus = dev->link_list; /* Set up the primary, secondary and subordinate bus numbers. We have * no idea how many buses are behind this bridge yet, so we set the @@ -1179,7 +1185,7 @@ */ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) { - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); return max; } Modified: trunk/src/devices/pcix_device.c ============================================================================== --- trunk/src/devices/pcix_device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/pcix_device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -61,20 +61,11 @@ } } -unsigned int pcix_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void pcix_tune_bus(struct bus *bus) { device_t child; - max = pci_scan_bus(bus, min_devfn, max_devfn, max); - for(child = bus->children; child; child = child->sibling) { - if ( (child->path.pci.devfn < min_devfn) || - (child->path.pci.devfn > max_devfn)) - { - continue; - } + for(child = bus->children; child; child = child->sibling) pcix_tune_dev(child); - } - return max; } const char *pcix_speed(unsigned sstatus) @@ -124,18 +115,17 @@ unsigned pos; unsigned sstatus; + max = do_pci_scan_bridge(dev, max, pci_scan_bus); /* Find the PCI-X capability */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS); - if (PCI_X_SSTATUS_MFREQ(sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - max = do_pci_scan_bridge(dev, max, pci_scan_bus); - } else { - max = do_pci_scan_bridge(dev, max, pcix_scan_bus); + if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI) { + pcix_tune_bus(dev->link_list); } /* Print the PCI-X bus speed */ - printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link[0].secondary, pcix_speed(sstatus)); + printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, pcix_speed(sstatus)); return max; } Modified: trunk/src/devices/root_device.c ============================================================================== --- trunk/src/devices/root_device.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/root_device.c Thu Jun 10 00:41:35 2010 (r5626) @@ -75,17 +75,17 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) { device_t child; - unsigned link; + struct bus* link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for(link = 0; link < bus->links; link++) { + for(link = bus->link_list; link; link = link->next) { /* for smbus bus enumerate */ - child = bus->link[link].children; + child = link->children; if(child && child->path.type == DEVICE_PATH_I2C) { - bus->link[link].secondary = ++smbus_max; + link->secondary = ++smbus_max; } - for(child = bus->link[link].children; child; child = child->sibling) { + for(child =link->children; child; child = child->sibling) { if (child->chip_ops && child->chip_ops->enable_dev) { child->chip_ops->enable_dev(child); } @@ -94,15 +94,15 @@ } if (child->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), child->bus->link ); + dev_path(child->bus->dev), child->bus->link_num ); } printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled?"enabled": "disabled"); } } - for(link = 0; link < bus->links; link++) { - for(child = bus->link[link].children; child; child = child->sibling) { + for(link = bus->link_list; link; link = link->next) { + for(child = link->children; child; child = child->sibling) { if (!child->ops || !child->ops->scan_bus) continue; printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); @@ -130,10 +130,10 @@ */ void enable_childrens_resources(device_t dev) { - unsigned link; - for(link = 0; link < dev->links; link++) { + struct bus *link; + for(link = dev->link_list; link; link = link->next) { device_t child; - for(child = dev->link[link].children; child; child = child->sibling) { + for(child = link->children; child; child = child->sibling) { enable_resources(child); } } Modified: trunk/src/devices/smbus_ops.c ============================================================================== --- trunk/src/devices/smbus_ops.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/devices/smbus_ops.c Thu Jun 10 00:41:35 2010 (r5626) @@ -58,7 +58,7 @@ // printk(BIOS_INFO, " %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link); if (ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) { if (pbus_a[i]->dev->ops && pbus_a[i]->dev->ops->set_link) - pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link); + pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link_num); } } // printk(BIOS_INFO, " %s\n", dev_path(dev)); Modified: trunk/src/drivers/generic/debug/debug_dev.c ============================================================================== --- trunk/src/drivers/generic/debug/debug_dev.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/drivers/generic/debug/debug_dev.c Thu Jun 10 00:41:35 2010 (r5626) @@ -85,7 +85,7 @@ static void print_smbus_regs(struct device *dev) { int j; - printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link); + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link_num); printk(BIOS_DEBUG, "%s", dev_path(dev)); for(j = 0; j < 256; j++) { int status; @@ -107,22 +107,22 @@ static void print_smbus_regs_all(struct device *dev) { struct device *child; - int i; + struct bus *link; if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) { // Here don't need to call smbus_set_link, because we scan it from top to down if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) { if(dev->bus->dev->ops && dev->bus->dev->ops->set_link) - dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link); + dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link_num); } } if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev); } - for(i=0; i< dev->links; i++) { - for (child = dev->link[i].children; child; child = child->sibling) { + for(link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { print_smbus_regs_all(child); } } Modified: trunk/src/drivers/i2c/i2cmux/i2cmux.c ============================================================================== --- trunk/src/drivers/i2c/i2cmux/i2cmux.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/drivers/i2c/i2cmux/i2cmux.c Thu Jun 10 00:41:35 2010 (r5626) @@ -34,7 +34,7 @@ static void enable_dev(struct device *dev) { - if(dev->links>0) + if(dev->link_list != NULL) dev->ops = &i2cmux_operations; } Modified: trunk/src/drivers/i2c/i2cmux2/i2cmux2.c ============================================================================== --- trunk/src/drivers/i2c/i2cmux2/i2cmux2.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/drivers/i2c/i2cmux2/i2cmux2.c Thu Jun 10 00:41:35 2010 (r5626) @@ -33,7 +33,7 @@ static void enable_dev(struct device *dev) { - if(dev->links>0) + if(dev->link_list != NULL) dev->ops = &i2cmux2_operations; } Modified: trunk/src/include/device/device.h ============================================================================== --- trunk/src/include/device/device.h Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/include/device/device.h Thu Jun 10 00:41:35 2010 (r5626) @@ -40,8 +40,9 @@ struct bus { device_t dev; /* This bridge device */ device_t children; /* devices behind this bridge */ + struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ - unsigned char link; /* The index of this link */ + unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ @@ -49,8 +50,6 @@ unsigned disable_relaxed_ordering : 1; }; -#define MAX_RESOURCES 24 -#define MAX_LINKS 8 /* * There is one device structure for each slot-number/function-number * combination: @@ -79,9 +78,7 @@ /* links are (downstream) buses attached to the device, usually a leaf * device with no children has 0 buses attached and a bridge has 1 bus */ - struct bus link[MAX_LINKS]; - /* number of buses attached to the device */ - unsigned int links; + struct bus *link_list; struct device_operations *ops; const struct chip_operations *chip_ops; @@ -96,6 +93,7 @@ extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; +extern struct bus *free_links; /* Generic device interface functions */ device_t alloc_dev(struct bus *parent, struct device_path *path); Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -60,7 +60,7 @@ static void cpu_pci_domain_set_resources(device_t dev) { - u32 pci_tolm = find_pci_tolm(&dev->link[0]); + u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; int idx; @@ -91,7 +91,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static void cpu_pci_domain_read_resources(struct device *dev) Modified: trunk/src/mainboard/ibase/mb899/mptable.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/mptable.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/mainboard/ibase/mb899/mptable.c Thu Jun 10 00:41:35 2010 (r5626) @@ -70,7 +70,7 @@ if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); if (riser) { - riser_bus = riser->link[0].secondary; + riser_bus = riser->link_list->secondary; printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus); max_pci_bus = riser_bus; } Modified: trunk/src/mainboard/kontron/986lcd-m/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mptable.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/mainboard/kontron/986lcd-m/mptable.c Thu Jun 10 00:41:35 2010 (r5626) @@ -70,7 +70,7 @@ if (!riser) riser = dev_find_device(0x3388, 0x0022, 0); if (riser) { - riser_bus = riser->link[0].secondary; + riser_bus = riser->link_list->secondary; printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus); max_pci_bus = riser_bus; } Modified: trunk/src/mainboard/tyan/s2881/mainboard.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/mainboard.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/mainboard/tyan/s2881/mainboard.c Thu Jun 10 00:41:35 2010 (r5626) @@ -46,7 +46,7 @@ /* Find the ADT7463 device. */ path.type = DEVICE_PATH_I2C; path.i2c.device = 0x2d; - adt7463 = find_dev_path(smbus_dev->link, &path); + adt7463 = find_dev_path(smbus_dev->link_list, &path); if (!adt7463) die("ADT7463 not found\n"); printk(BIOS_DEBUG, "ADT7463 found\n"); @@ -113,7 +113,6 @@ { struct device_path path; device_t dummy; - unsigned link_i; max = root_dev_scan_bus(root, max); @@ -126,20 +125,10 @@ * as the last device to be initialized. */ - link_i = root->links; - if (link_i >= MAX_LINKS) { - printk(BIOS_DEBUG, "Reached MAX_LINKS, not configuring ADT7463"); - return max; - } - root->link[link_i].link = link_i; - root->link[link_i].dev = root; - root->link[link_i].children = 0; - root->links++; - path.type = DEVICE_PATH_PNP; path.pnp.port = 0; path.pnp.device = 0; - dummy = alloc_dev(&root->link[link_i], &path); + dummy = alloc_dev(root->link_list, &path); dummy->ops = &dummy_operations; return max; Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -137,7 +137,7 @@ } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, +static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -149,7 +149,7 @@ u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - u32 is_sublink1 = (link>3); + u32 is_sublink1 = (link_num>3); device_t devx; u32 busses; u32 segn = max>>8; @@ -162,7 +162,7 @@ if(is_sublink1) { u32 regpos; u32 reg; - regpos = 0x170 + 4 * (link&3); // it is only on sublink0 + regpos = 0x170 + 4 * (link_num&3); // it is only on sublink0 reg = pci_read_config32(dev, regpos); if(reg & 1) return max; // already ganged no sblink1 devx = get_node_pci(nodeid, 4); @@ -171,15 +171,15 @@ devx = dev; - dev->link[link].cap = 0x80 + ((link&3) *0x20); + link->cap = 0x80 + ((link_num&3) *0x20); do { - link_type = pci_read_config32(devx, dev->link[link].cap + 0x18); + link_type = pci_read_config32(devx, link->cap + 0x18); } while(link_type & ConnectionPending); if (!(link_type & LinkConnected)) { return max; } do { - link_type = pci_read_config32(devx, dev->link[link].cap + 0x18); + link_type = pci_read_config32(devx, link->cap + 0x18); } while(!(link_type & InitComplete)); if (!(link_type & NonCoherent)) { return max; @@ -187,7 +187,7 @@ /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link, &sysconf); + ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf); #if CONFIG_EXT_CONF_SUPPORT == 0 if(ht_c_index>=4) return max; @@ -199,7 +199,7 @@ */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -221,26 +221,26 @@ #endif max_bus = 0xfc | (segn<<8); - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + link->secondary = min_bus; + link->subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(devx, dev->link[link].cap + 0x14); + busses = pci_read_config32(devx, link->cap + 0x14); /* Configure the bus numbers for this bridge: the configuration * transactions will not be propagates by the bridge if it is * not correctly configured */ busses &= 0xffff00ff; - busses |= ((u32)(dev->link[link].secondary) << 8); - pci_write_config32(devx, dev->link[link].cap + 0x14, busses); + busses |= ((u32)(link->secondary) << 8); + pci_write_config32(devx, link->cap + 0x14, busses); /* set the config map space */ - set_config_map_reg(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -255,17 +255,17 @@ else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link, ht_c_index, (max+1)>>sysconf.segbit, (dev->link[link].subordinate)>>sysconf.segbit, sysconf.nodes); + clear_config_map_reg(nodeid, link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); } - dev->link[link].subordinate = max; - set_config_map_reg(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, sysconf.segbit, sysconf.nodes); + link->subordinate = max; + set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); sysconf.ht_c_num++; { @@ -278,14 +278,14 @@ sysconf.hcdn_reg[ht_c_index] = temp; } - store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf); + store_ht_c_conf_bus(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); return max; } -static u32 amdfam10_scan_chains(device_t dev, u32 max) +static unsigned amdfam10_scan_chains(device_t dev, unsigned max) { unsigned nodeid; - u32 link; + struct bus *link; unsigned sblink = sysconf.sblk; unsigned offset_unitid = 0; @@ -297,7 +297,9 @@ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif - max = amdfam10_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 + for (link = dev->link_list; link; link = link->next) + if (link->link_num == sblink) + max = amdfam10_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 } #endif @@ -305,19 +307,19 @@ max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif - for(link = 0; link < dev->links; link++) { + for(link = dev->link_list; link; link = link->next) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done + if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) + if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; #endif - max = amdfam10_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdfam10_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid); } return max; } @@ -482,12 +484,12 @@ static void amdfam10_read_resources(device_t dev) { - u32 nodeid, link; - + u32 nodeid; + struct bus *link; nodeid = amdfam10_nodeid(dev); - for(link = 0; link < dev->links; link++) { - if (dev->link[link].children) { - amdfam10_link_read_bases(dev, nodeid, link); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam10_link_read_bases(dev, nodeid, link->link_num); } } } @@ -496,7 +498,7 @@ u32 nodeid) { resource_t rbase, rend; - unsigned reg, link; + unsigned reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -525,20 +527,20 @@ /* Get the register and link */ reg = resource->index & 0xfff; // 4k - link = IOINDEX_LINK(resource->index); + link_num = IOINDEX_LINK(resource->index); if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8); - store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8); + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + store_conf_io_addr(nodeid, link_num, reg, (resource->index >> 24), rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] - store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8); + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] + store_conf_mmio_addr(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %02x link %02x>", - nodeid, link); + sprintf(buf, " <node %x link %x>", + nodeid, link_num); report_resource_stored(dev, resource, buf); } @@ -553,18 +555,18 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) { - unsigned link; + struct bus *link; /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = 0; link < dev->links; link++) { - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI == 1 - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) ) #endif break; @@ -572,16 +574,17 @@ } /* no VGA card installed */ - if (link == dev->links) + if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); - set_vga_enable_reg(nodeid, link); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); + set_vga_enable_reg(nodeid, link->link_num); } static void amdfam10_set_resources(device_t dev) { - u32 nodeid, link; + unsigned nodeid; + struct bus *bus; struct resource *res; /* Find the nodeid */ @@ -594,9 +597,7 @@ amdfam10_set_resource(dev, res, nodeid); } - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -672,22 +673,22 @@ #if CONFIG_PCI_64BIT_PREF_MEM == 0 pci_domain_read_resources(dev); #else - unsigned link; + struct bus *link; struct resource *resource; - for(link=0; link<dev->links; link++) { + for(link=dev->link_list; link; link = link->next) { /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link<<2)); + resource = new_resource(dev, 0|(link->link_num<<2)); resource->base = 0x400; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO; /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link<<2)); + resource = new_resource(dev, 1|(link->link_num<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link<<2)); + resource = new_resource(dev, 2|(link->link_num<<2)); resource->limit = 0xfcffffffffULL; resource->flags = IORESOURCE_MEM; } @@ -881,7 +882,7 @@ unsigned long mmio_basek; u32 pci_tolm; int i, idx; - u32 link; + struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; @@ -889,12 +890,12 @@ #if CONFIG_PCI_64BIT_PREF_MEM == 1 - for(link = 0; link < dev->links; link++) { + for(link = dev->link_list; link; link = link->next) { /* Now reallocate the pci resources memory with the * highest addresses I can manage. */ - mem1 = find_resource(dev, 1|(link<<2)); - mem2 = find_resource(dev, 2|(link<<2)); + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", mem1->base, mem1->limit, mem1->size, mem1->align); @@ -939,8 +940,8 @@ #endif pci_tolm = 0xffffffffUL; - for(link = 0; link<dev->links; link++) { - pci_tolm = find_pci_tolm(&dev->link[link], pci_tolm); + for(link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link, pci_tolm); } // FIXME handle interleaved nodes. If you fix this here, please fix @@ -1084,11 +1085,9 @@ #endif } - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; - if (bus->children) { - assign_resources(bus); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); } } } @@ -1097,6 +1096,7 @@ { u32 reg; int i; + struct bus *link; /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); @@ -1114,8 +1114,8 @@ #endif - for(i = 0; i < dev->links; i++) { - max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + for(link = dev->link_list; link; link = link->next) { + max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); } /* Tune the hypertransport transaction for best performance. @@ -1129,12 +1129,12 @@ u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link[0].disable_relaxed_ordering) { + if (!dev->link_list->disable_relaxed_ordering) { httc |= HTTC_RSP_PASS_PW; } printk(BIOS_SPEW, "%s passpw: %s\n", dev_path(dev), - (!dev->link[0].disable_relaxed_ordering)? + (!dev->link_list->disable_relaxed_ordering)? "enabled":"disabled"); pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } @@ -1197,6 +1197,42 @@ #endif } +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1250,7 +1286,7 @@ printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { - if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) { + if((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); @@ -1279,18 +1315,19 @@ #if CONFIG_CBB && (NODE_NUMS > 32) if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe - if(pci_domain->links==1) { - pci_domain->links++; // from 1 to 2 - pci_domain->link[1].link = 1; - pci_domain->link[1].dev = pci_domain; - pci_domain->link[1].children = 0; - printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(pci_domain), pci_domain->links); + if(pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); } - pci_domain->link[1].secondary = CONFIG_CBB - 1; + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; } #endif /* Find which cpus are present */ - cpu_bus = &dev->link[0]; + cpu_bus = dev->link_list; for(i = 0; i < nodes; i++) { device_t cdb_dev, cpu; struct device_path cpu_path; @@ -1304,7 +1341,7 @@ if(i>=32) { busn--; devn-=32; - pbus = &(pci_domain->link[1]); + pbus = pci_domain->link_list->next); } #endif @@ -1325,21 +1362,13 @@ /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int link; int linknum; #if CONFIG_HT3_SUPPORT==1 linknum = 8; #else linknum = 4; #endif - if (cdb_dev->links < linknum) { - for(link=cdb_dev->links; link<linknum; link++) { - cdb_dev->link[link].link = link; - cdb_dev->link[link].dev = cdb_dev; - } - cdb_dev->links = linknum; - printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(cdb_dev), cdb_dev->links); - } + add_more_links(cdb_dev, linknum); } cores_found = 0; // one core @@ -1410,7 +1439,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -81,7 +81,7 @@ return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, +static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { @@ -94,15 +94,15 @@ u32 min_bus; u32 max_devfn; - dev->link[link].cap = 0x80 + (link *0x20); + link->cap = 0x80 + (link_num *0x20); do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + link_type = pci_read_config32(dev, link->cap + 0x18); } while(link_type & ConnectionPending); if (!(link_type & LinkConnected)) { return max; } do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + link_type = pci_read_config32(dev, link->cap + 0x18); } while(!(link_type & InitComplete)); if (!(link_type & NonCoherent)) { return max; @@ -120,7 +120,7 @@ } if (((config & 3) == 3) && (((config >> 4) & 7) == nodeid) && - (((config >> 8) & 3) == link)) { + (((config >> 8) & 3) == link_num)) { break; } } @@ -140,7 +140,7 @@ */ #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -160,13 +160,13 @@ #endif max_bus = 0xff; - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; + link->secondary = min_bus; + link->subordinate = max_bus; /* Read the existing primary/secondary/subordinate bus * number configuration. */ - busses = pci_read_config32(dev, dev->link[link].cap + 0x14); + busses = pci_read_config32(dev, link->cap + 0x14); config_busses = f1_read_config32(config_reg); /* Configure the bus numbers for this bridge: the configuration @@ -175,17 +175,17 @@ */ busses &= 0xff000000; busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(dev->link[link].secondary) << 8) | - ((unsigned int)(dev->link[link].subordinate) << 16)); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + ((unsigned int)(link->secondary) << 8) | + ((unsigned int)(link->subordinate) << 16)); + pci_write_config32(dev, link->cap + 0x14, busses); config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | - ((dev->link[link].secondary) << 16) | - ((dev->link[link].subordinate) << 24); + (( link_num & 3 ) << 8) | + ((link->secondary) << 16) | + ((link->subordinate) << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -200,18 +200,18 @@ else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - dev->link[link].subordinate = max; + link->subordinate = max; busses = (busses & 0xff00ffff) | - ((unsigned int) (dev->link[link].subordinate) << 16); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + ((unsigned int) (link->subordinate) << 16); + pci_write_config32(dev, link->cap + 0x14, busses); config_busses = (config_busses & 0x00ffffff) | - (dev->link[link].subordinate << 24); + (link->subordinate << 24); f1_write_config32(config_reg, config_busses); { @@ -232,7 +232,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) { unsigned nodeid; - unsigned link; + struct bus *link; unsigned sblink = 0; unsigned offset_unitid = 0; @@ -244,23 +244,25 @@ #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif - max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 + for (link = dev->link_list; link; link = link->next) + if (link->link_num == sblink) + max = amdk8_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 #endif } - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done + if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done #endif offset_unitid = 0; #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) + if((nodeid == 0) && (sblink == link->link_num)) #endif offset_unitid = 1; #endif - max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + max = amdk8_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid); } return max; } @@ -375,21 +377,22 @@ static void amdk8_read_resources(device_t dev) { - unsigned nodeid, link; + unsigned nodeid; + struct bus *link; nodeid = amdk8_nodeid(dev); - for(link = 0; link < dev->links; link++) { - if (dev->link[link].children) { - amdk8_link_read_bases(dev, nodeid, link); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + amdk8_link_read_bases(dev, nodeid, link->link_num); } } - amdk8_create_vga_resource(dev, nodeid); } static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) { + struct bus *link; resource_t rbase, rend; - unsigned reg, link; + unsigned reg, link_num; char buf[50]; /* Make certain the resource has actually been set */ @@ -426,7 +429,17 @@ /* Get the register and link */ reg = resource->index & 0xfc; - link = IOINDEX_LINK(resource->index); + link_num = IOINDEX_LINK(resource->index); + + for (link = dev->link_list; link; link = link->next) + if (link->link_num == link_num) + break; + + if (link == NULL) { + printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__, + link_num, resource->index); + return; + } if (resource->flags & IORESOURCE_IO) { u32 base, limit; @@ -437,15 +450,15 @@ base |= 3; limit &= 0xfe000fc8; limit |= rend & 0x01fff000; - limit |= (link & 3) << 4; + limit |= (link_num & 3) << 4; limit |= (nodeid & 7); - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", - __func__, dev_path(dev), link); + __func__, dev_path(dev), link_num); base |= PCI_IO_BASE_VGA_EN; } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { base |= PCI_IO_BASE_NO_ISA; } @@ -461,14 +474,14 @@ base |= 3; limit &= 0x00000048; limit |= (rend >> 8) & 0xffffff00; - limit |= (link & 3) << 4; + limit |= (link_num & 3) << 4; limit |= (nodeid & 7); f1_write_config32(reg + 0x4, limit); f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; sprintf(buf, " <node %x link %x>", - nodeid, link); + nodeid, link_num); report_resource_stored(dev, resource, buf); } @@ -479,18 +492,18 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) { struct resource *resource; - unsigned link; + struct bus *link; /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ - for (link = 0; link < dev->links; link++) { - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI == 1 - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) ) #endif break; @@ -498,13 +511,13 @@ } /* no VGA card installed */ - if (link == dev->links) + if (link == NULL) return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); /* allocate a temp resource for the legacy VGA buffer */ - resource = new_resource(dev, IOINDEX(4, link)); + resource = new_resource(dev, IOINDEX(4, link->link_num)); if(!resource){ printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev)); return; @@ -518,7 +531,8 @@ static void amdk8_set_resources(device_t dev) { - unsigned nodeid, link; + unsigned nodeid; + struct bus *bus; struct resource *res; /* Find the nodeid */ @@ -553,9 +567,7 @@ compact_resources(dev); - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -909,7 +921,7 @@ } #endif - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix // amdfam10, too. @@ -1066,7 +1078,7 @@ } #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } @@ -1078,7 +1090,7 @@ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. @@ -1091,12 +1103,12 @@ u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link[0].disable_relaxed_ordering) { + if (!dev->link_list->disable_relaxed_ordering) { httc |= HTTC_RSP_PASS_PW; } printk(BIOS_SPEW, "%s passpw: %s\n", dev_path(dev), - (!dev->link[0].disable_relaxed_ordering)? + (!dev->link_list->disable_relaxed_ordering)? "enabled":"disabled"); pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } @@ -1113,6 +1125,42 @@ .ops_pci_bus = &pci_cf8_conf1, }; +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; @@ -1165,7 +1213,7 @@ } /* Find which cpus are present */ - cpu_bus = &dev->link[0]; + cpu_bus = dev->link_list; for(i = 0; i < sysconf.nodes; i++) { device_t cpu_dev, cpu; struct device_path cpu_path; @@ -1187,11 +1235,7 @@ */ dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); if(dev_f0) { - dev_f0->links = 3; - for(local_j=0;local_j<3;local_j++) { - dev_f0->link[local_j].link = local_j; - dev_f0->link[local_j].dev = dev_f0; - } + add_more_links(dev_f0, 3); } } @@ -1290,7 +1334,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/amd/gx1/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx1/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/amd/gx1/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -115,8 +115,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; unsigned int ramreg = 0; @@ -163,7 +163,7 @@ idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -177,7 +177,7 @@ static void cpu_bus_init(device_t dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/amd/gx2/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -303,11 +303,9 @@ pci_set_resource(dev, resource); } #endif - unsigned link; + struct bus *bus; - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { assign_resources(bus); } @@ -402,8 +400,8 @@ device_t mc_dev; u32 pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; unsigned int ramreg = 0; @@ -444,7 +442,7 @@ ram_resource(dev, idx++, 0, tolmk); } #endif - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -457,7 +455,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/amd/lx/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -318,7 +318,6 @@ static void northbridge_set_resources(struct device *dev) { - unsigned link; uint8_t line; #if 0 @@ -331,9 +330,8 @@ } #endif - for (link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; + struct bus *bus; + for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", bus->secondary); @@ -402,7 +400,7 @@ printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { tomk = get_systop() / 1024; /* Report the memory regions @@ -418,7 +416,7 @@ #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static void pci_domain_enable(device_t dev) @@ -452,7 +450,7 @@ { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/e7501/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7501/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/e7501/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -58,8 +58,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -135,7 +135,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -149,7 +149,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/e7520/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7520/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/e7520/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -62,7 +62,7 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -72,7 +72,7 @@ pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -151,7 +151,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 e7520_domain_scan_bus(device_t dev, u32 max) @@ -219,7 +219,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/e7525/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7525/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/e7525/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -62,7 +62,7 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -72,7 +72,7 @@ pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -151,7 +151,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 e7525_domain_scan_bus(device_t dev, u32 max) @@ -219,7 +219,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i3100/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i3100/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i3100/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -83,7 +83,7 @@ device_t mc_dev; u32 pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); #if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -93,7 +93,7 @@ pci_tolm = 0xe0000000; /* Ensure pci_tolm is 128M aligned */ pci_tolm &= 0xf8000000; - mc_dev = dev->link[0].children; + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -172,7 +172,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static u32 i3100_domain_scan_bus(device_t dev, u32 max) @@ -240,7 +240,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i3100/pciexp_porta_ep80579.c ============================================================================== --- trunk/src/northbridge/intel/i3100/pciexp_porta_ep80579.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i3100/pciexp_porta_ep80579.c Thu Jun 10 00:41:35 2010 (r5626) @@ -56,7 +56,7 @@ static void pcie_bus_enable_resources(struct device *dev) { - if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); Modified: trunk/src/northbridge/intel/i440bx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i440bx/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -82,8 +82,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; int idx; @@ -118,7 +118,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -131,7 +131,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i440lx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i440lx/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -110,8 +110,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; int idx; @@ -146,7 +146,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -159,7 +159,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i82810/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i82810/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -119,8 +119,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -178,7 +178,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -191,7 +191,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i82830/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -111,8 +111,8 @@ uint32_t pci_tolm; int igd_memory = 0; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (!mc_dev) return; @@ -152,7 +152,7 @@ ram_resource(dev, idx++, 768, 256); ram_resource(dev, idx++, 1024, tolmk - 1024); - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ @@ -171,7 +171,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i855/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i855/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i855/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -83,8 +83,8 @@ printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children->sibling; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); @@ -134,7 +134,7 @@ high_tables_size = HIGH_TABLES_SIZE * 1024; #endif } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -147,7 +147,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/intel/i945/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i945/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/intel/i945/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -138,7 +138,7 @@ /* Can we find out how much memory we can use at most * this way? */ - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", @@ -208,7 +208,7 @@ ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ @@ -326,7 +326,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/cn400/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn400/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/cn400/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -233,7 +233,7 @@ printk(BIOS_SPEW, "Entering %s.\n", __func__); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN400_MEMCTRL, 0); @@ -267,7 +267,7 @@ ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); printk(BIOS_SPEW, "Leaving %s.\n", __func__); } @@ -276,7 +276,7 @@ { printk(BIOS_DEBUG, "Entering %s.\n", __func__); - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); return max; } @@ -290,7 +290,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/cn700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn700/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/cn700/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -157,7 +157,7 @@ printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); @@ -199,7 +199,7 @@ ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -212,7 +212,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/cx700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/cx700/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -87,7 +87,7 @@ unsigned char rambits; int idx; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0); rambits = pci_read_config8(mc_dev, 0x88); @@ -128,7 +128,7 @@ /* TODO: Hole needed? Should this go elsewhere? */ ram_resource(dev, idx++, 0, 640); /* first 640k */ ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */ - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -141,7 +141,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/vt8601/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8601/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/vt8601/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -98,8 +98,8 @@ device_t mc_dev; uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; @@ -140,7 +140,7 @@ idx = 10; ram_resource(dev, idx++, 0, tolmk); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -153,7 +153,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/vt8623/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -158,8 +158,8 @@ printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; + pci_tolm = find_pci_tolm(dev->link_list); + mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; @@ -201,7 +201,7 @@ ram_resource(dev, idx++, 0, 640); /* first 640k */ ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */ } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -214,7 +214,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/northbridge/via/vx800/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/northbridge/via/vx800/northbridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -128,7 +128,7 @@ printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n"); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); @@ -175,7 +175,7 @@ /* Leave a hole for vga, 0xa0000 - 0xc0000 */ ram_resource(dev, idx++, 768, (tolmk - 768)); } - assign_resources(&dev->link[0]); + assign_resources(dev->link_list); } static struct device_operations pci_domain_ops = { @@ -188,7 +188,7 @@ static void cpu_bus_init(device_t dev) { - initialize_cpus(&dev->link[0]); + initialize_cpus(dev->link_list); } static void cpu_bus_noop(device_t dev) Modified: trunk/src/southbridge/amd/amd8131/amd8131_bridge.c ============================================================================== --- trunk/src/southbridge/amd/amd8131/amd8131_bridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/amd/amd8131/amd8131_bridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -25,7 +25,7 @@ continue; } if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) { - amd8131_walk_children(&child->link[0], visit, ptr); + amd8131_walk_children(child->link_list, visit, ptr); } visit(child, ptr); } Modified: trunk/src/southbridge/amd/amd8132/amd8132_bridge.c ============================================================================== --- trunk/src/southbridge/amd/amd8132/amd8132_bridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/amd/amd8132/amd8132_bridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -47,7 +47,7 @@ continue; } if (child->hdr_type == PCI_HEADER_TYPE_BRIDGE) { - amd8132_walk_children(&child->link[0], visit, ptr); + amd8132_walk_children(child->link_list, visit, ptr); } visit(child, ptr); } Modified: trunk/src/southbridge/amd/sb600/sb600_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/amd/sb600/sb600_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -106,7 +106,7 @@ */ static void sb600_lpc_enable_childrens_resources(device_t dev) { - u32 link; + struct bus *link; u32 reg, reg_x; int var_num = 0; u16 reg_var[3]; @@ -114,9 +114,9 @@ reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; + for (child = link->children; child; child = child->sibling) { enable_resources(child); if (child->enabled Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -118,7 +118,7 @@ */ static void sb700_lpc_enable_childrens_resources(device_t dev) { - u32 link; + struct bus *link; u32 reg, reg_x; int var_num = 0; u16 reg_var[3]; @@ -126,9 +126,9 @@ reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; + for (child = link->children; child; child = child->sibling) { enable_resources(child); if (child->enabled Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -67,14 +67,14 @@ */ static void bcm5785_lpc_enable_childrens_resources(device_t dev) { - unsigned link; + struct bus *link; uint32_t reg; reg = pci_read_config8(dev, 0x44); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; child = child->sibling) { + for (child = link->children; child; child = child->sibling) { enable_resources(child); if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_pci.c Thu Jun 10 00:41:35 2010 (r5626) @@ -100,10 +100,10 @@ /* enable IO in command register if there is VGA card * connected with (even it does not claim IO resource) */ - if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) + if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) dev->command |= PCI_COMMAND_IO; ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link[0].bridge_ctrl; + ctrl |= dev->link_list->bridge_ctrl; ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); Modified: trunk/src/southbridge/intel/pxhd/pxhd_bridge.c ============================================================================== --- trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Thu Jun 10 00:41:35 2010 (r5626) @@ -41,8 +41,7 @@ { int bus_100Mhz = 0; - dev->link[0].dev = dev; - dev->links = 1; + dev->link_list->dev = dev; get_option(&bus_100Mhz, "pxhd_bus_speed_100"); if(bus_100Mhz) { @@ -58,7 +57,7 @@ pci_write_config16(dev, 0x40, word); /* reset the bus to make the new frequencies effective */ - pci_bus_reset(&dev->link[0]); + pci_bus_reset(dev->link_list); } return pcix_scan_bridge(dev, max); } Modified: trunk/src/southbridge/nvidia/ck804/ck804_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -231,15 +231,15 @@ */ static void ck804_lpc_enable_childrens_resources(device_t dev) { - unsigned link; + struct bus *link; uint32_t reg, reg_var[4]; int i, var_num = 0; reg = pci_read_config32(dev, 0xa0); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; child = child->sibling) { + for (child = link->children; child; child = child->sibling) { enable_resources(child); if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; Modified: trunk/src/southbridge/nvidia/ck804/ck804_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_smbus.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/nvidia/ck804/ck804_smbus.c Thu Jun 10 00:41:35 2010 (r5626) @@ -23,7 +23,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_recv_byte(res->base, device); } @@ -37,7 +37,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_send_byte(res->base, device, val); } @@ -51,7 +51,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_read_byte(res->base, device, address); } @@ -65,7 +65,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_write_byte(res->base, device, address, val); } Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -205,16 +205,16 @@ */ static void mcp55_lpc_enable_childrens_resources(device_t dev) { - unsigned link; uint32_t reg, reg_var[4]; int i; int var_num = 0; + struct bus *link; reg = pci_read_config32(dev, 0xa0); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; child = child->sibling) { + for (child = link->children; child; child = child->sibling) { enable_resources(child); if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c Thu Jun 10 00:41:35 2010 (r5626) @@ -41,7 +41,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_recv_byte(res->base, device); } @@ -55,7 +55,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_send_byte(res->base, device, val); } @@ -69,7 +69,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_read_byte(res->base, device, address); } @@ -83,7 +83,7 @@ device = dev->path.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link_num * 4)); return do_smbus_write_byte(res->base, device, address, val); } Modified: trunk/src/southbridge/sis/sis966/sis966_lpc.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_lpc.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/src/southbridge/sis/sis966/sis966_lpc.c Thu Jun 10 00:41:35 2010 (r5626) @@ -198,16 +198,16 @@ */ static void sis966_lpc_enable_childrens_resources(device_t dev) { - unsigned link; + struct bus *link; uint32_t reg, reg_var[4]; int i; int var_num = 0; reg = pci_read_config32(dev, 0xa0); - for (link = 0; link < dev->links; link++) { + for (link = dev->link_list; link; link = link->next) { device_t child; - for (child = dev->link[link].children; child; child = child->sibling) { + for (child = link->children; child; child = child->sibling) { enable_resources(child); if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; Modified: trunk/util/sconfig/main.c ============================================================================== --- trunk/util/sconfig/main.c Thu Jun 10 00:39:00 2010 (r5625) +++ trunk/util/sconfig/main.c Thu Jun 10 00:41:35 2010 (r5626) @@ -278,10 +278,14 @@ } static void pass0(FILE *fil, struct device *ptr) { + if (ptr->type == device && ptr->id == 0) + fprintf(fil, "struct bus %s_links[];\n", ptr->name); if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) { fprintf(fil, "struct device %s;\n", ptr->name); if (ptr->rescnt > 0) fprintf(fil, "struct resource %s_res[];\n", ptr->name); + if (ptr->children || ptr->multidev) + fprintf(fil, "struct bus %s_links[];\n", ptr->name); } if ((ptr->type == device) && (ptr->id != 0) && ptr->used) fprintf(fil, "struct device %s;\n", ptr->aliased_name); @@ -291,7 +295,7 @@ if (!ptr->used && (ptr->type == device)) { fprintf(fil, "struct device %s = {\n", ptr->name); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); - fprintf(fil, "\t.bus = &%s.link[%d],\n", ptr->bus->name, ptr->bus->link); + fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); fprintf(fil, "\t.path = {"); fprintf(fil, ptr->path, ptr->path_a, ptr->path_b); fprintf(fil, "},\n"); @@ -301,33 +305,10 @@ fprintf(fil, "\t.resource_list = &%s_res[0],\n", ptr->name); } int link = 0; - fprintf(fil, "\t.link = {\n"); - if (ptr->multidev) { - struct device *d = ptr; - while (d) { - if (device_match(d, ptr)) { - fprintf(fil, "\t\t[%d] = {\n", d->link); - fprintf(fil, "\t\t\t.link = %d,\n", d->link); - fprintf(fil, "\t\t\t.dev = &%s,\n", d->name); - if (d->children) - fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - d = d->next_sibling; - } - } else { - if (ptr->children) { - fprintf(fil, "\t\t[0] = {\n"); - fprintf(fil, "\t\t\t.link = 0,\n"); - fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name); - fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name); - fprintf(fil, "\t\t},\n"); - link++; - } - } - fprintf(fil, "\t},\n"); - fprintf(fil, "\t.links = %d,\n", link); + if (ptr->children || ptr->multidev) + fprintf(fil, "\t.link_list = &%s_links[0],\n", ptr->name); + else + fprintf(fil, "\t.link_list = NULL,\n", ptr->name); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) { @@ -356,6 +337,37 @@ } fprintf(fil, "\t };\n"); } + if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) { + fprintf(fil, "struct bus %s_links[] = {\n", ptr->name); + if (ptr->multidev) { + struct device *d = ptr; + while (d) { + if (device_match(d, ptr)) { + fprintf(fil, "\t\t[%d] = {\n", d->link); + fprintf(fil, "\t\t\t.link_num = %d,\n", d->link); + fprintf(fil, "\t\t\t.dev = &%s,\n", d->name); + if (d->children) + fprintf(fil, "\t\t\t.children = &%s,\n", d->children->name); + if (device_match(d->next_sibling, ptr)) + fprintf(fil, "\t\t\t.next=&%s_links[%d],\n", d->name, d->link+1); + else + fprintf(fil, "\t\t\t.next = NULL,\n"); + fprintf(fil, "\t\t},\n"); + } + d = d->next_sibling; + } + } else { + if (ptr->children) { + fprintf(fil, "\t\t[0] = {\n"); + fprintf(fil, "\t\t\t.link_num = 0,\n"); + fprintf(fil, "\t\t\t.dev = &%s,\n", ptr->name); + fprintf(fil, "\t\t\t.children = &%s,\n", ptr->children->name); + fprintf(fil, "\t\t\t.next = NULL,\n"); + fprintf(fil, "\t\t},\n"); + } + } + fprintf(fil, "\t};\n"); + } if ((ptr->type == chip) && (ptr->chiph_exists)) { if (ptr->reg) { fprintf(fil, "struct %s_config %s_info_%d\t= {\n", ptr->name_underscore, ptr->name_underscore, ptr->id);

1 0

[commit] r5625 - in trunk/src/northbridge/amd: amdfam10 amdk8
by repository service 10 Jun '10

10 Jun '10

Author: myles Date: Thu Jun 10 00:39:00 2010 New Revision: 5625 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5625 Log: Make k8 & fam10 northbridge.c code more similar. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/northbridge.c Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Wed Jun 9 21:07:19 2010 (r5624) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) @@ -55,6 +55,7 @@ static device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; +static unsigned fx_devs=0; device_t get_node_pci(u32 nodeid, u32 fn) { @@ -68,37 +69,37 @@ #else return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); #endif - } + static void get_fx_devs(void) { int i; - if (__f1_dev[0]) { - return; - } for(i = 0; i < FX_DEVS; i++) { __f0_dev[i] = get_node_pci(i, 0); __f1_dev[i] = get_node_pci(i, 1); __f2_dev[i] = get_node_pci(i, 2); __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; } - if (!__f1_dev[0]) { - printk(BIOS_ERR, "Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB); - die("Cannot go on\n"); + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); } } -static u32 f1_read_config32(u32 reg) +static u32 f1_read_config32(unsigned reg) { - get_fx_devs(); + if (fx_devs == 0) + get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(u32 reg, u32 value) +static void f1_write_config32(unsigned reg, u32 value) { int i; - get_fx_devs(); - for(i = 0; i < FX_DEVS; i++) { + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { device_t dev; dev = __f1_dev[i]; if (dev && dev->enabled) { @@ -107,7 +108,6 @@ } } - static u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 @@ -197,11 +197,10 @@ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here - min_bus = max; + min_bus = max; } #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 @@ -211,12 +210,12 @@ min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same } max = min_bus | (segn<<8); - #else + #else //other ... else { min_bus = ++max; } - #endif + #endif #else min_bus = ++max; #endif @@ -224,6 +223,7 @@ dev->link[link].secondary = min_bus; dev->link[link].subordinate = max_bus; + /* Read the existing primary/secondary/subordinate bus * number configuration. */ @@ -257,7 +257,6 @@ max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); - /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ @@ -270,7 +269,7 @@ sysconf.ht_c_num++; { - // config config_reg, and ht_unitid_base to update hcdn_reg; + // use ht_unitid_base to update hcdn_reg u32 temp = 0; for(i=0;i<4;i++) { temp |= (ht_unitid_base[i] & 0xff) << (i*8); @@ -279,23 +278,19 @@ sysconf.hcdn_reg[ht_c_index] = temp; } - - store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf); - - + store_ht_c_conf_bus(nodeid, link, ht_c_index, dev->link[link].secondary, dev->link[link].subordinate, &sysconf); return max; } static u32 amdfam10_scan_chains(device_t dev, u32 max) { - u32 nodeid; + unsigned nodeid; u32 link; - u32 sblink = sysconf.sblk; - u32 offset_unitid = 0; + unsigned sblink = sysconf.sblk; + unsigned offset_unitid = 0; nodeid = amdfam10_nodeid(dev); - // Put sb chain in bus 0 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if(nodeid==0) { @@ -306,12 +301,10 @@ } #endif - #if CONFIG_PCI_BUS_SEGN_BITS max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif - for(link = 0; link < dev->links; link++) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done @@ -330,14 +323,14 @@ } -static int reg_useable(u32 reg,device_t goal_dev, u32 goal_nodeid, - u32 goal_link) +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) { struct resource *res; - u32 nodeid, link = 0; + unsigned nodeid, link = 0; int result; res = 0; - for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) { + for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { device_t dev; dev = __f0_dev[nodeid]; if (!dev) @@ -358,7 +351,7 @@ return result; } -static struct resource *amdfam10_find_iopair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -433,7 +426,7 @@ struct resource *resource; /* Initialize the io space constraints on the current bus */ - resource = amdfam10_find_iopair(dev, nodeid, link); + resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; #if CONFIG_EXT_CONF_SUPPORT == 1 @@ -454,12 +447,13 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam10_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_BRIDGE; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; #if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext @@ -472,23 +466,20 @@ /* Initialize the memory constraints on the current bus */ resource = amdfam10_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - #if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } #endif - } } - static void amdfam10_read_resources(device_t dev) { u32 nodeid, link; @@ -501,7 +492,6 @@ } } - static void amdfam10_set_resource(device_t dev, struct resource *resource, u32 nodeid) { @@ -613,7 +603,6 @@ } } - static void amdfam10_enable_resources(device_t dev) { pci_dev_enable_resources(dev); @@ -665,14 +654,14 @@ } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); } - reg_link = (limit >> 4) & 7; + reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; if (reg_dev) { /* Reserve the resource */ - struct resource *reg_resource; - reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (reg_resource) { - reg_resource->flags = 1; + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; } } } @@ -714,8 +703,8 @@ return; } resource = new_resource(dev, index); - resource->base = basek << 10; - resource->size = sizek << 10; + resource->base = basek << 10; + resource->size = sizek << 10; resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } @@ -798,9 +787,9 @@ // WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards. // Does it make sense not to? #if CONFIG_AMDMCT == 0 -static void disable_hoist_memory(unsigned long hole_startk, int i) +static void disable_hoist_memory(unsigned long hole_startk, int node_id) { - int ii; + int i; device_t dev; struct dram_base_mask_t d; u32 sel_m; @@ -811,7 +800,7 @@ u32 one_DCT; struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; - meminfo = &sysinfox->meminfo[i]; + meminfo = &sysinfox->meminfo[node_id]; one_DCT = get_one_DCT(meminfo); @@ -824,54 +813,52 @@ hole_sizek = (4*1024*1024) - hole_startk; - for(ii=NODE_NUMS-1;ii>i;ii--) { + for(i=NODE_NUMS-1;i>node_id;i--) { - d = get_dram_base_mask(ii); + d = get_dram_base_mask(i); if(!(d.mask & 1)) continue; d.base -= (hole_sizek>>9); d.mask -= (hole_sizek>>9); - set_dram_base_mask(ii, d, sysconf.nodes); + set_dram_base_mask(i, d, sysconf.nodes); - if(get_DctSelHiEn(ii) & 1) { - sel_m = get_DctSelBaseAddr(ii); + if(get_DctSelHiEn(i) & 1) { + sel_m = get_DctSelBaseAddr(i); sel_m -= hole_startk>>10; - set_DctSelBaseAddr(ii, sel_m); + set_DctSelBaseAddr(i, sel_m); } } - d = get_dram_base_mask(i); - dev = __f1_dev[i]; - hoist = pci_read_config32(dev, 0xf0); - sel_hi_en = get_DctSelHiEn(i); + d = get_dram_base_mask(node_id); + dev = __f1_dev[node_id]; + sel_hi_en = get_DctSelHiEn(node_id); if(sel_hi_en & 1) { - sel_m = get_DctSelBaseAddr(i); + sel_m = get_DctSelBaseAddr(node_id); } - + hoist = pci_read_config32(dev, 0xf0); if(hoist & 1) { pci_write_config32(dev, 0xf0, 0); d.mask -= (hole_sizek>>9); - set_dram_base_mask(i, d, sysconf.nodes); + set_dram_base_mask(node_id, d, sysconf.nodes); if(one_DCT || (sel_m >= (hole_startk>>10))) { if(sel_hi_en & 1) { sel_m -= hole_startk>>10; - set_DctSelBaseAddr(i, sel_m); + set_DctSelBaseAddr(node_id, sel_m); } } if(sel_hi_en & 1) { - set_DctSelBaseOffset(i, 0); + set_DctSelBaseOffset(node_id, 0); } - } - else { + } else { d.base -= (hole_sizek>>9); d.mask -= (hole_sizek>>9); - set_dram_base_mask(i, d, sysconf.nodes); + set_dram_base_mask(node_id, d, sysconf.nodes); if(sel_hi_en & 1) { sel_m -= hole_startk>>10; - set_DctSelBaseAddr(i, sel_m); + set_DctSelBaseAddr(node_id, sel_m); } } @@ -885,7 +872,7 @@ extern uint64_t high_tables_base, high_tables_size; #endif -static void pci_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM == 1 struct resource *io, *mem1, *mem2; @@ -902,7 +889,7 @@ #if CONFIG_PCI_64BIT_PREF_MEM == 1 - for(link=0; link<dev->links; link++) { + for(link = 0; link < dev->links; link++) { /* Now reallocate the pci resources memory with the * highest addresses I can manage. */ @@ -946,16 +933,13 @@ for(res = &dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_ASSIGNED; - res->flags &= ~IORESOURCE_STORED; - link = (res>>2) & 3; res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); - } #endif pci_tolm = 0xffffffffUL; - for(link=0;link<dev->links; link++) { + for(link = 0; link<dev->links; link++) { pci_tolm = find_pci_tolm(&dev->link[link], pci_tolm); } @@ -967,7 +951,7 @@ // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M // MMIO hole. If you fix this here, please fix amdk8, too. - /* Round the mmio hold to 64M */ + /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1); #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1057,11 +1041,11 @@ idx += 0x10; sizek -= pre_sizek; #if CONFIG_WRITE_HIGH_TABLES==1 - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, "(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); } #endif @@ -1092,7 +1076,7 @@ #if CONFIG_WRITE_HIGH_TABLES==1 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (i==0 && high_tables_base==0) { + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; @@ -1130,7 +1114,7 @@ #endif - for(i=0;i<dev->links;i++) { + for(i = 0; i < dev->links; i++) { max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); } @@ -1138,7 +1122,7 @@ * Including enabling relaxed ordering if it is safe. */ get_fx_devs(); - for(i = 0; i < FX_DEVS; i++) { + for(i = 0; i < fx_devs; i++) { device_t f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { @@ -1160,7 +1144,7 @@ static struct device_operations pci_domain_ops = { .read_resources = amdfam10_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = amdfam10_domain_set_resources, .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = amdfam10_domain_scan_bus, @@ -1208,11 +1192,9 @@ } else { sysconf.lift_bsp_apicid = 1; } - } #endif #endif - } static u32 cpu_bus_scan(device_t dev, u32 max) @@ -1243,11 +1225,7 @@ get_option(&disable_siblings, "multi_core"); #endif - // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it - // still be 0) - // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? - // and differ d0 and e0 single core - + // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp??? nb_cfg_54 = read_nb_cfg_54(); #if CONFIG_CBB @@ -1264,7 +1242,6 @@ printk(BIOS_DEBUG, " but it is not under pci_domain directly "); } printk(BIOS_DEBUG, "\n"); - } dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if(!dev_mc) { @@ -1342,9 +1319,9 @@ cdb_dev = pci_probe_dev(NULL, pbus, PCI_DEVFN(devn, fn)); } - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); } - if(cdb_dev) { + if (cdb_dev) { /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ @@ -1355,7 +1332,7 @@ #else linknum = 4; #endif - if(cdb_dev->links < linknum) { + if (cdb_dev->links < linknum) { for(link=cdb_dev->links; link<linknum; link++) { cdb_dev->link[link].link = link; cdb_dev->link[link].dev = cdb_dev; @@ -1412,14 +1389,14 @@ cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0) - if(sysconf.enabled_apic_ext_id) { + if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { cpu->path.apic.apic_id += sysconf.apicid_offset; } else { if (cpu->path.apic.apic_id != 0) cpu->path.apic.apic_id += sysconf.apicid_offset; - } + } } #endif printk(BIOS_DEBUG, "CPU: %s %s\n", @@ -1431,18 +1408,15 @@ return max; } - static void cpu_bus_init(device_t dev) { initialize_cpus(&dev->link[0]); } - static void cpu_bus_noop(device_t dev) { } - static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, @@ -1451,7 +1425,6 @@ .scan_bus = cpu_bus_scan, }; - static void root_complex_enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Wed Jun 9 21:07:19 2010 (r5624) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Thu Jun 10 00:39:00 2010 (r5625) @@ -55,17 +55,17 @@ } } -static uint32_t f1_read_config32(unsigned reg) +static u32 f1_read_config32(unsigned reg) { - if ( fx_devs == 0) + if (fx_devs == 0) get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); } -static void f1_write_config32(unsigned reg, uint32_t value) +static void f1_write_config32(unsigned reg, u32 value) { int i; - if ( fx_devs == 0) + if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { device_t dev; @@ -76,22 +76,23 @@ } } -static unsigned int amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(device_t dev) { return (dev->path.pci.devfn >> 3) - 0x18; } -static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) +static u32 amdk8_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, + u32 max, u32 offset_unitid) { - uint32_t link_type; + u32 link_type; int i; - uint32_t busses, config_busses; - unsigned free_reg, config_reg; - unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain - unsigned max_bus; - unsigned min_bus; - unsigned max_devfn; + u32 busses, config_busses; + u32 free_reg, config_reg; + u32 ht_unitid_base[4]; // here assume only 4 HT device on chain + u32 max_bus; + u32 min_bus; + u32 max_devfn; dev->link[link].cap = 0x80 + (link *0x20); do { @@ -111,7 +112,7 @@ */ free_reg = 0; for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { - uint32_t config; + u32 config; config = f1_read_config32(config_reg); if (!free_reg && ((config & 3) == 0)) { free_reg = config_reg; @@ -150,7 +151,7 @@ max = min_bus; #else //other ... - else { + else { min_bus = ++max; } #endif @@ -214,9 +215,9 @@ f1_write_config32(config_reg, config_busses); { - // config config_reg, and ht_unitid_base to update hcdn_reg; + // use config_reg and ht_unitid_base to update hcdn_reg int index; - unsigned temp = 0; + u32 temp = 0; index = (config_reg-0xe0) >> 2; for(i=0;i<4;i++) { temp |= (ht_unitid_base[i] & 0xff) << (i*8); @@ -225,16 +226,16 @@ sysconf.hcdn_reg[index] = temp; } - return max; } -static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) +static unsigned amdk8_scan_chains(device_t dev, unsigned max) { unsigned nodeid; unsigned link; unsigned sblink = 0; unsigned offset_unitid = 0; + nodeid = amdk8_nodeid(dev); if(nodeid==0) { @@ -247,7 +248,7 @@ #endif } - for(link = 0; link < dev->links; link++) { + for (link = 0; link < dev->links; link++) { #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif @@ -261,16 +262,15 @@ max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); } - return max; } -static int reg_useable(unsigned reg, - device_t goal_dev, unsigned goal_nodeid, unsigned goal_link) +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) { struct resource *res; - unsigned nodeid, link=0; + unsigned nodeid, link = 0; int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { @@ -291,7 +291,6 @@ result = 1; } } - return result; } @@ -351,10 +350,10 @@ /* Initialize the prefetchable memory constraints on the current bus */ resource = new_resource(dev, IOINDEX(2, link)); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags |= IORESOURCE_BRIDGE; @@ -363,10 +362,10 @@ /* Initialize the memory constraints on the current bus */ resource = new_resource(dev, IOINDEX(1, link)); if (resource) { - resource->base = 0; - resource->size = 0; + resource->base = 0; + resource->size = 0; resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; } @@ -430,7 +429,7 @@ link = IOINDEX_LINK(resource->index); if (resource->flags & IORESOURCE_IO) { - uint32_t base, limit; + u32 base, limit; base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); base &= 0xfe000fcc; @@ -454,7 +453,7 @@ f1_write_config32(reg, base); } else if (resource->flags & IORESOURCE_MEM) { - uint32_t base, limit; + u32 base, limit; base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x4); base &= 0x000000f0; @@ -468,7 +467,7 @@ f1_write_config32(reg, base); } resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %d link %d>", + sprintf(buf, " <node %x link %x>", nodeid, link); report_resource_stored(dev, resource, buf); } @@ -580,18 +579,18 @@ } static struct device_operations northbridge_operations = { - .read_resources = amdk8_read_resources, - .set_resources = amdk8_set_resources, + .read_resources = amdk8_read_resources, + .set_resources = amdk8_set_resources, .enable_resources = amdk8_enable_resources, - .init = mcf0_control_init, - .scan_bus = amdk8_scan_chains, - .enable = 0, - .ops_pci = 0, + .init = mcf0_control_init, + .scan_bus = amdk8_scan_chains, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver mcf0_driver __pci_driver = { - .ops = &northbridge_operations, + .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1100, }; @@ -608,20 +607,20 @@ /* Find the already assigned resource pairs */ get_fx_devs(); for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { - uint32_t base, limit; + u32 base, limit; base = f1_read_config32(reg); limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned nodeid, link; + unsigned nodeid, reg_link; device_t reg_dev; nodeid = limit & 7; - link = (limit >> 4) & 3; + reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; if (reg_dev) { /* Reserve the resource */ struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x100 + reg, link)); + res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link)); if (res) { res->base = base; res->limit = limit; @@ -650,8 +649,8 @@ return; } resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } @@ -668,10 +667,10 @@ *best_p = best; } -static uint32_t find_pci_tolm(struct bus *bus) +static u32 find_pci_tolm(struct bus *bus) { struct resource *min; - uint32_t tolm; + u32 tolm; min = 0; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); tolm = 0xffffffffUL; @@ -697,8 +696,8 @@ mem_hole.node_id = -1; for (i = 0; i < fx_devs; i++) { - uint32_t base; - uint32_t hole; + u32 base; + u32 hole; base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -714,9 +713,9 @@ //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk if(mem_hole.node_id==-1) { - uint32_t limitk_pri = 0; + u32 limitk_pri = 0; for(i=0; i<8; i++) { - uint32_t base, limit; + u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -735,18 +734,16 @@ limitk_pri = limit_k; } } - return mem_hole; - } static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; device_t dev; - uint32_t base, limit; - uint32_t hoist; - uint32_t hole_sizek; + u32 base, limit; + u32 hoist; + u32 hole_sizek; //1. find which node has hole @@ -776,22 +773,22 @@ return; } hoist = pci_read_config32(dev, 0xf0); - if(hoist & 1) + if(hoist & 1) { pci_write_config32(dev, 0xf0, 0); - else { + } else { base = pci_read_config32(dev, 0x40 + (node_id << 3)); f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2)); } } -static uint32_t hoist_memory(unsigned long hole_startk, int node_id) +static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; - uint32_t carry_over; + u32 carry_over; device_t dev; - uint32_t base, limit; - uint32_t basek; - uint32_t hoist; + u32 base, limit; + u32 basek; + u32 hoist; carry_over = (4*1024*1024) - hole_startk; @@ -848,11 +845,11 @@ struct resource *res; #endif unsigned long mmio_basek; - uint32_t pci_tolm; + u32 pci_tolm; int i, idx; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - unsigned reset_memhole = 1; + u32 reset_memhole = 1; #endif #if 0 @@ -909,7 +906,6 @@ res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); - } #endif @@ -953,10 +949,10 @@ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some - uint32_t basek_pri; + u32 basek_pri; for (i = 0; i < fx_devs; i++) { - uint32_t base; - uint32_t basek; + u32 base; + u32 basek; base = f1_read_config32(0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; @@ -980,8 +976,8 @@ idx = 0x10; for(i = 0; i < fx_devs; i++) { - uint32_t base, limit; - unsigned basek, limitk, sizek; + u32 base, limit; + u32 basek, limitk, sizek; base = f1_read_config32(0x40 + (i << 3)); limit = f1_read_config32(0x44 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -1074,9 +1070,9 @@ } -static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max) +static u32 amdk8_domain_scan_bus(device_t dev, u32 max) { - unsigned reg; + u32 reg; int i; /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { @@ -1092,7 +1088,7 @@ device_t f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { - uint32_t httc; + u32 httc; httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); httc &= ~HTTC_RSP_PASS_PW; if (!dev->link[0].disable_relaxed_ordering) { @@ -1109,15 +1105,15 @@ } static struct device_operations pci_domain_ops = { - .read_resources = amdk8_domain_read_resources, - .set_resources = amdk8_domain_set_resources, + .read_resources = amdk8_domain_read_resources, + .set_resources = amdk8_domain_set_resources, .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = amdk8_domain_scan_bus, - .ops_pci_bus = &pci_cf8_conf1, + .init = 0, + .scan_bus = amdk8_domain_scan_bus, + .ops_pci_bus = &pci_cf8_conf1, }; -static unsigned int cpu_bus_scan(device_t dev, unsigned int max) +static u32 cpu_bus_scan(device_t dev, u32 max) { struct bus *cpu_bus; device_t dev_mc; @@ -1142,9 +1138,9 @@ get_option(&disable_siblings, "multi_core"); #endif - // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) - // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core - + // for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0) + // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp??? + // and differ d0 and e0 single core nb_cfg_54 = read_nb_cfg_54(); dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); @@ -1197,7 +1193,6 @@ dev_f0->link[local_j].dev = dev_f0; } } - } e0_later_single_core = 0; @@ -1236,7 +1231,7 @@ } } - unsigned jj; + u32 jj; if(e0_later_single_core || disable_siblings) { jj = 0; } else @@ -1280,8 +1275,8 @@ cpu->path.apic.apic_id += sysconf.apicid_offset; } else { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; + if (cpu->path.apic.apic_id != 0) + cpu->path.apic.apic_id += sysconf.apicid_offset; } } printk(BIOS_DEBUG, "CPU: %s %s\n", @@ -1303,11 +1298,11 @@ } static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev)

1 0

ectool: Add support to extended commands
by Антон Кочков 10 Jun '10

10 Jun '10

Add support to extended EC series Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> ---

2 1

superiotool: Add support to IT85xx series
by Антон Кочков 10 Jun '10

10 Jun '10

Add support to IT85xx series Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> ---

2 1

Minor update on IDE mode on Wyse S10 (CS5536)
by Oliver Schinagl 09 Jun '10

09 Jun '10

I built a 2.6.24.7 kernel almost exactly to Nils his config, had to change some things like USB storage as my main boot medium, and it worked. I think the generic IDE driver loads up, still says 'IDE disabled' but then probes for hdb en hda. hda actually is a Transcend IDE disk (Compact Flash sort of IDE disk, but still). hdparm -tT reports a whopping 1.87mb/s and I can't enable DMA, operation not permitted, suggesting the chipset driver is missing, which I belive is compiled in. The more interesting part though is, that I was able to install partitions, grub and actually am booting and running with said 2.6.24.7 kernel and openwrt distro! I attached a new lspci -vvvxxx output, which shows slightly different IDE timings. In any case, I went trough the CS5536 documentation and also found MSR stuff about enabling the IDE port (or hooking it to flash chips directly) and that there where certain 'balls' that also setup the board a certain way. After checking the pinout of the CS5536 and using the very handy msrutil I found the IDE port is actually connected in IDE mode, and why the bios lists stupid notions about the port being disabled baffles me. I am now ready I think to start giving coreboot a whirl on this thing. Though I still wonder, if the bios can boot the kernel from the IDE 'drive', I assume coreboot will equally be able to boot it; but if recent kernels refuse to use the disk, I may end up being screwed anyway :S. Well I could always make a big initrd I suppose with everything in it ... Sorry for ranting on this list :p Oliver

1 0

[commit] r5624 - in trunk/src/southbridge: amd/cs5530 via/vt8231 via/vt8235
by repository service 09 Jun '10

09 Jun '10

Author: stepan Date: Wed Jun 9 21:07:19 2010 New Revision: 5624 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5624 Log: The interrupt controller lives at I/O 0x4d0/0x4d1. However on these platforms we were causing a resource conflict by letting the resource allocator start allocations at 0x400. Change the constraints to start at 0x1000 so we avoid allocating over LPT ports (0x778-0x77f), PCI (0xcf8-0xcff) and some other fixed resources that might live down there (smbus base, acpi base,...) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/southbridge/amd/cs5530/cs5530_isa.c trunk/src/southbridge/via/vt8231/vt8231_lpc.c trunk/src/southbridge/via/vt8235/vt8235_lpc.c Modified: trunk/src/southbridge/amd/cs5530/cs5530_isa.c ============================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530_isa.c Wed Jun 9 10:08:12 2010 (r5623) +++ trunk/src/southbridge/amd/cs5530/cs5530_isa.c Wed Jun 9 21:07:19 2010 (r5624) @@ -33,7 +33,7 @@ res = new_resource(dev, 1); res->base = 0x0UL; - res->size = 0x400UL; + res->size = 0x1000UL; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_lpc.c Wed Jun 9 10:08:12 2010 (r5623) +++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c Wed Jun 9 21:07:19 2010 (r5624) @@ -136,7 +136,7 @@ res = new_resource(dev, 1); res->base = 0x0UL; - res->size = 0x400UL; + res->size = 0x1000UL; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; Modified: trunk/src/southbridge/via/vt8235/vt8235_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_lpc.c Wed Jun 9 10:08:12 2010 (r5623) +++ trunk/src/southbridge/via/vt8235/vt8235_lpc.c Wed Jun 9 21:07:19 2010 (r5624) @@ -110,7 +110,7 @@ // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); - // Set ACPI base address to IO 0x4000 + // Set ACPI base address to IO 0x400 pci_write_config16(dev, 0x88, 0x0401); // set ACPI irq to 5 @@ -223,7 +223,7 @@ res = new_resource(dev, 1); res->base = 0x0UL; - res->size = 0x400UL; + res->size = 0x1000UL; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

1 0

Re PATCH: ECS P6IWP-Fe
by anders＠jenbo.dk 09 Jun '10

09 Jun '10

Agreed, the only reason I haven't done car yet is that I haven't had a board where the best match to copy from used CAR. I defiantly hav plans for updating all the boards I have to car but I am waiting til I hit a board where car is the best match or I run out if board / easy targets. By then I might help out with porting the 440bx boards (is 440lx below?). Mvh Anders ----- Reply message ----- Fra: "Joseph Smith" <joe(a)settoplinux.org> Dato: ons., jun. 9, 2010 14:44 Emne: [coreboot] PATCH: ECS P6IWP-Fe Til: <coreboot(a)coreboot.org> Cc: "Stefan Reinauer" <stefan.reinauer(a)coresystems.de> On Wed, 09 Jun 2010 07:16:48 -0400, Joseph Smith <joe(a)settoplinux.org> wrote: > > > > On Wed, 9 Jun 2010 13:00:26 +0200, Stefan Reinauer > <stefan.reinauer(a)coresystems.de> wrote: >> >> On 09.06.2010, at 12:47, Joseph Smith <joe(a)settoplinux.org> wrote: >> >>> >>> >>> >>> On Wed, 09 Jun 2010 10:09:21 +0200, Stefan Reinauer >> <stepan(a)coresystems.de >>> > >>> wrote: >>>> On 6/9/10 1:57 AM, Anders Jenbo wrote: >>>>> This patch adds the ECS P6IWP-Fe board to coreboot. >>>>> >>>>> Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> >>>> >>>> Thanks a lot! >>>> >>>> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> >>>> and checked in as r5623 >>>> >>>> But please add a license header to the device tree as well in an >>>> extra >>>> patch.. >>>> >>> Yes thanks Anders :-) >>> One more suggestion. I think from this point forward there is really >>> no >>> excuse for any Intel 440bx and up to be using romcc. I feel there >>> should be >>> a new rule, any new boards 440bx and up need to be running CAR for a >>> Ack. >>> Other wise that will be just one more board to back paddle to CAR. >>> Anyone >>> else have a thought on this? >>> >> >> Since people always copy from existing boards and keep changing them >> until it works, a patch that moves all existing 440 boards to CAR >> would most likely solve the problem better than a rule. Want to give >> it a try? >> > I could but not sure how much sense that would make considering I do not > have a 440bx to test.... > > On the other hand I do have some i810's, That chip I would be glad to > convert :-) > Yes, this is going to be a new side project. Hey maybe a i815 port will even come out of it :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

Indtast Bcc PATCH: ECS P6IWP-Fe
by anders＠jenbo.dk 09 Jun '10

09 Jun '10

Oh ok, was not aware that that was possible. Mvh Anders ----- Reply message ----- Fra: "Stefan Reinauer" <stepan(a)coresystems.de> Dato: ons., jun. 9, 2010 10:09 Emne: [coreboot] PATCH: ECS P6IWP-Fe Til: <coreboot(a)coreboot.org> On 6/9/10 1:57 AM, Anders Jenbo wrote: > This patch adds the ECS P6IWP-Fe board to coreboot. > > Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> Thanks a lot! Acked-by: Stefan Reinauer <stepan(a)coresystems.de> and checked in as r5623 But please add a license header to the device tree as well in an extra patch.. Stefan -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

PATCH: Porting v3-style Geode LX cpu init to v4
by Edwin Beasant 09 Jun '10

09 Jun '10

This patch moves the GLCP Delay control register calculation and cpuInit functions over from v3 into v4. This fixes a bug whereby boards that use terminated DRAM and manual PLL configuration fail to set a correct GLCP_DELAY_CONTROL. This also imports a v3 style msrinit_t structure into the msr.h. Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> --- Edwin Beasant

1 0

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coreboot June 2010