coreboot June 2010

coreboot@coreboot.org

60 participants
222 discussions

Booting UHCI with FILO
by Joseph Smith 08 Jun '10

08 Jun '10

Hello, Trying to boot Fedora 12 Live USB. FILO loads the Kernel just fine and then Loads the initrd just fine. Then: Jumping to entry point... Out of memory while allocating output buffer -- System halted Any Ideas? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

4 8

[PATCH] Wyse S50 RAMBASE 0x100000 fix
by Nils 08 Jun '10

08 Jun '10

This patch fixes RAMBASE 0x100000 for Wyse S50. I think that the problem was that extended memory was not setup early enough. This patch is boot tested on r5621. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> And now with patch attached,sorry. Thanks,Nils.

3 2

[commit] r5622 - trunk/src/northbridge/amd/gx2
by repository service 08 Jun '10

08 Jun '10

Author: oxygene Date: Tue Jun 8 07:57:05 2010 New Revision: 5622 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5622 Log: Fix auto-mangled comments (trivial) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Mon Jun 7 22:15:54 2010 (r5621) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Tue Jun 8 07:57:05 2010 (r5622) @@ -37,9 +37,9 @@ {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/ {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/ + {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ + {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ + {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/ {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},

1 0

[PATCH] Wyse S50 RAMBASE 0x100000 fix
by Nils 08 Jun '10

08 Jun '10

1 0

[commit] r5621 - in trunk/src: drivers drivers/dec drivers/ti include/device mainboard/nokia/ip530 southbridge southbridge/dec southbridge/dec/21143 southbridge/ti southbridge/ti/pci1x2x
by repository service 07 Jun '10

07 Jun '10

Author: myles Date: Mon Jun 7 22:15:54 2010 New Revision: 5621 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5621 Log: Fix some of Peter's suggestions for the Nokia IP530. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/src/southbridge/dec/ trunk/src/southbridge/dec/21143/ (props changed) - copied from r5619, trunk/src/drivers/dec/21143/ trunk/src/southbridge/dec/21143/21143.c (contents, props changed) - copied, changed from r5619, trunk/src/drivers/dec/21143/21143pd.c trunk/src/southbridge/dec/21143/Kconfig trunk/src/southbridge/dec/Kconfig trunk/src/southbridge/dec/Makefile.inc trunk/src/southbridge/ti/pci1x2x/ trunk/src/southbridge/ti/pci1x2x/Kconfig trunk/src/southbridge/ti/pci1x2x/Makefile.inc (contents, props changed) - copied, changed from r5619, trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc trunk/src/southbridge/ti/pci1x2x/pci1x2x.c (contents, props changed) - copied, changed from r5619, trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c Deleted: trunk/src/drivers/dec/ trunk/src/drivers/ti/ trunk/src/southbridge/dec/21143/21143pd.c Modified: trunk/src/drivers/Kconfig trunk/src/include/device/pci_ids.h trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/southbridge/Kconfig trunk/src/southbridge/Makefile.inc trunk/src/southbridge/dec/21143/Makefile.inc trunk/src/southbridge/ti/Kconfig trunk/src/southbridge/ti/Makefile.inc Modified: trunk/src/drivers/Kconfig ============================================================================== --- trunk/src/drivers/Kconfig Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/drivers/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -23,21 +23,3 @@ help It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it. - -config DRIVERS_TI - bool - -config DRIVERS_TI_PCI1225 - select DRIVERS_TI - bool - -config DRIVERS_TI_PCI1420 - select DRIVERS_TI - bool - -config DRIVERS_TI_PCI1520 - select DRIVERS_TI - bool - -config DRIVERS_DEC_21143PD - bool Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/include/device/pci_ids.h Mon Jun 7 22:15:54 2010 (r5621) @@ -696,7 +696,7 @@ #define PCI_DEVICE_ID_TI_4410 0xac41 #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 -#define PCI_DEVICE_ID_TI_1520 0xAC55 +#define PCI_DEVICE_ID_TI_1520 0xac55 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 @@ -1742,9 +1742,9 @@ #define PCI_DEVICE_ID_CCD_B00C 0xb00c #define PCI_DEVICE_ID_CCD_B100 0xb100 -#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy -#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications -#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications +#define PCI_VENDOR_ID_NOKIA 0x13B8 +#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 +#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 #define PCI_VENDOR_ID_3WARE 0x13C1 #define PCI_DEVICE_ID_3WARE_1000 0x1000 Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/mainboard/nokia/ip530/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -24,8 +24,8 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO - select DRIVERS_TI_PCI1225 - select DRIVERS_DEC_21143PD + select SOUTHBRIDGE_TI_PCI1X2X + select SOUTHBRIDGE_DEC_21143 select BOARD_ROMSIZE_KB_256 select ROMCC select PIRQ_ROUTE Modified: trunk/src/southbridge/Kconfig ============================================================================== --- trunk/src/southbridge/Kconfig Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/southbridge/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -1,5 +1,6 @@ source src/southbridge/amd/Kconfig source src/southbridge/broadcom/Kconfig +source src/southbridge/dec/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig source src/southbridge/ricoh/Kconfig Modified: trunk/src/southbridge/Makefile.inc ============================================================================== --- trunk/src/southbridge/Makefile.inc Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/southbridge/Makefile.inc Mon Jun 7 22:15:54 2010 (r5621) @@ -1,5 +1,6 @@ subdirs-y += amd subdirs-y += broadcom +subdirs-y += dec subdirs-y += intel subdirs-y += nvidia subdirs-y += ricoh Copied and modified: trunk/src/southbridge/dec/21143/21143.c (from r5619, trunk/src/drivers/dec/21143/21143pd.c) ============================================================================== --- trunk/src/drivers/dec/21143/21143pd.c Mon Jun 7 18:51:11 2010 (r5619, copy source) +++ trunk/src/southbridge/dec/21143/21143.c Mon Jun 7 22:15:54 2010 (r5621) @@ -40,9 +40,9 @@ /** * This driver take the values from Kconfig and load them in the registers */ -static void dec_21143pd_enable( device_t dev ) +static void dec_21143_enable( device_t dev ) { - printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n"); + printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n"); // Command and Status Configuration Register (Offset 0x04) pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); @@ -55,16 +55,16 @@ return; } -static struct device_operations dec_21143pd_ops = { +static struct device_operations dec_21143_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = dec_21143pd_enable, + .init = dec_21143_enable, .scan_bus = 0, }; -static const struct pci_driver dec_21143pd_driver __pci_driver = { - .ops = &dec_21143pd_ops, +static const struct pci_driver dec_21143_driver __pci_driver = { + .ops = &dec_21143_ops, .vendor = PCI_VENDOR_ID_DEC, .device = PCI_DEVICE_ID_DEC_21142, }; Added: trunk/src/southbridge/dec/21143/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/dec/21143/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -0,0 +1,2 @@ +config SOUTHBRIDGE_DEC_21143 + bool Modified: trunk/src/southbridge/dec/21143/Makefile.inc ============================================================================== --- trunk/src/drivers/dec/21143/Makefile.inc Mon Jun 7 18:51:11 2010 (r5619) +++ trunk/src/southbridge/dec/21143/Makefile.inc Mon Jun 7 22:15:54 2010 (r5621) @@ -1,2 +1,2 @@ -driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o +driver-y += 21143.o Added: trunk/src/southbridge/dec/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/dec/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -0,0 +1 @@ +source src/southbridge/dec/21143/Kconfig Added: trunk/src/southbridge/dec/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/dec/Makefile.inc Mon Jun 7 22:15:54 2010 (r5621) @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_DEC_21143) += 21143 Modified: trunk/src/southbridge/ti/Kconfig ============================================================================== --- trunk/src/southbridge/ti/Kconfig Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/southbridge/ti/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -19,3 +19,4 @@ source src/southbridge/ti/pci7420/Kconfig source src/southbridge/ti/pcixx12/Kconfig +source src/southbridge/ti/pci1x2x/Kconfig Modified: trunk/src/southbridge/ti/Makefile.inc ============================================================================== --- trunk/src/southbridge/ti/Makefile.inc Mon Jun 7 19:12:57 2010 (r5620) +++ trunk/src/southbridge/ti/Makefile.inc Mon Jun 7 22:15:54 2010 (r5621) @@ -19,3 +19,4 @@ subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12 +subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x Added: trunk/src/southbridge/ti/pci1x2x/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/ti/pci1x2x/Kconfig Mon Jun 7 22:15:54 2010 (r5621) @@ -0,0 +1,2 @@ +config SOUTHBRIDGE_TI_PCI1X2X + bool Copied and modified: trunk/src/southbridge/ti/pci1x2x/Makefile.inc (from r5619, trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc) ============================================================================== --- trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc Mon Jun 7 18:51:11 2010 (r5619, copy source) +++ trunk/src/southbridge/ti/pci1x2x/Makefile.inc Mon Jun 7 22:15:54 2010 (r5621) @@ -1,2 +1 @@ -driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o - +driver-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.o Copied and modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c (from r5619, trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c) ============================================================================== --- trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c Mon Jun 7 18:51:11 2010 (r5619, copy source) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Mon Jun 7 22:15:54 2010 (r5621) @@ -65,27 +65,20 @@ .scan_bus = 0, }; -#ifdef CONFIG_DRIVERS_TI_PCI1225 static const struct pci_driver ti_pci1225_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, }; -#endif -#ifdef CONFIG_DRIVERS_TI_PCI1420 static const struct pci_driver ti_pci1420_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; -#endif -#ifdef CONFIG_DRIVERS_TI_PCI1520 + static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &ti_pci1x2y_ops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; -#endif - -

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[commit] r5609 - in trunk/src: drivers drivers/dec drivers/dec/21143 drivers/ti drivers/ti/pcmcia-cardbus include/device mainboard/nokia/ip530
by repository service 07 Jun '10

07 Jun '10

Author: myles Date: Fri Jun 4 21:53:55 2010 New Revision: 5609 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5609 Log: Fixes for Nokia IP530 and associated drivers. Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Marc Bertens <mbertens(a)xs4all.nl> Added: trunk/src/drivers/dec/ trunk/src/drivers/dec/21143/ trunk/src/drivers/dec/21143/21143pd.c trunk/src/drivers/dec/21143/Makefile.inc trunk/src/drivers/ti/ trunk/src/drivers/ti/pcmcia-cardbus/ trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c Modified: trunk/src/drivers/Kconfig trunk/src/drivers/Makefile.inc trunk/src/include/device/pci_ids.h trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/mainboard/nokia/ip530/irq_tables.c trunk/src/mainboard/nokia/ip530/mainboard.c Modified: trunk/src/drivers/Kconfig ============================================================================== --- trunk/src/drivers/Kconfig Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/drivers/Kconfig Fri Jun 4 21:53:55 2010 (r5609) @@ -23,3 +23,21 @@ help It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it. + +config DRIVERS_TI + bool + +config DRIVERS_TI_PCI1225 + select DRIVERS_TI + bool + +config DRIVERS_TI_PCI1420 + select DRIVERS_TI + bool + +config DRIVERS_TI_PCI1520 + select DRIVERS_TI + bool + +config DRIVERS_DEC_21143PD + bool Modified: trunk/src/drivers/Makefile.inc ============================================================================== --- trunk/src/drivers/Makefile.inc Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/drivers/Makefile.inc Fri Jun 4 21:53:55 2010 (r5609) @@ -1,3 +1,5 @@ subdirs-y += generic/debug subdirs-y += ati/ragexl subdirs-y += sil/3114 +subdirs-y += ti/pcmcia-cardbus +subdirs-y += dec/21143 Added: trunk/src/drivers/dec/21143/21143pd.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/dec/21143/21143pd.c Fri Jun 4 21:53:55 2010 (r5609) @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> + +/** + * The following should be set in the mainboard-specific Kconfig file. + */ +#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \ + !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \ + !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION)) +#error "you must supply these values in your mainboard-specific Kconfig file" +#endif + +/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */ +/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */ +/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */ + +/** + * This driver take the values from Kconfig and load them in the registers + */ +static void dec_21143pd_enable( device_t dev ) +{ + printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n"); + // Command and Status Configuration Register (Offset 0x04) + pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION ); + printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) ); + // Cache Line Size Register (Offset 0x0C) + pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE ); + printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) ); + // Expansion ROM Base Address Register (Offset 0x30) + pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS ); + printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) ); + return; +} + +static struct device_operations dec_21143pd_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = dec_21143pd_enable, + .scan_bus = 0, +}; + +static const struct pci_driver dec_21143pd_driver __pci_driver = { + .ops = &dec_21143pd_ops, + .vendor = PCI_VENDOR_ID_DEC, + .device = PCI_DEVICE_ID_DEC_21142, +}; Added: trunk/src/drivers/dec/21143/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/dec/21143/Makefile.inc Fri Jun 4 21:53:55 2010 (r5609) @@ -0,0 +1,2 @@ +driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o + Added: trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/ti/pcmcia-cardbus/Makefile.inc Fri Jun 4 21:53:55 2010 (r5609) @@ -0,0 +1,2 @@ +driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o + Added: trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c Fri Jun 4 21:53:55 2010 (r5609) @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <console/console.h> + +#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \ + !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \ + !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \ + !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \ + !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \ + !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) ) +#error "you must supply these values in your mainboard-specific Kconfig file" +#endif + +static void ti_pci1x2y_init(struct device *dev) +{ + printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n"); + // Command register (offset 04) + pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR ); + // Cache Line Size Register (offset 0x0C) + pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR ); + // CardBus latency timer register (offset 1B) + pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR ); + // Bridge control register (offset 3E) + pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR ); + /** Enable change sub-vendor id + * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */ + pci_write_config32( dev, 0x80, 0x10 ); + pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA ); + // Now write the correct value for SCR + // System Control Register (offset 0x80) + pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR ); + // Multifunction routing register + pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR ); + // Set Device Control Register (0x92) accordingly + pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 ); + return; +} + +static struct device_operations ti_pci1x2y_ops = { + .read_resources = NULL, //pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ti_pci1x2y_init, + .scan_bus = 0, +}; + +#ifdef CONFIG_DRIVERS_TI_PCI1225 +static const struct pci_driver ti_pci1225_driver __pci_driver = { + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1225, +}; + +#endif +#ifdef CONFIG_DRIVERS_TI_PCI1420 +static const struct pci_driver ti_pci1420_driver __pci_driver = { + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1420, +}; +#endif +#ifdef CONFIG_DRIVERS_TI_PCI1520 +static const struct pci_driver ti_pci1520_driver __pci_driver = { + .ops = &ti_pci1x2y_ops, + .vendor = PCI_VENDOR_ID_TI, + .device = PCI_DEVICE_ID_TI_1420, +}; +#endif + + Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/include/device/pci_ids.h Fri Jun 4 21:53:55 2010 (r5609) @@ -696,6 +696,7 @@ #define PCI_DEVICE_ID_TI_4410 0xac41 #define PCI_DEVICE_ID_TI_4451 0xac42 #define PCI_DEVICE_ID_TI_1420 0xac51 +#define PCI_DEVICE_ID_TI_1520 0xAC55 #define PCI_VENDOR_ID_SONY 0x104d #define PCI_DEVICE_ID_SONY_CXD3222 0x8039 @@ -1741,6 +1742,10 @@ #define PCI_DEVICE_ID_CCD_B00C 0xb00c #define PCI_DEVICE_ID_CCD_B100 0xb100 +#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy +#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications +#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications + #define PCI_VENDOR_ID_3WARE 0x13C1 #define PCI_DEVICE_ID_3WARE_1000 0x1000 Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/mainboard/nokia/ip530/Kconfig Fri Jun 4 21:53:55 2010 (r5609) @@ -24,10 +24,12 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO + select DRIVERS_TI_PCI1225 + select DRIVERS_DEC_21143PD select ROMCC + select PIRQ_ROUTE select HAVE_PIRQ_TABLE select UDELAY_TSC - select BOARD_ROMSIZE_KB_256 config MAINBOARD_DIR string @@ -46,6 +48,52 @@ config IRQ_SLOT_COUNT int - default 6 + default 22 depends on BOARD_NOKIA_IP530 +## Configuration items for the ethernet adaptors +config DEC21143_CACHE_LINE_SIZE + int + default 0x00000000 + depends on BOARD_NOKIA_IP530 + +config DEC21143_EXPANSION_ROM_BASE_ADDRESS + hex + default 0x00000000 + depends on BOARD_NOKIA_IP530 + +config DEC21143_COMMAND_AND_STATUS_CONFIGURATION + hex + default 0x02800107 + depends on BOARD_NOKIA_IP530 + +## Configuration for the PCMCIA-Cardbus controller. +config TI_PCMCIA_CARDBUS_CMDR + hex + default 0x0107 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_CLSR + hex + default 0x00 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_CLTR + hex + default 0x40 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_BCR + hex + default 0x07C0 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_SCR + hex + default 0x08449060 + depends on BOARD_NOKIA_IP530 + +config TI_PCMCIA_CARDBUS_MRR + hex + default 0x00007522 + depends on BOARD_NOKIA_IP530 Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Fri Jun 4 21:53:55 2010 (r5609) @@ -30,16 +30,8 @@ chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end + device pnp 3f0.0 off end # Floppy (No connector) + device pnp 3f0.3 off end # Parallel port (No connector) device pnp 3f0.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -48,47 +40,23 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.9 on # Game port - io 0x60 = 0x201 - end - device pnp 3f0.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 3f0.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end + device pnp 3f0.7 on end # PS/2 keyboard / mouse + device pnp 3f0.6 on end # RTC + device pnp 3f0.8 on end # AUX I/O + device pnp 3f0.A off end # ACPI (No support yet) end end device pci 7.1 on end # IDE - device pci 7.2 on end # USB - device pci 7.3 on end # ACPI + device pci 7.2 off end # USB (No connector) + device pci 7.3 off end # ACPI (No support yet) register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" + # Disable UDMA/33 for lower speed if your IDE device(s) don't support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" end - device pci 0d.0 on end # NIC (DEC DECchip 21142/43) - device pci 0e.0 on end # NIC (DEC DECchip 21142/43) - device pci 0f.0 on end # CardBus bridge (TI PCI1225) - device pci 0f.1 on end # CardBus bridge (TI PCI1225) - end - device pci_domain 1 on # PCI domain 1 - device pci 00.0 on end # PCI bridge (DEC DECchip 21150) - end - device pci_domain 2 on # PCI domain 2 - device pci 04.0 on end # NIC (DECchip 21142/43) - device pci 04.0 on end # NIC (DECchip 21142/43) end end - Modified: trunk/src/mainboard/nokia/ip530/irq_tables.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/irq_tables.c Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/mainboard/nokia/ip530/irq_tables.c Fri Jun 4 21:53:55 2010 (r5609) @@ -31,15 +31,46 @@ 0x122e, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x36, /* Checksum */ + 0x44, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0}, - {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0}, - {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0}, - {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, + /** + * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller. + */ + // Southbridge 82371 + { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, + // On-board PCI-to-PCI bridge + { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 }, + // ETH1 on front panel + { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH2 on front panel + { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH3 on front panel + { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // ETH4 on front panel + { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // PCMCIA/Cardbus controller + { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 }, + // Bridge for slot 1 (top) + { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 1 (top) + { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 }, + { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 }, + { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 }, + { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 }, + // Bridge for slot 2 (middle) + { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 2 (middle) + { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 }, + { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 }, + { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 }, + { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 }, + // Bridge for slot 3 (bottom) + { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 }, + // PCI compact slots 3 (bottom) + { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 }, + { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 }, + { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 }, + { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 }, } }; @@ -47,3 +78,13 @@ { return copy_pirq_routing_table(addr); } + +/** + * TODO: This stub function is here until the point is solved in the + * main code of coreboot. see also arch/i386/boot/pirq_tables.c + */ +void pirq_assign_irqs(const unsigned char pIntAtoD[4]) +{ + return; +} + Modified: trunk/src/mainboard/nokia/ip530/mainboard.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/mainboard.c Fri Jun 4 17:55:12 2010 (r5608) +++ trunk/src/mainboard/nokia/ip530/mainboard.c Fri Jun 4 21:53:55 2010 (r5609) @@ -20,7 +20,44 @@ #include <device/device.h> #include "chip.h" +#include <device/pci_def.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#define OUTB outb +#define INB inb + +/* +* Taken from flashrom project +* Generic Super I/O helper functions +*/ +static uint8_t sio_read(uint16_t port, uint8_t reg) +{ + OUTB( reg, port ); + return ( INB( port + 1 ) ); +} + +static void sio_write(uint16_t port, uint8_t reg, uint8_t data) +{ + OUTB( reg, port ); + OUTB( data, port + 1 ); + return; +} + +static void nokia_ip530_board_enable( device_t dev ) +{ + print_debug( "Setting up IP530-Super I/O devices\n"); + sio_write( 0x20, 0x03, 0x80 ); + printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) ); + sio_write( 0x20, 0x22, 0x30 ); + printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) ); + sio_write( 0x20, 0x24, 0x84 ); + printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) ); + return; +} struct chip_operations mainboard_ops = { CHIP_NAME("Nokia IP530 Mainboard") + .enable_dev = nokia_ip530_board_enable, };

3 2

build service results for r5620
by repository service 07 Jun '10

07 Jun '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5620 to the coreboot repository. This caused the following changes: Change Log: Remove the rest of cardbus_scan_bus. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of getac:p470 has been fixed Compilation of roda:rk886ex has been fixed Compilation of via:epia-m has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5620 - in trunk/src: include/device southbridge/ricoh/rl5c476 southbridge/ti/pci7420 southbridge/ti/pcixx12
by repository service 07 Jun '10

07 Jun '10

Author: myles Date: Mon Jun 7 19:12:57 2010 New Revision: 5620 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5620 Log: Remove the rest of cardbus_scan_bus. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/include/device/cardbus.h trunk/src/southbridge/ricoh/rl5c476/rl5c476.c trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c trunk/src/southbridge/ti/pcixx12/pcixx12.c Modified: trunk/src/include/device/cardbus.h ============================================================================== --- trunk/src/include/device/cardbus.h Mon Jun 7 18:51:11 2010 (r5619) +++ trunk/src/include/device/cardbus.h Mon Jun 7 19:12:57 2010 (r5620) @@ -3,9 +3,6 @@ /* (c) 2005 Linux Networx GPL see COPYING for details */ void cardbus_read_resources(device_t dev); -unsigned int cardbus_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max); -unsigned int cardbus_scan_bridge(device_t dev, unsigned int max); void cardbus_enable_resources(device_t dev); extern struct device_operations default_cardbus_ops_bus; Modified: trunk/src/southbridge/ricoh/rl5c476/rl5c476.c ============================================================================== --- trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Mon Jun 7 18:51:11 2010 (r5619) +++ trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Mon Jun 7 19:12:57 2010 (r5620) @@ -203,7 +203,7 @@ .set_resources = rl5c476_set_resources, .enable_resources = cardbus_enable_resources, .init = rl5c476_init, - .scan_bus = cardbus_scan_bridge, + .scan_bus = pci_scan_bridge, }; static const struct pci_driver ricoh_rl5c476_driver __pci_driver = { Modified: trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c ============================================================================== --- trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c Mon Jun 7 18:51:11 2010 (r5619) +++ trunk/src/southbridge/ti/pci7420/pci7420_cardbus.c Mon Jun 7 19:12:57 2010 (r5620) @@ -102,7 +102,7 @@ .set_resources = pci7420_cardbus_set_resources, .enable_resources = cardbus_enable_resources, .init = pci7420_cardbus_init, - .scan_bus = cardbus_scan_bridge, + .scan_bus = pci_scan_bridge, }; static const struct pci_driver ti_pci7420_driver __pci_driver = { Modified: trunk/src/southbridge/ti/pcixx12/pcixx12.c ============================================================================== --- trunk/src/southbridge/ti/pcixx12/pcixx12.c Mon Jun 7 18:51:11 2010 (r5619) +++ trunk/src/southbridge/ti/pcixx12/pcixx12.c Mon Jun 7 19:12:57 2010 (r5620) @@ -52,7 +52,7 @@ .set_resources = pcixx12_set_resources, .enable_resources = cardbus_enable_resources, .init = pcixx12_init, - .scan_bus = cardbus_scan_bridge, + .scan_bus = pci_scan_bridge, }; static const struct pci_driver ti_pcixx12_driver __pci_driver = {

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build service results for r5619
by repository service 07 Jun '10

07 Jun '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5619 to the coreboot repository. This caused the following changes: Change Log: cardbus_scan_bridge is identical to pci_scan_bridge (since PCI_PRIMARY_BUS == PCI_CB_PRIMARY_BUS.) Remove it. Fix a typo while there. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5619&device=p470&vendor=ge… Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5619&device=rk886ex&vendor… Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5619&device=epia-m&vendor=… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] remove duplicate code
by Myles Watson 07 Jun '10

07 Jun '10

cardbus_scan_bridge is identical to pci_scan_bridge (since PCI_PRIMARY_BUS == PCI_CB_PRIMARY_BUS.) Remove it. Fix a typo while there. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot June 2010