coreboot June 2010

coreboot@coreboot.org

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222 discussions

[commit] r5616 - in trunk/payloads/libpayload: drivers/usb include/usb
by repository service 07 Jun '10

07 Jun '10

Author: oxygene Date: Mon Jun 7 15:58:17 2010 New Revision: 5616 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5616 Log: Avoid using the name "pid_t", which is used on unixoid systems. Move controller specific data structures into private headers, to avoid conflicts between controller drivers. Factor out the USB PID ids, which are only exposed on UHCI. It's of not much use on the other controllers. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/payloads/libpayload/drivers/usb/uhci_private.h - copied, changed from r5615, trunk/payloads/libpayload/drivers/usb/uhci.h Modified: trunk/payloads/libpayload/drivers/usb/uhci.c trunk/payloads/libpayload/drivers/usb/uhci.h trunk/payloads/libpayload/drivers/usb/uhci_rh.c trunk/payloads/libpayload/include/usb/usb.h Modified: trunk/payloads/libpayload/drivers/usb/uhci.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/uhci.c Mon Jun 7 10:29:36 2010 (r5615) +++ trunk/payloads/libpayload/drivers/usb/uhci.c Mon Jun 7 15:58:17 2010 (r5616) @@ -29,16 +29,17 @@ //#define USB_DEBUG +#include <arch/virtual.h> #include <usb/usb.h> #include "uhci.h" -#include <arch/virtual.h> +#include "uhci_private.h" static void uhci_start (hci_t *controller); static void uhci_stop (hci_t *controller); static void uhci_reset (hci_t *controller); static void uhci_shutdown (hci_t *controller); static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize); -static int uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, +static int uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen, u8 *data); static void* uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming); static void uhci_destroy_intr_queue (endpoint_t *ep, void *queue); @@ -66,13 +67,13 @@ char td_value[3]; char *td_type; switch (td->pid) { - case SETUP: + case UHCI_SETUP: td_type="SETUP"; break; - case IN: + case UHCI_IN: td_type="IN"; break; - case OUT: + case UHCI_OUT: td_type="OUT"; break; default: @@ -296,7 +297,7 @@ } static int -uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, int dalen, +uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen, unsigned char *data) { int endp = 0; /* this is control: always 0 */ @@ -316,7 +317,7 @@ tds[count].depth_first = 1; tds[count].terminate = 1; - tds[0].pid = SETUP; + tds[0].pid = UHCI_SETUP; tds[0].dev_addr = dev->address; tds[0].endp = endp; tds[0].maxlen = maxlen (drlen); @@ -328,7 +329,11 @@ int toggle = 1; for (i = 1; i < count; i++) { - tds[i].pid = dir; + switch (dir) { + case SETUP: tds[i].pid = UHCI_SETUP; break; + case IN: tds[i].pid = UHCI_IN; break; + case OUT: tds[i].pid = UHCI_OUT; break; + } tds[i].dev_addr = dev->address; tds[i].endp = endp; tds[i].maxlen = maxlen (min (mlen, dalen)); @@ -342,7 +347,7 @@ data += mlen; } - tds[count].pid = (dir == OUT) ? IN : OUT; + tds[count].pid = (dir == OUT) ? UHCI_IN : UHCI_OUT; tds[count].dev_addr = dev->address; tds[count].endp = endp; tds[count].maxlen = maxlen (0); Modified: trunk/payloads/libpayload/drivers/usb/uhci.h ============================================================================== --- trunk/payloads/libpayload/drivers/usb/uhci.h Mon Jun 7 10:29:36 2010 (r5615) +++ trunk/payloads/libpayload/drivers/usb/uhci.h Mon Jun 7 15:58:17 2010 (r5616) @@ -33,90 +33,6 @@ #include <pci.h> #include <usb/usb.h> -typedef union { - struct { - unsigned long terminate:1; - unsigned long queue_head:1; - unsigned long:2; - unsigned long ptr_part:28; - }; - u32 ptr; -} __attribute__ ((packed)) flistp_t; - -typedef struct { - union { - struct { - unsigned long terminate:1; - unsigned long queue_head:1; - unsigned long depth_first:1; - unsigned long:29; - } __attribute__ ((packed)); - u32 ptr; - } __attribute__ ((packed)); - - volatile unsigned long actlen:11; - volatile unsigned long:5; - union { - struct { - unsigned long:1; // bit 0 - unsigned long status_bitstuff_err:1; - unsigned long status_crc_err:1; - unsigned long status_nakrcvd:1; - unsigned long status_babble:1; - unsigned long status_databuf_err:1; - unsigned long status_stalled:1; - unsigned long status_active:1; // bit 7 - } __attribute__ ((packed)); - unsigned char status; - } __attribute__ ((packed)); - volatile unsigned long ioc:1; /* interrupt on complete */ - volatile unsigned long isochronous:1; - volatile unsigned long lowspeed:1; - volatile unsigned long counter:2; - volatile unsigned long shortpck:1; - volatile unsigned long:2; - - unsigned long pid:8; - unsigned long dev_addr:7; - unsigned long endp:4; - unsigned long data_toggle:1; - unsigned long:1; - unsigned long maxlen:11; - - u32 bufptr; - -} __attribute__ ((packed)) - td_t; - - typedef struct { - flistp_t headlinkptr; - volatile flistp_t elementlinkptr; - } __attribute__ ((packed)) - qh_t; - - typedef enum { USBCMD = 0, USBSTS = 2, USBINTR = 4, FRNUM = - 6, FLBASEADD = 8, SOFMOD = 0xc, PORTSC1 = 0x10, PORTSC2 = - 0x12 - } usbreg; - - void uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value); - u32 uhci_reg_read32 (hci_t *ctrl, usbreg reg); - void uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value); - u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg); - void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value); - u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg); - void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask); - void uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask); - void uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask); - - typedef struct uhci { - flistp_t *framelistptr; - qh_t *qh_prei, *qh_intr, *qh_data, *qh_last; - usbdev_t *roothub; - } uhci_t; - -#define UHCI_INST(controller) ((uhci_t*)((controller)->instance)) - hci_t *uhci_init (pcidev_t addr); void uhci_rh_init (usbdev_t *dev); Copied and modified: trunk/payloads/libpayload/drivers/usb/uhci_private.h (from r5615, trunk/payloads/libpayload/drivers/usb/uhci.h) ============================================================================== --- trunk/payloads/libpayload/drivers/usb/uhci.h Mon Jun 7 10:29:36 2010 (r5615, copy source) +++ trunk/payloads/libpayload/drivers/usb/uhci_private.h Mon Jun 7 15:58:17 2010 (r5616) @@ -27,11 +27,10 @@ * SUCH DAMAGE. */ -#ifndef __UHCI_H -#define __UHCI_H +#ifndef __UHCI_PRIVATE_H +#define __UHCI_PRIVATE_H -#include <pci.h> -#include <usb/usb.h> +typedef enum { UHCI_SETUP = 0x2d, UHCI_IN = 0x69, UHCI_OUT = 0xe1 } uhci_pid_t; typedef union { struct { @@ -117,8 +116,4 @@ #define UHCI_INST(controller) ((uhci_t*)((controller)->instance)) - hci_t *uhci_init (pcidev_t addr); - - void uhci_rh_init (usbdev_t *dev); - #endif Modified: trunk/payloads/libpayload/drivers/usb/uhci_rh.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/uhci_rh.c Mon Jun 7 10:29:36 2010 (r5615) +++ trunk/payloads/libpayload/drivers/usb/uhci_rh.c Mon Jun 7 15:58:17 2010 (r5616) @@ -31,6 +31,7 @@ #include <libpayload.h> #include "uhci.h" +#include "uhci_private.h" typedef struct { int port[2]; Modified: trunk/payloads/libpayload/include/usb/usb.h ============================================================================== --- trunk/payloads/libpayload/include/usb/usb.h Mon Jun 7 10:29:36 2010 (r5615) +++ trunk/payloads/libpayload/include/usb/usb.h Mon Jun 7 15:58:17 2010 (r5616) @@ -80,14 +80,14 @@ struct usbdev; typedef struct usbdev usbdev_t; -typedef enum { SETUP = 0x2d, IN = 0x69, OUT = 0xe1 } pid_t; +typedef enum { SETUP, IN, OUT } direction_t; typedef enum { CONTROL = 0, ISOCHRONOUS = 1, BULK = 2, INTERRUPT = 3 } endpoint_type; typedef struct { usbdev_t *dev; int endpoint; - pid_t direction; + direction_t direction; int toggle; int maxpacketsize; endpoint_type type; @@ -121,7 +121,7 @@ void (*reset) (hci_t *controller); void (*shutdown) (hci_t *controller); int (*bulk) (endpoint_t *ep, int size, u8 *data, int finalize); - int (*control) (usbdev_t *dev, pid_t pid, int dr_length, + int (*control) (usbdev_t *dev, direction_t pid, int dr_length, void *devreq, int data_length, u8 *data); void* (*create_intr_queue) (endpoint_t *ep, int reqsize, int reqcount, int reqtiming); void (*destroy_intr_queue) (endpoint_t *ep, void *queue);

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Fwd: SIS630ET coreboot challenge
by Darmawan Salihun 07 Jun '10

07 Jun '10

---------- Forwarded message ---------- From: Darmawan Salihun <darmawan.salihun(a)gmail.com> Date: Mon, 7 Jun 2010 20:00:08 +0700 Subject: Re: [coreboot] SIS630ET coreboot challenge To: Tiago Marques <tiagomnm(a)gmail.com> I've sent a datasheet in my posession to Keith. Haven't heard back from him yet. Hopefully he can make use of it :-) On 6/6/10, Tiago Marques <tiagomnm(a)gmail.com> wrote: > Me? I wasn't after that. > > Best regards > > On Sat, Jun 5, 2010 at 9:32 AM, Stefan Reinauer < > stefan.reinauer(a)coresystems.de> wrote: > >> On 6/5/10 5:15 AM, Tiago Marques wrote: >> > See the attachment, doesn't look like something from a company that's >> > alive and kicking. I know them since the SiS 730. >> > Last time I heard they had some design win for a Core 2 chipset that I >> > haven't seen in any product and started selling SiS branded SO-DIMMS :| >> > >> So you did contact them for data sheets? >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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[PATCH]Changes to libpayload's USB stack
by Patrick Georgi 07 Jun '10

07 Jun '10

Hi, attached patch - avoids using the name "pid_t", which is used on unixoid systems - moves controller specific data structures into private headers, to avoid conflicts between controller drivers - factors out the USB PID ids, which are only exposed on UHCI. It's of not much use on the other controllers. It requires a copy of uhci.h to uhci_private.h Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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Re: [coreboot] [PATCH] Fix geode lx VSA loading
by Stefan Reinauer 07 Jun '10

07 Jun '10

On 6/7/10 10:30 AM, Edwin Beasant wrote: > Agreed - ax should be 0, it is only 0 in this case due to the argument passed in! > Before the segment setup, but after the _registers section, an xorl %ax, %al would be appropriate. > Thanks! > Edwin > > Did I miss one? Stefan > -----Original Message----- > From: coreboot-bounces+edwin_beasant=virtensys.com(a)coreboot.org [mailto:coreboot-bounces+edwin_beasant=virtensys.com@coreboot.org] On Behalf Of ron minnich > Sent: 06 June 2010 05:50 > To: Myles Watson > Cc: Stefan Reinauer; coreboot(a)coreboot.org > Subject: Re: [coreboot] [PATCH] Fix geode lx VSA loading > > On Fri, Jun 4, 2010 at 9:53 AM, Myles Watson <mylesgw(a)gmail.com> wrote: > > >> mov $0, %ax >> > use the classic: > xorl %ax, %ax > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > >

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Re: [coreboot] [PATCH] Fix geode lx VSA loading
by Patrick Georgi 07 Jun '10

07 Jun '10

Am Freitag, den 04.06.2010, 16:25 +0100 schrieb Edwin Beasant: > This patch fixes the option rom code that was buggy when it switched > segment registers before restoring register values. This was breaking > the Geode VSA, and probably would have hurt other option roms as well. > > > > Signed-off by: Edwin Beasant edwin_beasant(a)virtensys.com Except for the first two parts (the magic values in ecx/edx and whitespace), and assuming this is tested, the patch is Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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[commit] r5615 - in trunk/src: cpu/amd/car cpu/amd/model_lx cpu/via/car mainboard/digitallogic/msm586seg
by repository service 07 Jun '10

07 Jun '10

Author: stepan Date: Mon Jun 7 10:29:36 2010 New Revision: 5615 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5615 Log: replace outb -> port 0x80 with post_code() in some places. Especially most _smbus functions misuse port 0x80 writes for delays. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/mainboard/digitallogic/msm586seg/romstage.c Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Sat Jun 5 12:03:08 2010 (r5614) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Mon Jun 7 10:29:36 2010 (r5615) @@ -49,9 +49,7 @@ /*for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: - - movb $0xA0, %al - outb %al, $0x80 + post_code(0xa0) /* enable SSE */ movl %cr4, %eax @@ -284,8 +282,7 @@ orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax wrmsr - movb $0xA1, %al - outb %al, $0x80 + post_code(0xa1) /* enable cache */ movl %cr0, %eax @@ -301,8 +298,7 @@ jnc CAR_FAM10_ap fam10_end_part1: - movb $0xA2, %al - outb %al, $0x80 + post_code(0xa2) /* Read the range with lodsl*/ cld @@ -320,8 +316,7 @@ movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl %eax, %esp - movb $0xA3, %al - outb %al, $0x80 + post_code(0xa3) jmp CAR_FAM10_ap_out CAR_FAM10_ap: @@ -363,13 +358,11 @@ /* retrive init detected */ movl %esi, %ebx - movb $0xA4, %al - outb %al, $0x80 + post_code(0xa4) CAR_FAM10_ap_out: - movb $0xA5, %al - outb %al, $0x80 + post_code(0xa5) /* disable SSE */ movl %cr4, %eax @@ -386,8 +379,7 @@ call cache_as_ram_main /* We will not go back */ - movb $0xAF, %al /* Should never see this postcode */ - outb %al, $0x80 + post_code(0xaf) /* Should never see this postcode */ fixed_mtrr_msr: .long 0x250, 0x258, 0x259 Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Sat Jun 5 12:03:08 2010 (r5614) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Mon Jun 7 10:29:36 2010 (r5615) @@ -169,8 +169,8 @@ popl %ecx cmpl %ecx, %edx je DCacheSetupGood - movb $0xC5, %al - outb %al, $0x80 + + post_code(0xc5) DCacheSetupBad: hlt /* issues */ jmp DCacheSetupBad Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Sat Jun 5 12:03:08 2010 (r5614) +++ trunk/src/cpu/via/car/cache_as_ram.inc Mon Jun 7 10:29:36 2010 (r5615) @@ -152,8 +152,8 @@ movl %eax, %esp #ifdef CARTEST -testok: movb $0x40,%al - outb %al, $0x80 +testok: + post_code(0x40) xorl %edx, %edx xorl %eax, %eax movl $0x5c5c,%edx Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sat Jun 5 12:03:08 2010 (r5614) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Mon Jun 7 10:29:36 2010 (r5615) @@ -183,7 +183,7 @@ // while(1) print_err("STATIC MEM DONE\n"); - outb(0xee, 0x80); + post_code(0xee); print_err("loop forever ...\n"); #if 0 @@ -231,13 +231,14 @@ *dst = *src; //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n"); dst++, src++; - outb((unsigned char)i, 0x80); + post_code(i & 0xff); } } dumpmem(); - outb(0, 0x80); + post_code(0x00); + print_err("loop forever\n"); - outb(0xdd, 0x80); + post_code(0xdd); __asm__ volatile( "movl %0, %%edi\n\t" "jmp *%%edi\n\t"

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AMD CAR quiz question
by Rudolf Marek 07 Jun '10

07 Jun '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, It makes me wonder why CAR on APs use same stack? How does this can work? I thought CPUs somehow keep caches coherent between them. I see that Fam10h CAR code allocates 1KB for each AP. But not pre Fam10h. How this can work? Rationale for question is to have some kind of mutex for serial console printouts and for Network over console. Secret plan is to print outputs from different CPUs on different UDP port ;) Second reason is that we really need some inter CPU mutex for PCI access. In principle is correct that all CPUs once after CAR stage share the cache contents? Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkwLuDwACgkQ3J9wPJqZRNU/cwCcChsbMNe7bxKp03IofGnNvU/g YiEAn1z1+Du/GgB/i5+4tBq2ItJ0ylyr =ArrJ -----END PGP SIGNATURE-----

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Re: [coreboot] Mobo Support
by Anders Jenbo 07 Jun '10

07 Jun '10

Hallo David I am currently working on the chip-set that your board uses. So support is in progress. I have debug console running via serial and i am about a 1/3 in to getting the ram initialized. If you think you can help (time is the only real skill required) coding in the support you are more then welcome. You should get in contact with the flashrom developers to get support for your flash chip. Remove the AMI BIOS lable from the rom chip and read the fist number on the actual chip, should be some thing similar to these http://www.flashrom.org/Supported_hardware. You can find the flashrom developers at freenode.net #flashrom, or flashrom(a)flashrom.org. Good luck -Anders On Sun 06/06/10 19:17 , David Borg <borg.db(a)gmail.com> wrote: > Hey all, I was thinking of trying out coreboot on my old desktop pc > and would like to check whether the motherboard is supported, as it is > not in the list of supported motherboards. > System description: > Board vendor : GigabyteBoard name : GA-6VX7-4XCPU : Intel Celeron > 633MHz > Northbridge : VT82C694X > (URL: http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446 > 497.pdf[1]) Southbridge : VT82C686A > (URL: http://www.charmed.com/PDF/VT82C686A.pdf [2]) > > The output of lspci -tvnn is attached (lscpi.txt). Note:-0b.0 > Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] > > Links: > ------ > [1] > http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446497.pdf > [2] http://www.charmed.com/PDF/VT82C686A.pdf > [3] > http://www.gigabyte.com/products/product-page.aspx?pid=1415&dl=#sp > > ---- Msg sent via @Mail - http://atmail.com/

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Mobo Support
by David Borg 06 Jun '10

06 Jun '10

Hey all, I was thinking of trying out coreboot on my old desktop pc and would like to check whether the motherboard is supported, as it is not in the list of supported motherboards. System description: Board vendor : Gigabyte Board name : GA-6VX7-4X CPU : Intel Celeron 633MHz Northbridge : VT82C694X (URL: http://www.datasheetarchive.com/pdf-datasheets/Datasheets-23/DSA-446497.pdf) Southbridge : VT82C686A (URL: http://www.charmed.com/PDF/VT82C686A.pdf) The output of lspci -tvnn is attached (lscpi.txt). Note: \-0b.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] <= PCI network card +-01.0-[0000:01]----00.0 S3 Inc. 86c368 [Trio 3D/2X] [5333:8a13] <= AGP graphics card No super io chip was identified by superiotool (output attached as superiotool.txt). Note: Super-IO should be integrated in the southbridge chip VT82C686A BIOS device: PLCC32 chip (soldered directly to mainboard). Flashrom does not detect the BIOS chip. Output of flashrom attached as flashrom.txt Motherboard info: http://www.gigabyte.com/products/product-page.aspx?pid=1415&dl=#sp Thanks, David Borg

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A patch to replace the headers of three files - no functional changes.
by Vibrans, Frank 06 Jun '10

06 Jun '10

This patch replaces the headers of the following files: src/cpu/amd/model_fxx/model_fxx_update_microcode.c src/northbridge/amd/amdk8/amdk8_acpi.c src/southbridge/amd/amd8132/amd8132_bridge.c Signed-off by: Frank Vibrans frank.vibrans(a)amd.com<mailto:frank.vibrans@amd.com> ---

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coreboot June 2010