---------- Forwarded message ----------
From: Darmawan Salihun <darmawan.salihun(a)gmail.com>
Date: Mon, 7 Jun 2010 20:00:08 +0700
Subject: Re: [coreboot] SIS630ET coreboot challenge
To: Tiago Marques <tiagomnm(a)gmail.com>
I've sent a datasheet in my posession to Keith. Haven't heard back
from him yet. Hopefully he can make use of it :-)
On 6/6/10, Tiago Marques <tiagomnm(a)gmail.com> wrote:
> Me? I wasn't after that.
> Best regards
> On Sat, Jun 5, 2010 at 9:32 AM, Stefan Reinauer <
> stefan.reinauer(a)coresystems.de> wrote:
>> On 6/5/10 5:15 AM, Tiago Marques wrote:
>> > See the attachment, doesn't look like something from a company that's
>> > alive and kicking. I know them since the SiS 730.
>> > Last time I heard they had some design win for a Core 2 chipset that I
>> > haven't seen in any product and started selling SiS branded SO-DIMMS :|
>> So you did contact them for data sheets?
>> coreboot mailing list: coreboot(a)coreboot.org
-= Human knowledge belongs to the world =-
-= Human knowledge belongs to the world =-
- avoids using the name "pid_t", which is used on unixoid systems
- moves controller specific data structures into private headers,
to avoid conflicts between controller drivers
- factors out the USB PID ids, which are only exposed on UHCI. It's
of not much use on the other controllers.
It requires a copy of uhci.h to uhci_private.h
Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
On 6/7/10 10:30 AM, Edwin Beasant wrote:
> Agreed - ax should be 0, it is only 0 in this case due to the argument passed in!
> Before the segment setup, but after the _registers section, an xorl %ax, %al would be appropriate.
Did I miss one?
> -----Original Message-----
> From: coreboot-bounces+edwin_beasant=virtensys.com(a)coreboot.org [mailto:firstname.lastname@example.org] On Behalf Of ron minnich
> Sent: 06 June 2010 05:50
> To: Myles Watson
> Cc: Stefan Reinauer; coreboot(a)coreboot.org
> Subject: Re: [coreboot] [PATCH] Fix geode lx VSA loading
> On Fri, Jun 4, 2010 at 9:53 AM, Myles Watson <mylesgw(a)gmail.com> wrote:
>> mov $0, %ax
> use the classic:
> xorl %ax, %ax
> coreboot mailing list: coreboot(a)coreboot.org
Am Freitag, den 04.06.2010, 16:25 +0100 schrieb Edwin Beasant:
> This patch fixes the option rom code that was buggy when it switched
> segment registers before restoring register values. This was breaking
> the Geode VSA, and probably would have hurt other option roms as well.
> Signed-off by: Edwin Beasant edwin_beasant(a)virtensys.com
Except for the first two parts (the magic values in ecx/edx and
whitespace), and assuming this is tested, the patch is
Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de>
-----BEGIN PGP SIGNED MESSAGE-----
It makes me wonder why CAR on APs use same stack? How does this can work? I
thought CPUs somehow keep caches coherent between them. I see that Fam10h CAR
code allocates 1KB for each AP. But not pre Fam10h.
How this can work?
Rationale for question is to have some kind of mutex for serial console
printouts and for Network over console. Secret plan is to print outputs from
different CPUs on different UDP port ;)
Second reason is that we really need some inter CPU mutex for PCI access.
In principle is correct that all CPUs once after CAR stage share the cache contents?
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
-----END PGP SIGNATURE-----
Hey all, I was thinking of trying out coreboot on my old desktop pc and
would like to check whether the motherboard is supported, as it is not in
the list of supported motherboards.
Board vendor : Gigabyte
Board name : GA-6VX7-4X
CPU : Intel Celeron 633MHz
Northbridge : VT82C694X (URL:
Southbridge : VT82C686A (URL: http://www.charmed.com/PDF/VT82C686A.pdf)
The output of lspci -tvnn is attached (lscpi.txt).
\-0b.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] <=
PCI network card
+-01.0-[0000:01]----00.0 S3 Inc. 86c368 [Trio 3D/2X] [5333:8a13] <= AGP
No super io chip was identified by superiotool (output attached as
Super-IO should be integrated in the southbridge chip VT82C686A
BIOS device: PLCC32 chip (soldered directly to mainboard). Flashrom does not
detect the BIOS chip.
Output of flashrom attached as flashrom.txt
This patch replaces the headers of the following files:
Signed-off by: Frank Vibrans frank.vibrans(a)amd.com<mailto:email@example.com>