coreboot June 2010

coreboot@coreboot.org

60 participants
222 discussions

nVidia CK804 + AMD Fam 10 + Winbond Super I/O
by Mayhall, Anthony J. (MSFC-ES53)[Dynamic Concepts Inc.] 01 Jun '10

01 Jun '10

Has anyone ever put together a motherboard configuration using the nVidia CK804, AMD Fam 10 and Winbond W83627HF SuperI/O chipsets? And has anyone used CoreBoot with the 6 core AMD Opteron processors? Thanks, Anthony Mayhall Dynamic Concepts, Inc. (256)544-7620

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[commit] r5604 - trunk/src/arch/i386/boot
by repository service 01 Jun '10

01 Jun '10

Author: myles Date: Tue Jun 1 21:28:45 2010 New Revision: 5604 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5604 Log: Fix a format string to keep the compiler happy. Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/arch/i386/boot/pirq_routing.c Modified: trunk/src/arch/i386/boot/pirq_routing.c ============================================================================== --- trunk/src/arch/i386/boot/pirq_routing.c Tue Jun 1 21:25:31 2010 (r5603) +++ trunk/src/arch/i386/boot/pirq_routing.c Tue Jun 1 21:28:45 2010 (r5604) @@ -64,7 +64,7 @@ rt_curr = (uint8_t*)addr; rt_orig = (uint8_t*)&intel_irq_routing_table; - printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08x... ", addr); + printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08lx... ", addr); for (i = 0; i < intel_irq_routing_table.size; i++) { if (*(rt_curr + i) != *(rt_orig + i)) { printk(BIOS_INFO, "failed\n");

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[commit] r5603 - in trunk/src: . arch/i386/boot mainboard/lippert/spacerunner-lx
by repository service 01 Jun '10

01 Jun '10

Author: myles Date: Tue Jun 1 21:25:31 2010 New Revision: 5603 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5603 Log: CONFIG_DEBUG is too generic. Remove it and replace it with CONFIG_DEBUG_SMBUS and CONFIG_DEBUG_PIRQ. Fix a couple of typos. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/Kconfig trunk/src/arch/i386/boot/pirq_routing.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Tue Jun 1 17:19:25 2010 (r5602) +++ trunk/src/Kconfig Tue Jun 1 21:25:31 2010 (r5603) @@ -139,10 +139,6 @@ hex default 0x4000 -config DEBUG - bool - default n - config USE_PRINTK_IN_CAR bool default n @@ -520,6 +516,13 @@ If unsure, say N. +config DEBUG_PIRQ + bool "Check PIRQ table consistency" + default n + depends on GENERATE_PIRQ_TABLE + help + If unsure, say N. + config DEBUG_SMBUS bool "Output verbose SMBus debug messages" default n @@ -528,6 +531,7 @@ || NORTHBRIDGE_VIA_CX700 \ || NORTHBRIDGE_AMD_AMDK8 \ || NORTHBRIDGE_AMD_AMDFAM10 \ + || BOARD_LIPPERT_SPACERUNNER_LX \ || SOUTHBRIDGE_VIA_VT8231) help This option enables additional SMBus (and SPD) debug messages. Modified: trunk/src/arch/i386/boot/pirq_routing.c ============================================================================== --- trunk/src/arch/i386/boot/pirq_routing.c Tue Jun 1 17:19:25 2010 (r5602) +++ trunk/src/arch/i386/boot/pirq_routing.c Tue Jun 1 21:25:31 2010 (r5603) @@ -3,7 +3,7 @@ #include <string.h> #include <device/pci.h> -#if CONFIG_DEBUG +#if CONFIG_DEBUG_PIRQ static void check_pirq_routing_table(struct irq_routing_table *rt) { uint8_t *addr = (uint8_t *)rt; @@ -13,7 +13,7 @@ printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n"); if (sizeof(struct irq_routing_table) != rt->size) { - printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", + printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%lx/0x%x).\n", sizeof(struct irq_routing_table), rt->size ); @@ -51,7 +51,7 @@ */ if (sum) { printk(BIOS_WARNING, "Checksum error in Interrupt Routing Table " - "could not be fixed.\n"); + "could not be fixed.\n"); } printk(BIOS_INFO, "done.\n"); @@ -64,7 +64,7 @@ rt_curr = (uint8_t*)addr; rt_orig = (uint8_t*)&intel_irq_routing_table; - printk(BIOS_INFO, "Verifing copy of Interrupt Routing Table at 0x%08x... ", addr); + printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08x... ", addr); for (i = 0; i < intel_irq_routing_table.size; i++) { if (*(rt_curr + i) != *(rt_orig + i)) { printk(BIOS_INFO, "failed\n"); @@ -89,7 +89,7 @@ printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ", addr); memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size); printk(BIOS_INFO, "done.\n"); -#if CONFIG_DEBUG +#if CONFIG_DEBUG_PIRQ verify_copy_pirq_routing_table(addr); #endif pirq_routing_irqs(addr); Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Jun 1 17:19:25 2010 (r5602) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Jun 1 21:25:31 2010 (r5603) @@ -84,7 +84,7 @@ if (device != DIMM0) return 0xFF; /* No DIMM1, don't even try. */ -#if CONFIG_DEBUG +#if CONFIG_DEBUG_SMBUS if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { print_err("ERROR: spd_read_byte(DIMM0, 0x"); print_err_hex8(address);

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addition to getpir
by mbertens 01 Jun '10

01 Jun '10

hi all, i make an addition to getpir, getpir works are before without any commandline parameters. when applying for example build\coreboot_ram as parameter it looks in the file for the PIRQ table prints it to stdout and shows if the checksum is correct. THis is very handy for developing a PIRQ table. Marc PS this patch was send before, but was not applied to svn.

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[PATCH] superiotool support for Fintek F81216
by Stefan Reinauer 01 Jun '10

01 Jun '10

See patch... ./superiotool -d superiotool r5549 Found Fintek F81216A/AG (vid=0x3419, id=0x1602) at 0x4e Register dump: idx 25 27 val 00 10 def 00 NA LDN 0x00 (UART1) idx 30 60 61 70 f0 f1 f4 f5 val 00 00 00 00 00 44 00 00 def NA NA NA NA 00 40 00 00 LDN 0x01 (UART2) idx 30 60 61 70 f0 f4 f5 val 00 00 00 00 00 00 00 def NA NA NA NA 00 00 00 LDN 0x02 (UART3) idx 30 60 61 70 f0 f4 f5 val 00 00 00 00 00 00 00 def NA NA NA NA 00 00 00 LDN 0x03 (UART4) idx 30 60 61 70 f0 f4 f5 val 00 00 00 00 00 00 00 def NA NA NA NA 00 00 00 LDN 0x08 (WDT) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 00 def 00 NA NA NA NA NA -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Trying to build MSI 6119 coreboot BIOS
by Alex Buell 01 Jun '10

01 Jun '10

I've just downloaded and built SeaBIOS ready to use with CoreBoot on my old MSI 6119 motherboard. Unfortunately, CoreBoot is stopping with a build error in src/lib/uart8250.c with an undeclared CONFIG_TTYS0_BASE error on line 83. I have checked and serial console output is definitely disabled in menuconfig. Any ideas why? I'm using the latest svn checkout, many thanks! -- http://www.munted.org.uk One very high maintenance cat living here.

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Selfboot error checking fix
by Myles Watson 01 Jun '10

01 Jun '10

Check the return value of ulzma, and quit instead of loading the next segment if there's an error. Size pointers 8 characters instead of 16 to beautify the common case where selfboot is loading something into memory below 4GB. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[commit] r5602 - trunk/src/boot
by repository service 01 Jun '10

01 Jun '10

Author: myles Date: Tue Jun 1 17:19:25 2010 New Revision: 5602 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5602 Log: Check the value of ulzma and do not continue if there was an error. Print fewer characters for pointers to make the output more concise. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/boot/selfboot.c Modified: trunk/src/boot/selfboot.c ============================================================================== --- trunk/src/boot/selfboot.c Tue Jun 1 12:04:28 2010 (r5601) +++ trunk/src/boot/selfboot.c Tue Jun 1 17:19:25 2010 (r5602) @@ -473,6 +473,8 @@ case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); len = ulzma(src, dest); + if (!len) /* Decompression Error. */ + return 0; break; } #if CONFIG_COMPRESSED_PAYLOAD_NRV2B==1 @@ -495,7 +497,7 @@ } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%016lx, %016lx, 0x%016lx) <- %016lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", (unsigned long)dest, (unsigned long)middle, (unsigned long)end,

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[commit] r5601 - trunk/util/inteltool
by repository service 01 Jun '10

01 Jun '10

Author: stepan Date: Tue Jun 1 12:04:28 2010 New Revision: 5601 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5601 Log: inteltool: basic poulsbo sch support. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/cpu.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h Modified: trunk/util/inteltool/cpu.c ============================================================================== --- trunk/util/inteltool/cpu.c Sun May 30 15:44:32 2010 (r5600) +++ trunk/util/inteltool/cpu.c Tue Jun 1 12:04:28 2010 (r5601) @@ -464,7 +464,7 @@ /* Get CPU family and model, not the stepping * (TODO: extended family/model) */ - id = cpuid(1) & 0xff0; + id = cpuid(1) & 0xfffff0; for (i = 0; i < ARRAY_SIZE(cpulist); i++) { if(cpulist[i].model == id) { cpu = &cpulist[i]; Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Sun May 30 15:44:32 2010 (r5600) +++ trunk/util/inteltool/inteltool.c Tue Jun 1 12:04:28 2010 (r5601) @@ -45,7 +45,9 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME-GMCH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" }, @@ -261,8 +263,16 @@ } id = cpuid(1); - printf("Intel CPU: Family %x, Model %x\n", - (id >> 8) & 0xf, (id >> 4) & 0xf); + + /* Intel has suggested applications to display the family of a CPU as + * the sum of the "Family" and the "Extended Family" fields shown + * above, and the model as the sum of the "Model" and the 4-bit + * left-shifted "Extended Model" fields. + * http://download.intel.com/design/processor/applnots/24161832.pdf + */ + printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n", + (id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff), + ((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf)); /* Determine names */ for (i = 0; i < ARRAY_SIZE(supported_chips_list); i++) Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Sun May 30 15:44:32 2010 (r5600) +++ trunk/util/inteltool/inteltool.h Tue Jun 1 12:04:28 2010 (r5601) @@ -51,6 +51,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810DC 0x7122 @@ -66,6 +67,7 @@ #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 #define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405 +#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */

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[PATCH] MCP55 azalia driver
by Stefan Reinauer 01 Jun '10

01 Jun '10

A while back I sent a fix for the MCP55 azalia driver which prevented coreboot from hanging and at the same time allowed per-board Azalia VERBs. The attached patch implements per-board VERBs for all MCP55 boards, and as I don't have the correct VERBs for all boards, uses the default MCP55 VERB for all of them. Stefan

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coreboot June 2010