coreboot June 2010

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Trac reminder: list of new ticket(s)
by coreboot tracker 14 Jun '10

14 Jun '10

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WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 2MB of RAM
by Joseph Smith 12 Jun '10

12 Jun '10

Hello, While working on my i810 port I am getting this message from the Linux kernel about my mtrr setup: BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 0000000000001000 type 16 BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 00000000000c0000 - 000000000fef0000 (usable) BIOS-e820: 000000000fef0000 - 000000000ff00000 type 16 DMI not present or invalid. last_pfn = 0xfef0 max_arch_pfn = 0x100000 WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 2MB of RAM. ------------[ cut here ]------------ WARNING: at arch/x86/kernel/cpu/mtrr/main.c:1557 mtrr_trim_uncached_memory+0x295/0x2b6() (Not tainted) Modules linked in: Pid: 0, comm: swapper Not tainted 2.6.27.24-170.2.68.fc10.i686 #1 [<c042ddfb>] warn_on_slowpath+0x65/0x8b [<c06ab53c>] ? _spin_unlock_irqrestore+0x1b/0x38 [<c06ab53c>] ? _spin_unlock_irqrestore+0x1b/0x38 [<c06ab543>] ? _spin_unlock_irqrestore+0x22/0x38 [<c042e2f1>] ? release_console_sem+0x1bf/0x1c7 [<c042e76c>] ? vprintk+0x2ce/0x2f3 [<c06a96db>] ? printk+0xf/0x14 [<c0824127>] mtrr_trim_uncached_memory+0x295/0x2b6 [<c081f73b>] setup_arch+0x48f/0x947 [<c042e76c>] ? vprintk+0x2ce/0x2f3 [<c08218dd>] ? __reserve_early+0xe4/0xf8 [<c06a96db>] ? printk+0xf/0x14 [<c0819605>] start_kernel+0x73/0x2f0 [<c0819080>] __init_begin+0x80/0x88 ======================= ---[ end trace 4eaa2a86a8e2da22 ]--- update e820 for mtrr modified physical RAM map: modified: 0000000000000000 - 0000000000001000 type 16 modified: 0000000000001000 - 00000000000a0000 (usable) modified: 00000000000c0000 - 000000000fc00000 (usable) modified: 000000000fc00000 - 000000000fef0000 (reserved) modified: 000000000fef0000 - 000000000ff00000 type 16 last_pfn = 0xfc00 max_arch_pfn = 0x100000 ---------------------------------------------- Any ideas? Full bootlog attached. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[commit] r5631 - trunk/payloads/libpayload/drivers/usb
by repository service 11 Jun '10

11 Jun '10

Author: oxygene Date: Fri Jun 11 16:25:40 2010 New Revision: 5631 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5631 Log: Follow up to the USB refactoring patch: Missed setting pid values correctly. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/payloads/libpayload/drivers/usb/uhci.c Modified: trunk/payloads/libpayload/drivers/usb/uhci.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/uhci.c Thu Jun 10 18:19:02 2010 (r5630) +++ trunk/payloads/libpayload/drivers/usb/uhci.c Fri Jun 11 16:25:40 2010 (r5631) @@ -400,7 +400,11 @@ fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data, int *toggle) { - td->pid = ep->direction; + switch (ep->direction) { + case IN: td->pid = UHCI_IN; break; + case OUT: td->pid = UHCI_OUT; break; + case SETUP: td->pid = UHCI_SETUP; break; + } td->dev_addr = ep->dev->address; td->endp = ep->endpoint & 0xf; td->maxlen = maxlen (length); @@ -507,7 +511,11 @@ tds[i].queue_head = 0; tds[i].depth_first = 0; - tds[i].pid = ep->direction; + switch (ep->direction) { + case IN: tds[i].pid = UHCI_IN; break; + case OUT: tds[i].pid = UHCI_OUT; break; + case SETUP: tds[i].pid = UHCI_SETUP; break; + } tds[i].dev_addr = ep->dev->address; tds[i].endp = ep->endpoint & 0xf; tds[i].maxlen = maxlen (reqsize);

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Re: [coreboot] Re PATCH: ECS P6IWP-Fe
by Joseph Smith 11 Jun '10

11 Jun '10

On Wed, 09 Jun 2010 16:26:31 +0200, "anders(a)jenbo.dk" <anders(a)jenbo.dk> wrote: > Agreed, the only reason I haven't done car yet is that I haven't had a > board where the best match to copy from used CAR. I defiantly hav plans for > updating all the boards I have to car but I am waiting til I hit a board > where car is the best match or I run out if board / easy targets. > > By then I might help out with porting the 440bx boards (is 440lx below?). > No worries CAR for i810/socket_370 will be coming on the next few days :-) I am really excited to get rid of that model_6xx clump-o-crap. Anders you should really get togethor with Keith on the 440bx CAR conversion. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 3

[PATCH] SeaBIOS VGA hooks
by Stefan Reinauer 11 Jun '10

11 Jun '10

SeaBIOS VGA hooks for Getac P470 and Roda RK886EX notebooks -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[PATCH] SeaBIOS CD/DVD abbreviations
by Stefan Reinauer 11 Jun '10

11 Jun '10

See Patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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Re PATCH: ECS P6IWP-Fe (Joseph Smith)
by Keith Hui 11 Jun '10

11 Jun '10

>>> On Wed, 09 Jun 2010 16:26:31 +0200, "anders(a)jenbo.dk"<anders(a)jenbo.dk> >>> wrote: >>>> Agreed, the only reason I haven't done car yet is that I haven't had a >>>> board where the best match to copy from used CAR. I defiantly hav plans >>> for >>>> updating all the boards I have to car but I am waiting til I hit a > board >>>> where car is the best match or I run out if board / easy targets. >>>> >>>> By then I might help out with porting the 440bx boards (is 440lx >> below?). >>>> >>> No worries CAR for i810/socket_370 will be coming on the next few days >> :-) >>> I am really excited to get rid of that model_6xx clump-o-crap. >>> >> Anders in case your curious, I will be porting the Intel D810E2CB. >> >> > Update: Almost done with this port :-) It will be done today. > I should write a blog about porting your board in 48 hours or less :-) > > My 1GHz PIII FC-PGA Copermine is not supported yet, so what better way to > kick off CAR for Socket 370 :-) > > Anyways, then I can dig out my box of 370's and start testing and sending > CAR patches for all of them. > > Oh, Anders don't forget to update wiki with your new port. > Just go ahead and enable CAR. It would use the intel CAR code already in the tree. It works for 6bx. Would be interesting to see if it works out of the box for Coppermine. The tiny little bit of L1 should be enough to get things going. ;-) Then it's to see if L2 is enabled without additional configuration like 6bx. I did put out patches to support the entire Slot1+370 lineup...

2 1

[h8dme-fam10] acquiring coreboot skills from scratch somewhat daunting
by Joe Korty 10 Jun '10

10 Jun '10

Hi, As a learning experience, I've been trying to port coreboot to the supermicro h8dme-2 w/ AMD K10. I've had not much luck either in the learning or the porting. In any case I've got coreboot up to where it is out of car and has started to clear memory, at which point it hangs. I presume this is because I failed to properly set up each socket's memory controller. Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: I started with the h8dmr_fam10 port since the h8dmr is identical, spec-wise, to the h8dme except that it has half the number of dimm slots. Also there is both K8 and K10 versions of coreboot for the h8dmr which in principle makes the study of the differences a good way to learn coreboot internals. In any case I have not been able to find where the info in spd_addr.h comes from, so I have not been able to make it correct for my board. How does one construct this table? In general, how does one construct devicetree.cb and the other tables from scratch? Is there an apprenticeship program somewhere, perhaps at some conference? How do people in general get their coreboot skill-set jump-started? Regards, Joe

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build service results for r5630
by repository service 10 Jun '10

10 Jun '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "monofin" checked in revision 5630 to the coreboot repository. This caused the following changes: Change Log: Fix a missing include file that was breaking the Traverse Geos build. Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Acked-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Build Log: Compilation of traverse:geos has been fixed If something broke during this checkin please be a pain in monofin's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5630 - trunk/src/mainboard/traverse/geos
by repository service 10 Jun '10

10 Jun '10

Author: monofin Date: Thu Jun 10 18:19:02 2010 New Revision: 5630 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5630 Log: Fix a missing include file that was breaking the Traverse Geos build. Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Acked-by: Edwin Beasant <edwin_beasant(a)virtensys.com> Modified: trunk/src/mainboard/traverse/geos/romstage.c Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Thu Jun 10 17:24:57 2010 (r5629) +++ trunk/src/mainboard/traverse/geos/romstage.c Thu Jun 10 18:19:02 2010 (r5630) @@ -19,6 +19,7 @@ */ #include <stdint.h> +#include <stdlib.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h>

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coreboot June 2010