coreboot June 2010

coreboot@coreboot.org

60 participants
222 discussions

Nokia IP530 Finaly back to life.......
by mbertens 21 Jun '10

21 Jun '10

hey guys, i got my Nokia IP530 back to life, i build my own: - syslinux 3.86, - kernel 2.6.34 - busybox 1.16.2 - udev 1.41 and it boots very nicelly. The problem was in the kernel/udev of the debian distro... Why that is i dont know, but i will test the complete system to see if there are any problems. It was a big learing curve for me, and maybe i would be a nice idea to put together a howto to setup a basic image for booting linux with coreboot that gives stable results. Marc

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Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR
by Joseph Smith 21 Jun '10

21 Jun '10

On Mon, 21 Jun 2010 09:23:36 -0600, "Myles Watson" <mylesgw(a)gmail.com> wrote: >> > Yes, it tries without the mask, i.e for 681 - 68f it tries 680. Then, > if >> > that does not match, it dies with "Unknown CPU". >> > There is no failsafe nor fallback involved. What makes you think there >> > is? It just means adding 1 entry to the table instead of 16. >> > >> Ok, if it is not a _fail_safe_ or _fall_back_ why don't we just always do >> this as a default? > My understanding is that barring errata, the stepping shouldn't matter. > Just in case it does, we check it. If there isn't a specific entry for the > stepping, we go to the "normal" case of using the ops without the stepping > information. > Correct, I get that. >> Why print out a "generic" message? > I think it just means "not-stepping-specific" > I like your verbage alot better than "generic". Or even "default" would be better than "generic". -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 2

Trac reminder: list of new ticket(s)
by coreboot tracker 21 Jun '10

21 Jun '10

1 0

[PATCH] i810 GFXUMA and Northbridge fixes
by Joseph Smith 20 Jun '10

20 Jun '10

Hello, This patch implements gfxuma on all supported i810 boards. Also some fix-ups to the i810 northbridge.c code. Abuild tested all i810 boards. Build and boot tested on soon to come i810e board. Signed-off by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 3

[commit] r5635 - in trunk/src: mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/ecs/p6iwp-fe mainboard/hp/e_vectra_p2706t mainboard/mitac/6513wu mainboard/msi/ms6178 mainboard/nec/powermate200...
by repository service 20 Jun '10

20 Jun '10

Author: linux_junkie Date: Sun Jun 20 20:59:40 2010 New Revision: 5635 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5635 Log: This patch implements GFXUMA on all supported i810 boards. Also some fix-ups to the i810 northbridge.c code. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/mew-am/Kconfig trunk/src/mainboard/asus/mew-am/mainboard.c trunk/src/mainboard/asus/mew-vm/Kconfig trunk/src/mainboard/asus/mew-vm/mainboard.c trunk/src/mainboard/ecs/p6iwp-fe/Kconfig trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig trunk/src/mainboard/hp/e_vectra_p2706t/mainboard.c trunk/src/mainboard/mitac/6513wu/Kconfig trunk/src/mainboard/mitac/6513wu/mainboard.c trunk/src/mainboard/msi/ms6178/Kconfig trunk/src/mainboard/msi/ms6178/mainboard.c trunk/src/mainboard/nec/powermate2000/Kconfig trunk/src/mainboard/nec/powermate2000/mainboard.c trunk/src/northbridge/intel/i82810/northbridge.c Modified: trunk/src/mainboard/asus/mew-am/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-am/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/asus/mew-am/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -28,6 +28,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/mew-am/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/asus/mew-am/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-AM Mainboard") }; Modified: trunk/src/mainboard/asus/mew-vm/Kconfig ============================================================================== --- trunk/src/mainboard/asus/mew-vm/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/asus/mew-vm/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -28,6 +28,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/mew-vm/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/asus/mew-vm/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -1,6 +1,12 @@ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("ASUS MEW-VM Mainboard") }; Modified: trunk/src/mainboard/ecs/p6iwp-fe/Kconfig ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/ecs/p6iwp-fe/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -29,6 +29,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("ECS P6IWP-Fe Mainboard") }; Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -31,6 +31,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/hp/e_vectra_p2706t/mainboard.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/hp/e_vectra_p2706t/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("HP e-Vectra P2706T Mainboard") }; Modified: trunk/src/mainboard/mitac/6513wu/Kconfig ============================================================================== --- trunk/src/mainboard/mitac/6513wu/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/mitac/6513wu/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -28,6 +28,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/mitac/6513wu/mainboard.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/mitac/6513wu/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("Mitac 6513WU Mainboard") }; Modified: trunk/src/mainboard/msi/ms6178/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6178/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/msi/ms6178/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -27,6 +27,8 @@ select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms6178/mainboard.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/msi/ms6178/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("MSI MS-6178 Mainboard") }; Modified: trunk/src/mainboard/nec/powermate2000/Kconfig ============================================================================== --- trunk/src/mainboard/nec/powermate2000/Kconfig Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/nec/powermate2000/Kconfig Sun Jun 20 20:59:40 2010 (r5635) @@ -28,6 +28,8 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/nec/powermate2000/mainboard.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/mainboard.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/mainboard/nec/powermate2000/mainboard.c Sun Jun 20 20:59:40 2010 (r5635) @@ -19,8 +19,14 @@ */ #include <device/device.h> +#include <boot/tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + struct chip_operations mainboard_ops = { CHIP_NAME("NEC PowerMate 2000 Mainboard") }; Modified: trunk/src/northbridge/intel/i82810/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.c Sat Jun 19 08:55:17 2010 (r5634) +++ trunk/src/northbridge/intel/i82810/northbridge.c Sun Jun 20 20:59:40 2010 (r5635) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +30,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include "chip.h" +#include <boot/tables.h> #include "northbridge.h" #include "i82810.h" @@ -100,6 +102,18 @@ return tolm; } +/* IGD UMA memory */ +uint64_t uma_memory_base=0, uma_memory_size=0; + +int add_northbridge_resources(struct lb_memory *mem) +{ + printk(BIOS_DEBUG, "Adding IGD UMA memory area\n"); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_base, uma_memory_size); + + return 0; +} + /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. * Note that 2 is a value which the DRP should never be programmed to. * Some size values appear twice, due to single-sided vs dual-sided banks. @@ -118,66 +132,67 @@ { device_t mc_dev; uint32_t pci_tolm; + int igd_memory = 0; pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; + if (!mc_dev) + return; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - unsigned long tomk, tolmk; - int idx; - int drp_value; - - /* First get the value for DIMM 0. */ - drp_value = pci_read_config8(mc_dev, DRP); - /* Translate it to MB and add to tomk. */ - tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]); - /* Now do the same for DIMM 1. */ - drp_value = drp_value >> 4; // >>= 4; //? mess with later - tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); - - printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk); - - /* Convert tomk from MB to KB. */ - tomk = tomk << 10; - -#if CONFIG_VIDEO_MB - /* Check for VGA reserved memory. */ - if (CONFIG_VIDEO_MB == 512) { - tomk -= 512; - printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "512KB"); - } else if (CONFIG_VIDEO_MB == 1) { - tomk -= 1024 ; - printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "1MB"); - } else { - printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "0MB"); - } -#endif + unsigned long tomk, tolmk; + int idx, drp_value; + u8 reg8; + + reg8 = pci_read_config8(mc_dev, SMRAM); + reg8 &= 0xc0; + + switch (reg8) { + case 0xc0: + igd_memory = 1024; + printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory); + break; + case 0x80: + igd_memory = 512; + printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory); + break; + default: + igd_memory = 0; + printk(BIOS_DEBUG, "No IGD UMA Memory\n"); + break; + } - /* Compute the top of Low memory. */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - - /* Report the memory regions. */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + /* Get the value for DIMM 0 and translate it to MB. */ + drp_value = pci_read_config8(mc_dev, DRP); + tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0x0f]); + /* Get the value for DIMM 1 and translate it to MB. */ + drp_value = drp_value >> 4; + tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); + /* Convert tomk from MB to KB. */ + tomk = tomk << 10; + tomk -= igd_memory; + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = igd_memory * 1024ULL; + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + + /* Compute the top of low memory. */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); #if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; #endif - } assign_resources(dev->link_list); }

1 0

[patch] Added dependency checking for the USB EHCI debug Kconfig option
by Cristi Magherusan 20 Jun '10

20 Jun '10

See attached patch. I had to add that ifdef because config.h didn't have defined the CONFIG_USBDEBUG_DIRECT option and compilation failed. If anyone has an idea how I can get it defined there, I'm all ears. Signed-off-by: Cristi Magherusan <cristi.magherusan(a)net.utcluj.ro> -- Cristi Măgherușan, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

2 2

GSOC AMD 7xx Mainboard mass-porting
by bari 20 Jun '10

20 Jun '10

Wang, If you need any AMD 7xx boards donated to your GSOC project that are only available in Europe or USA, please let us know. -Bari

4 5

Booting problem
by mbertens 19 Jun '10

19 Jun '10

Hi all, i made two logs with one disk one log is where disk boots in the donor PC and there i see the difference that there are messages send to the console (without a timestamp) those do not show up in the log with coreboot. Both logs are made in the serial console, with the same kernel parameter "console=ttyS0,115200" so there should not be a difference! Has anyone an idea where this problem comes from ? Marc

1 0

[commit] r5634 - trunk/src/southbridge/amd/sb700
by repository service 19 Jun '10

19 Jun '10

Author: zbao Date: Sat Jun 19 08:55:17 2010 New Revision: 5634 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5634 Log: Trivial. Cleaning up about the blank line. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/southbridge/amd/sb700/sb700.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sm.c trunk/src/southbridge/amd/sb700/sb700_usb.c Modified: trunk/src/southbridge/amd/sb700/sb700.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700.c Sat Jun 19 08:55:17 2010 (r5634) @@ -120,21 +120,21 @@ printk(BIOS_DEBUG, "sb700_enable()\n"); -/* -* 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 -* 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 -* 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 -* 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 -* 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 -* 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 -* 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 -* 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 -* 0:14.0 SMBUS 0 -* 0:14.1 IDE 1 -* 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 -* 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 -* 0:14.4 PCI 4 -*/ + /* + * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 + * 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 + * 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 + * 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 + * 0:13.0 OHCI0-USB2 bit 4 of sm_dev 0x68 + * 0:13.1 OHCI1-USB2 bit 5 of sm_dev 0x68 + * 0:13.2 EHCI-USB2 bit 6 of sm_dev 0x68 + * 0:14.5 OHCI0-USB3 bit 7 of sm_dev 0x68 + * 0:14.0 SMBUS 0 + * 0:14.1 IDE 1 + * 0:14.2 HDA bit 3 of pm_io 0x59 : 1 - enable, default + 32 * 4 + * 0:14.3 LPC bit 20 of sm_dev 0x64 : 0 - disable, default + 32 * 1 + * 0:14.4 PCI 4 + */ if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; @@ -143,6 +143,7 @@ vendorid = dev->vendor; deviceid = dev->device; } + bus_dev = dev->bus->dev; if ((bus_dev->vendor == PCI_VENDOR_ID_ATI) && (bus_dev->device == PCI_DEVICE_ID_ATI_SB700_PCI)) { @@ -156,7 +157,6 @@ case 5 << 3: ; } - return; } Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Sat Jun 19 08:55:17 2010 (r5634) @@ -58,7 +58,6 @@ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); - } static void sb700_lpc_read_resources(device_t dev) @@ -100,7 +99,6 @@ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, 0xA0); pci_write_config32(dev, 0xA0, res->base | 1 << 1); - } /** Modified: trunk/src/southbridge/amd/sb700/sb700_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sm.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_sm.c Sat Jun 19 08:55:17 2010 (r5634) @@ -72,7 +72,6 @@ dword |= 1 << 13; pci_write_config16(dev, 0x64, dword); - /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */ /* rpr 2.1 Enabling Legacy Interrupt */ dword = pci_read_config8(dev, 0x62); @@ -282,6 +281,7 @@ return do_smbus_write_byte(res->base, device, address, val); } + static struct smbus_bus_operations lops_smbus_bus = { .recv_byte = lsmbus_recv_byte, .send_byte = lsmbus_send_byte, @@ -335,10 +335,9 @@ res->gran = 8; res->flags = IORESOURCE_IO | IORESOURCE_FIXED; - compact_resources(dev); - } + static void sb700_sm_set_resources(struct device *dev) { struct resource *res; @@ -346,7 +345,6 @@ pci_dev_set_resources(dev); - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ byte = pm_ioread(0x52); byte |= 1 << 6; @@ -365,6 +363,7 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; + static struct device_operations smbus_ops = { .read_resources = sb700_sm_read_resources, .set_resources = sb700_sm_set_resources, @@ -374,6 +373,7 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_ATI, Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Thu Jun 17 18:16:56 2010 (r5633) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Sat Jun 19 08:55:17 2010 (r5634) @@ -42,7 +42,6 @@ byte |= 0xFF; pci_write_config8(sm_dev, 0x68, byte); - /* RPR 6.2 Enables the USB PME Event,Enable USB resume support */ byte = pm_ioread(0x61); byte |= 1 << 6; @@ -188,7 +187,6 @@ set_ehci_base(base); report_resource_stored(dev, res, ""); #endif - } static struct device_operations usb_ops = { @@ -205,6 +203,7 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, }; + static const struct pci_driver usb_1_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_ATI,

1 0

CS5536 write MSR and trigger I/O error
by Li Gen 18 Jun '10

18 Jun '10

Hi, I have a main board with cs5536, and need to write the bios. During the pci devices scaning, I can found cs5536, and the device number is 9. So I use following codes to read and write MSR to configure CS5536. However, I found that I can successfully read the MSR content, but when I write the same content to the same MSR, the I/O error was happened after writing the low data to 0xf8. Then I try to write the high data first and then write the low data, I found that writing the high data will not trigger I/O error, only writing low data will trigger I/O error. Is there something else I forgot to initialize before writing MSR? and what do I do something wrong? Thank you! #define CS5536_SB_MSR_BASE (0x00000000) pci_write(CS5536_PCI_CONF_BASE+0xf4, CS5536_SB_MSR_BASE | 0x10) ; // OK pci_read(CS5536_PCI_CONF_BASE+0xf8, &low ) ; // OK low =00000003h pci_read(CS5536_PCI_CONF_BASE+0xfc, &hi ) ; // OK hi = 44000030h pci_write(CS5536_PCI_CONF_BASE+0xf4, CS5536_SB_MSR_BASE | 0x10) ; // OK pci_write(CS5536_PCI_CONF_BASE+0xf8, low ) ; // I/O Error, Why? pci_write(CS5536_PCI_CONF_BASE+0xfc, hi ) ; // I/O Error, Why? Q: Is there something else I forgot to initialize before writing MSR? and what do I do something wrong?

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coreboot June 2010