Hello, I have a strange thing happening on the i810 port I am working on. When I power the board on i do not get any serial console from coreboot. VGA turns on and works fine, but no serial output. The strange part is if I push the reset button, serial console comes up and works fine until the next power off. The SuperIO is SMSC LPC47M102 and I am using superio/smsc/smscsuperio. Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated.
On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello, I have a strange thing happening on the i810 port I am working on. When I power the board on i do not get any serial console from coreboot. VGA turns on and works fine, but no serial output. The strange part is if I push the reset button, serial console comes up and works fine until the next power off. The SuperIO is SMSC LPC47M102 and I am using superio/smsc/smscsuperio. Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated.
Your Super IO chip is not initialized correctly. Compare the register output after reset and from cold start. Did you run the same coreboot image already when you pressed the reset button, or did you initially boot with the BIOS?
Stefan
On Tue, 15 Jun 2010 14:13:24 +0200, Stefan Reinauer stefan.reinauer@coresystems.de wrote:
On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello, I have a strange thing happening on the i810 port I am working on. When
I
power the board on i do not get any serial console from coreboot. VGA
turns
on and works fine, but no serial output. The strange part is if I push
the
reset button, serial console comes up and works fine until the next
power
off. The SuperIO is SMSC LPC47M102 and I am using
superio/smsc/smscsuperio.
Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated.
Your Super IO chip is not initialized correctly. Compare the register output after reset and from cold start.
You mean with superiotool?
Did you run the same coreboot image already when you pressed the reset button, or did you initially boot with the BIOS?
Yes, same coreboot image.
It would seem that the RAM code is right but the "early setup" code is wrong. It's working because the "early setup" is probably having no effect whatsoever ...
ron
On Tue, 15 Jun 2010 05:30:07 -0700, ron minnich rminnich@gmail.com wrote:
It would seem that the RAM code is right but the "early setup" code is wrong. It's working because the "early setup" is probably having no effect whatsoever ...
Hmm, There is a src/superio/smsc/lpc47m10x maybe I will try that and see if it works. Maybe the src/superio/smsc/smscsuperio does not do early_serial correctly for this chip? FYI, after I push the reset button and can see the bootlog, it appears that the superio is detected and setup correctly.
On 6/15/10 2:41 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 05:30:07 -0700, ron minnich rminnich@gmail.com wrote:
It would seem that the RAM code is right but the "early setup" code is wrong. It's working because the "early setup" is probably having no effect whatsoever ...
Hmm, There is a src/superio/smsc/lpc47m10x maybe I will try that and see if it works.
That driver seems non functional. It looks like it was added for the sun ultra 40 board but then romstage.c of that machine includes init code of another superio ....
Maybe the src/superio/smsc/smscsuperio does not do early_serial correctly for this chip?
Google tells me that this document knows the answer: http://www.smsc.com/media/Downloads_Public/Data_Sheets/47m10x.pdf
FYI, after I push the reset button and can see the bootlog, it appears that the superio is detected and setup correctly.
Does pushing the superio button help when you're still in FILO, too?
Stefan
On Tue, 15 Jun 2010 15:50:51 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 6/15/10 2:41 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 05:30:07 -0700, ron minnich rminnich@gmail.com
wrote:
It would seem that the RAM code is right but the "early setup" code is wrong. It's working because the "early setup" is probably having no effect whatsoever ...
Hmm, There is a src/superio/smsc/lpc47m10x maybe I will try that and see if
it
works.
That driver seems non functional. It looks like it was added for the sun ultra 40 board but then romstage.c of that machine includes init code of another superio ....
Yeh I noticed that it is a half port....
Maybe the src/superio/smsc/smscsuperio does not do early_serial
correctly
for this chip?
Google tells me that this document knows the answer: http://www.smsc.com/media/Downloads_Public/Data_Sheets/47m10x.pdf
Yes, of course I have the datasheeet, silly :-)
FYI, after I push the reset button and can see the bootlog, it appears that the superio is detected and setup correctly.
Does pushing the superio button help when you're still in FILO, too?
Hmm, not sure I usually push the reset before I get to payload. I can check.
On 6/15/10 2:25 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 14:13:24 +0200, Stefan Reinauer stefan.reinauer@coresystems.de wrote:
On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello, I have a strange thing happening on the i810 port I am working on. When
I
power the board on i do not get any serial console from coreboot. VGA
turns
on and works fine, but no serial output. The strange part is if I push
the
reset button, serial console comes up and works fine until the next
power
off. The SuperIO is SMSC LPC47M102 and I am using
superio/smsc/smscsuperio.
Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated.
Your Super IO chip is not initialized correctly. Compare the register output after reset and from cold start.
You mean with superiotool?
That might already be too late
Did you run the same coreboot image already when you pressed the reset button, or did you initially boot with the BIOS?
Yes, same coreboot image.
So booting Linux fixes the issue? Does serial console in linux work on a cold boot?
On Tue, 15 Jun 2010 15:39:25 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 6/15/10 2:25 PM, Joseph Smith wrote:
On Tue, 15 Jun 2010 14:13:24 +0200, Stefan Reinauer stefan.reinauer@coresystems.de wrote:
On 6/15/10 1:38 PM, Joseph Smith wrote:
Hello, I have a strange thing happening on the i810 port I am working on.
When
I
power the board on i do not get any serial console from coreboot. VGA
turns
on and works fine, but no serial output. The strange part is if I push
the
reset button, serial console comes up and works fine until the next
power
off. The SuperIO is SMSC LPC47M102 and I am using
superio/smsc/smscsuperio.
Just wondering if anyone else has encountered this before. Any help / thoughts would be appreciated.
Your Super IO chip is not initialized correctly. Compare the register output after reset and from cold start.
You mean with superiotool?
That might already be too late
Did you run the same coreboot image already when you pressed the reset button, or did you initially boot with the BIOS?
Yes, same coreboot image.
So booting Linux fixes the issue? Does serial console in linux work on a cold boot?
I don't think there is really a issue. The post card spins through all the post codes just fine, vga starts up and it boots into Linux just fine. When I cold boot it, if I hit the reset button before Linux starts, it restarts with coreboot serial console just fine. I have not tried Linux serial console mode yet. I think something wrong is happening at the early_serial point. I wonder if it could be a SB gpio or SB PM event to wake the serial port? The devices on the LPC47M102 do support PM wake-up events, So I wonder if it is related?
On 6/15/10 4:07 PM, Joseph Smith wrote:
When I cold boot it, if I hit the reset button before Linux starts, it restarts with coreboot serial console just fine.
Hm...
Maybe 0x2e/0x4e are mapped to LPC after the SuperIO is configured (and that mapping survives a reset)... that would be a southbridge init issue.
Or, the hardware has to stabilize after power on before you can configure the SuperIO.
Stefan
On Tue, 15 Jun 2010 16:16:46 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 6/15/10 4:07 PM, Joseph Smith wrote:
When I cold boot it, if I hit the reset button before Linux starts, it
restarts
with coreboot serial console just fine.
Hm...
Maybe 0x2e/0x4e are mapped to LPC after the SuperIO is configured (and that mapping survives a reset)... that would be a southbridge init issue.
Hmm, This is interesting. The first time I booted it, I had copied romstage from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it came to detecting and inializing the superio, I got all kinds of errors from coreboot about device not found.
So I changed it to 0x2e as described in the datasheet and detected with superiotool(vendor bios), and that is when this problem started. But now coreboot is happy, detects the device and the resource allocator is happy, I just do not get early_serial on cold boot.
This is weird!
Or, the hardware has to stabilize after power on before you can configure the SuperIO.
Maybe?
On 6/15/10 4:28 PM, Joseph Smith wrote:
Hmm, This is interesting. The first time I booted it, I had copied romstage from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it came to detecting and inializing the superio, I got all kinds of errors from coreboot about device not found.
So I changed it to 0x2e as described in the datasheet and detected with superiotool(vendor bios), and that is when this problem started. But now coreboot is happy, detects the device and the resource allocator is happy, I just do not get early_serial on cold boot.
This is weird!
The above define does not change any behavior in stage 2 / the resource allocator. Try disabling romstage smsc initialization completely and see if that helps.
On Tue, 15 Jun 2010 16:32:21 +0200, Stefan Reinauer stepan@coresystems.de wrote:
On 6/15/10 4:28 PM, Joseph Smith wrote:
Hmm, This is interesting. The first time I booted it, I had copied
romstage
from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it
came
to detecting and inializing the superio, I got all kinds of errors from coreboot about device not found.
So I changed it to 0x2e as described in the datasheet and detected with superiotool(vendor bios), and that is when this problem started. But now coreboot is happy, detects the device and the resource allocator is
happy,
I just do not get early_serial on cold boot.
This is weird!
The above define does not change any behavior in stage 2 / the resource allocator. Try disabling romstage smsc initialization completely and see if that helps.
Are you sure about that? Attached is a bootlog with it set to 0x4e. Note the:
Found SMSC Super I/O (ID=0xff, rev=0xff)
With it set to 0x2e:
Found SMSC Super I/O (ID=0x59, rev=0x01)
On Tue, 15 Jun 2010 10:28:51 -0400, Joseph Smith joe@settoplinux.org wrote:
On Tue, 15 Jun 2010 16:16:46 +0200, Stefan Reinauer
wrote:
On 6/15/10 4:07 PM, Joseph Smith wrote:
When I cold boot it, if I hit the reset button before Linux starts, it
restarts
with coreboot serial console just fine.
Hm...
Maybe 0x2e/0x4e are mapped to LPC after the SuperIO is configured (and that mapping survives a reset)... that would be a southbridge init
issue.
Hmm, This is interesting. The first time I booted it, I had copied
romstage
from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it
came
to detecting and inializing the superio, I got all kinds of errors from coreboot about device not found.
So I changed it to 0x2e as described in the datasheet and detected with superiotool(vendor bios), and that is when this problem started. But now coreboot is happy, detects the device and the resource allocator is
happy,
I just do not get early_serial on cold boot.
This is weird!
Or, the hardware has to stabilize after power on before you can configure the SuperIO.
Maybe?
Hmm from page 142 in the datasheet, I need to figure out of there is a pull-down resistor connected to the SYSOPT pin to use 0x2e or if there is a pull-up resistor connected to the SYSOPT pin to use 0x4e. And once powered up the configuration port base address can be changed through CR26 and CR27.
I bet you that there is a pull-up resistor connected to the SYSOPT pin and 0x4e is supposed to be used. And the vendor bios changes this to 0x2e at some point. That is what is throwing me off!
So I will try:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
and change all the devices in devicetree.cb to 4e.
My question is does it need to get changed to 0x2e at some point? Or can I just leave it at 0x4e? Will it matter to OS?
Thanks for all the brainstorming help Stefan and Ron.
On Tue, Jun 15, 2010 at 8:54 AM, Joseph Smith joe@settoplinux.org wrote:
My question is does it need to get changed to 0x2e at some point? Or can I just leave it at 0x4e? Will it matter to OS?
Thanks for all the brainstorming help Stefan and Ron.
Should not matter to OS IMHO ... the OS can probe for it pretty easily.
That's totally wacky if the vendor BIOS is doing that, but it's not the worst such thing we've seen (by far).
ron
On 06/15/2010 11:54 AM, Joseph Smith wrote:
On Tue, 15 Jun 2010 10:28:51 -0400, Joseph Smithjoe@settoplinux.org wrote:
On Tue, 15 Jun 2010 16:16:46 +0200, Stefan Reinauer
wrote:
On 6/15/10 4:07 PM, Joseph Smith wrote:
When I cold boot it, if I hit the reset button before Linux starts, it
restarts
with coreboot serial console just fine.
Hm...
Maybe 0x2e/0x4e are mapped to LPC after the SuperIO is configured (and that mapping survives a reset)... that would be a southbridge init
issue.
Hmm, This is interesting. The first time I booted it, I had copied
romstage
from another board that had:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
And I got coreboot serial console (early_serial) just fine but when it
came
to detecting and inializing the superio, I got all kinds of errors from coreboot about device not found.
So I changed it to 0x2e as described in the datasheet and detected with superiotool(vendor bios), and that is when this problem started. But now coreboot is happy, detects the device and the resource allocator is
happy,
I just do not get early_serial on cold boot.
This is weird!
Or, the hardware has to stabilize after power on before you can configure the SuperIO.
Maybe?
Hmm from page 142 in the datasheet, I need to figure out of there is a pull-down resistor connected to the SYSOPT pin to use 0x2e or if there is a pull-up resistor connected to the SYSOPT pin to use 0x4e. And once powered up the configuration port base address can be changed through CR26 and CR27.
I bet you that there is a pull-up resistor connected to the SYSOPT pin and 0x4e is supposed to be used. And the vendor bios changes this to 0x2e at some point. That is what is throwing me off!
So I will try:
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
and change all the devices in devicetree.cb to 4e.
My question is does it need to get changed to 0x2e at some point? Or can I just leave it at 0x4e? Will it matter to OS?
Thanks for all the brainstorming help Stefan and Ron.
Yup that did it :-) Looks like SYSOPT had a pull-up resistor so 0x4e works great.
But there is one other small issue. Looks like the resource allocater is not allocating any space for device 43.a the Runtime Registers.
My devicetree.cb looks like: device pnp 4e.a on # Runtime registers io 0x60 = 0x800 end
But my bootlog (attached) shows: PNP: 004e.a resource base 800 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
skipping PNP: 004e.a@60 fixed resource, size=0!
PNP: 004e.a 60 <- [0x0000000800 - 0x00000007ff] size 0x00000000 gran 0x00 io
PNP: 004e.a resource base 800 size 0 align 0 gran 0 limit 0 flags e0000100 index 60
Is it supposed to look like that?
On 6/16/10 12:37 AM, Joseph Smith wrote:
But there is one other small issue. Looks like the resource allocater is not allocating any space for device 43.a the Runtime Registers.
My devicetree.cb looks like: device pnp 4e.a on # Runtime registers io 0x60 = 0x800 end
But my bootlog (attached) shows: PNP: 004e.a resource base 800 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
It's probably missing a correct entry in the pnp_dev_info structure of the superio.
Stefan
On 06/15/2010 06:42 PM, Stefan Reinauer wrote:
On 6/16/10 12:37 AM, Joseph Smith wrote:
But there is one other small issue. Looks like the resource allocater is not allocating any space for device 43.a the Runtime Registers.
My devicetree.cb looks like: device pnp 4e.a on # Runtime registers io 0x60 = 0x800 end
But my bootlog (attached) shows: PNP: 004e.a resource base 800 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
It's probably missing a correct entry in the pnp_dev_info structure of the superio.
Ah yes, looks like my ip1000 that uses the same code does the same thing, I will have to fix that :-)
-
Joseph Smith -
ron minnich -
Stefan Reinauer -
Stefan Reinauer