coreboot March 2010

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VGA rom can not be loaded by SEABIOS
by Wang, Qingpei 17 Mar '10

17 Mar '10

Hi, With the latest version of seabios, the vgarom can not be loaded correctly. I find that in the code seabios/src/optionrom.c vga_setup Can to load the vga rom from cbfs. The detail log is attached. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

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[commit] r5251 - in trunk/src: cpu/amd/model_fxx include/cpu/amd mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah ma...
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 05:40:15 2010 New Revision: 5251 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5251 Log: trivial warning fixes, mostly for ACPI code Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/include/cpu/amd/microcode.h trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/irq_tables.c trunk/src/mainboard/iwill/dk8_htx/mptable.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/via/epia-m/acpi_tables.c trunk/src/mainboard/via/epia-m700/acpi_tables.c trunk/src/mainboard/via/epia-n/acpi_tables.c trunk/src/mainboard/via/vt8454c/acpi_tables.c trunk/src/southbridge/amd/amd8111/amd8111_acpi.c trunk/src/southbridge/amd/amd8111/amd8111_nic.c trunk/src/superio/winbond/w83627hf/superio.c Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Wed Mar 17 05:40:15 2010 (r5251) @@ -21,6 +21,7 @@ #include "../../../northbridge/amd/amdk8/amdk8.h" #include <cpu/amd/model_fxx_rev.h> +#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> @@ -462,8 +463,6 @@ } -extern void model_fxx_update_microcode(unsigned cpu_deviceid); - #if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; #endif Modified: trunk/src/include/cpu/amd/microcode.h ============================================================================== --- trunk/src/include/cpu/amd/microcode.h Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/include/cpu/amd/microcode.h Wed Mar 17 05:40:15 2010 (r5251) @@ -2,5 +2,6 @@ #define CPU_AMD_MICORCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); +void model_fxx_update_microcode(unsigned cpu_deviceid); #endif /* CPU_AMD_MICROCODE_H */ Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -93,7 +93,7 @@ extern void update_ssdt(void *ssdt); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { u8 *PCI; u8 *HCIN; @@ -251,7 +251,7 @@ current += ((acpi_header_t *)AmlCode)->length; memcpy((void *)dsdt,(void *)AmlCode, \ ((acpi_header_t *)AmlCode)->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment current = ( current + 0x07) & -0x08; Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/pistachio/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -156,7 +156,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; @@ -200,8 +200,6 @@ acpi_header_t *ssdtx; unsigned char *p; - unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM]; - int i; get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn @@ -313,7 +311,7 @@ current += ((acpi_header_t *)AmlCode)->length; memcpy((void *)dsdt,(void *)AmlCode, \ ((acpi_header_t *)AmlCode)->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FDAT */ printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -165,7 +165,7 @@ extern void update_ssdt(void *ssdt); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { u8 *PCI; u8 *HCIN; @@ -323,7 +323,7 @@ current += ((acpi_header_t *)AmlCode)->length; memcpy((void *)dsdt,(void *)AmlCode, \ ((acpi_header_t *)AmlCode)->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment current = ( current + 0x07) & -0x08; Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -123,7 +123,7 @@ ((acpi_header_t *) AmlCode)->length); dsdt->checksum = 0; /* Don't trust iasl to get this right. */ dsdt->checksum = acpi_checksum(dsdt, dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -138,7 +138,7 @@ ((acpi_header_t *) AmlCode)->length); dsdt->checksum = 0; /* Don't trust iasl to get this right. */ dsdt->checksum = acpi_checksum(dsdt, dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -148,7 +148,7 @@ ((acpi_header_t *) AmlCode)->length); dsdt->checksum = 0; /* Don't trust iasl to get this right. */ dsdt->checksum = acpi_checksum(dsdt, dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -99,7 +99,7 @@ int j = 0; for(i=1; i< sysconf.hc_possible_num; i++) { - unsigned d; + unsigned d = 0; if(!(sysconf.pci1234[i] & 0x1) ) continue; // 8131 need to use +4 @@ -159,7 +159,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; @@ -203,8 +203,6 @@ acpi_header_t *ssdtx; unsigned char *p; - unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM]; - int i; get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn @@ -318,7 +316,7 @@ current += ((acpi_header_t *)AmlCode)->length; memcpy((void *)dsdt,(void *)AmlCode, \ ((acpi_header_t *)AmlCode)->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FDAT */ printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/iwill/dk8_htx/irq_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/irq_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/iwill/dk8_htx/irq_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -58,7 +58,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/mptable.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/iwill/dk8_htx/mptable.c Wed Mar 17 05:40:15 2010 (r5251) @@ -12,7 +12,7 @@ extern void get_bus_conf(void); -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "IWILL "; Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/kontron/kt690/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -152,7 +152,7 @@ ((acpi_header_t *) AmlCode)->length); dsdt->checksum = 0; /* Don't trust iasl to get this right. */ dsdt->checksum = acpi_checksum(dsdt, dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -101,7 +101,7 @@ extern void get_bus_conf(void); -void update_ssdtx(void *ssdtx, int i) +static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; uint8_t *HCIN; Modified: trunk/src/mainboard/via/epia-m/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-m/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/via/epia-m/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -79,7 +79,7 @@ memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length); dsdt->checksum = 0; // don't trust intel iasl compiler to get this right dsdt->checksum = acpi_checksum(dsdt,dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Modified: trunk/src/mainboard/via/epia-m700/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/via/epia-m700/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -163,7 +163,7 @@ ((acpi_header_t *) AmlCode_dsdt)->length); dsdt->checksum = 0; /* Don't trust iasl to get this right. */ dsdt->checksum = acpi_checksum(dsdt, dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Modified: trunk/src/mainboard/via/epia-n/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-n/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/via/epia-n/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -165,7 +165,7 @@ memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length); dsdt->checksum = 0; // don't trust intel iasl compiler to get this right dsdt->checksum = acpi_checksum(dsdt,dsdt->length); - printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; Modified: trunk/src/mainboard/via/vt8454c/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/acpi_tables.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/mainboard/via/vt8454c/acpi_tables.c Wed Mar 17 05:40:15 2010 (r5251) @@ -187,7 +187,7 @@ dsdt->checksum = 0; // don't trust intel iasl compiler to get this right dsdt->checksum = acpi_checksum(dsdt, dsdt->length); #endif - printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, + printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); printk_debug("ACPI: * FADT\n"); Modified: trunk/src/southbridge/amd/amd8111/amd8111_acpi.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_acpi.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/southbridge/amd/amd8111/amd8111_acpi.c Wed Mar 17 05:40:15 2010 (r5251) @@ -73,12 +73,12 @@ static void acpi_init(struct device *dev) { uint8_t byte; - uint16_t word; uint16_t pm10_bar; uint32_t dword; int on; #if 0 + uint16_t word; printk_debug("ACPI: disabling NMI watchdog.. "); byte = pci_read_config8(dev, 0x49); pci_write_config8(dev, 0x49, byte | (1<<2)); @@ -98,9 +98,8 @@ word = pci_read_config16(dev, 0x46); pci_write_config16(dev, 0x46, word | (1<<9)); printk_debug("done.\n"); - - #endif + /* To enable the register 0xcf9 in the IO space * bit [D5] is set in the amd8111 configuration register. * The config. reg. is devBx41. Register 0xcf9 allows Modified: trunk/src/southbridge/amd/amd8111/amd8111_nic.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_nic.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/southbridge/amd/amd8111/amd8111_nic.c Wed Mar 17 05:40:15 2010 (r5251) @@ -54,12 +54,12 @@ /* Hard Reset PHY */ printk_debug("Reseting PHY... "); if (conf->phy_lowreset) { - write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); + write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { - write32((void *)(mmio + CMD3), VAL0 | RESET_PHY); + write32((mmio + CMD3), VAL0 | RESET_PHY); } mdelay(15); - write32((void *)(mmio + CMD3), RESET_PHY); + write32((mmio + CMD3), RESET_PHY); printk_debug("Done\n"); } Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Wed Mar 17 05:38:22 2010 (r5250) +++ trunk/src/superio/winbond/w83627hf/superio.c Wed Mar 17 05:40:15 2010 (r5251) @@ -57,6 +57,7 @@ return inb(port_base + 1); } +#if CONFIG_EXPERT static void w83627hf_16_bit_addr_qual(device_t dev) { int port = dev->path.pnp.port >> 8; @@ -66,6 +67,7 @@ outb(inb(port + 1) | 0x80, port + 1); pnp_exit_ext_func_mode(dev); } +#endif static void enable_hwm_smbus(device_t dev) {

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[commit] r5250 - trunk/src/devices
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 05:38:22 2010 New Revision: 5250 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5250 Log: drop shadow variable from hypertransport code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/hypertransport.c Modified: trunk/src/devices/hypertransport.c ============================================================================== --- trunk/src/devices/hypertransport.c Wed Mar 17 05:37:52 2010 (r5249) +++ trunk/src/devices/hypertransport.c Wed Mar 17 05:38:22 2010 (r5250) @@ -551,7 +551,6 @@ #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; - device_t last_func = 0; flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;

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[commit] r5249 - trunk/src/southbridge/intel/i82801dx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 05:37:52 2010 New Revision: 5249 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5249 Log: Actually enable HPET Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 05:04:20 2010 (r5248) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 05:37:52 2010 (r5249) @@ -193,7 +193,8 @@ */ reg32 &= ~(3 << 15); /* Clear it */ reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); }

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build service results for r5239
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5239 to the coreboot repository. This caused the following changes: Change Log: remove more warnings, and fix some boards (watchdog.h) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of tyan:s2735 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5248 - in trunk/src/devices/oprom/yabel: . compat
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 05:04:20 2010 New Revision: 5248 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5248 Log: Clean up warnings in yabel vbe code. No more warnings on the IP1000 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/oprom/yabel/compat/functions.c trunk/src/devices/oprom/yabel/vbe.c trunk/src/devices/oprom/yabel/vbe.h Modified: trunk/src/devices/oprom/yabel/compat/functions.c ============================================================================== --- trunk/src/devices/oprom/yabel/compat/functions.c Wed Mar 17 05:03:22 2010 (r5247) +++ trunk/src/devices/oprom/yabel/compat/functions.c Wed Mar 17 05:04:20 2010 (r5248) @@ -18,6 +18,7 @@ #include <device/device.h> #include "../debug.h" #include "../biosemu.h" +#include "../vbe.h" #include "../compat/time.h" #define VMEM_SIZE (1024 * 1024) /* 1 MB */ @@ -32,10 +33,6 @@ u8* vmem = NULL; #endif -#if CONFIG_BOOTSPLASH -void vbe_set_graphics(void); -#endif - void run_bios(struct device * dev, unsigned long addr) { Modified: trunk/src/devices/oprom/yabel/vbe.c ============================================================================== --- trunk/src/devices/oprom/yabel/vbe.c Wed Mar 17 05:03:22 2010 (r5247) +++ trunk/src/devices/oprom/yabel/vbe.c Wed Mar 17 05:04:20 2010 (r5248) @@ -31,6 +31,7 @@ #include "mem.h" #include "interrupt.h" #include "device.h" +#include "vbe.h" #include <cbfs.h> @@ -153,6 +154,7 @@ return 0; // successfull init } +#if CONFIG_BOOTSPLASH || CONFIG_EXPERT // VBE Function 00h static u8 vbe_info(vbe_info_t * info) @@ -299,7 +301,9 @@ } return 0; } +#endif +#if CONFIG_EXPERT //VBE Function 08h static u8 vbe_set_palette_format(u8 format) @@ -762,6 +766,7 @@ } return 0; } +#endif #if CONFIG_BOOTSPLASH vbe_mode_info_t mode_info; @@ -769,7 +774,6 @@ void vbe_set_graphics(void) { u8 rval; - int i; vbe_info_t info; rval = vbe_info(&info); @@ -802,7 +806,7 @@ /* Switching Intel IGD to 1MB video memory will break this. Who * cares. */ - int imagesize = 1024*768*2; + // int imagesize = 1024*768*2; unsigned char *jpeg = cbfs_find_file("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH); if (!jpeg) { Modified: trunk/src/devices/oprom/yabel/vbe.h ============================================================================== --- trunk/src/devices/oprom/yabel/vbe.h Wed Mar 17 05:03:22 2010 (r5247) +++ trunk/src/devices/oprom/yabel/vbe.h Wed Mar 17 05:04:20 2010 (r5248) @@ -13,4 +13,10 @@ #ifndef _BIOSEMU_VBE_H_ #define _BIOSEMU_VBE_H_ +struct lb_framebuffer; + +void vbe_set_graphics(void); +void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +void vbe_textmode_console(void); + #endif

1 0

[commit] r5247 - trunk/src/lib
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 05:03:22 2010 New Revision: 5247 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5247 Log: clean up shadow variables in jpeg decoder. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/lib/jpeg.c Modified: trunk/src/lib/jpeg.c ============================================================================== --- trunk/src/lib/jpeg.c Wed Mar 17 04:44:45 2010 (r5246) +++ trunk/src/lib/jpeg.c Wed Mar 17 05:03:22 2010 (r5247) @@ -160,7 +160,7 @@ #define dec_huffdc (dhuff + 0) #define dec_huffac (dhuff + 2) -static struct in in; +static struct in glob_in; static int readtables(int till) { @@ -248,7 +248,7 @@ { int i; - if (dec_readmarker(&in) != info.rm) + if (dec_readmarker(&glob_in) != info.rm) return -1; info.nm = info.dri; info.rm = (info.rm + 1) & ~0x08; @@ -356,7 +356,7 @@ idctqtab(quant[dscans[1].tq], decdata->dquant[1]); idctqtab(quant[dscans[2].tq], decdata->dquant[2]); initcol(decdata->dquant); - setinput(&in, datap); + setinput(&glob_in, datap); #if 0 /* landing zone */ @@ -376,7 +376,7 @@ if (dec_checkmarker()) return ERR_WRONG_MARKER; - decode_mcus(&in, decdata->dcts, 6, dscans, max); + decode_mcus(&glob_in, decdata->dcts, 6, dscans, max); idct(decdata->dcts, decdata->out, decdata->dquant[0], IFIX(128.5), max[0]); idct(decdata->dcts + 64, decdata->out + 64, decdata->dquant[0], IFIX(128.5), max[1]); idct(decdata->dcts + 128, decdata->out + 128, decdata->dquant[0], IFIX(128.5), max[2]); @@ -401,7 +401,7 @@ } } - m = dec_readmarker(&in); + m = dec_readmarker(&glob_in); if (m != M_EOI) return ERR_NO_EOI; @@ -664,7 +664,7 @@ 6, 13, 17, 24, 32, 38, 47, 49 }; -void idct(int *in, int *out, PREC *quant, PREC off, int max) +void idct(int *in, int *out, PREC *lquant, PREC off, int max) { PREC t0, t1, t2, t3, t4, t5, t6, t7, t; PREC tmp[64], *tmpp; @@ -673,7 +673,7 @@ t0 = off; if (max == 1) { - t0 += in[0] * quant[0]; + t0 += in[0] * lquant[0]; for (i = 0; i < 64; i++) out[i] = ITOINT(t0); return; @@ -682,21 +682,21 @@ tmpp = tmp; for (i = 0; i < 8; i++) { j = *zig2p++; - t0 += in[j] * quant[j]; + t0 += in[j] * lquant[j]; j = *zig2p++; - t5 = in[j] * quant[j]; + t5 = in[j] * lquant[j]; j = *zig2p++; - t2 = in[j] * quant[j]; + t2 = in[j] * lquant[j]; j = *zig2p++; - t7 = in[j] * quant[j]; + t7 = in[j] * lquant[j]; j = *zig2p++; - t1 = in[j] * quant[j]; + t1 = in[j] * lquant[j]; j = *zig2p++; - t4 = in[j] * quant[j]; + t4 = in[j] * lquant[j]; j = *zig2p++; - t3 = in[j] * quant[j]; + t3 = in[j] * lquant[j]; j = *zig2p++; - t6 = in[j] * quant[j]; + t6 = in[j] * lquant[j]; IDCT; tmpp[0 * 8] = t0; tmpp[1 * 8] = t1;

1 0

[commit] r5246 - in trunk/src: arch/i386/boot pc80
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:44:45 2010 New Revision: 5246 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5246 Log: fix minor warnings in RTC code when HAVE_OPTION_TABLE is disabled. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/boot/coreboot_table.c trunk/src/pc80/mc146818rtc.c Modified: trunk/src/arch/i386/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/i386/boot/coreboot_table.c Wed Mar 17 04:40:23 2010 (r5245) +++ trunk/src/arch/i386/boot/coreboot_table.c Wed Mar 17 04:44:45 2010 (r5246) @@ -185,6 +185,7 @@ return mainboard; } +#if (CONFIG_HAVE_OPTION_TABLE == 1) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { struct lb_record *rec; @@ -202,6 +203,7 @@ return cmos_checksum; } +#endif static void lb_strings(struct lb_header *header) { Modified: trunk/src/pc80/mc146818rtc.c ============================================================================== --- trunk/src/pc80/mc146818rtc.c Wed Mar 17 04:40:23 2010 (r5245) +++ trunk/src/pc80/mc146818rtc.c Wed Mar 17 04:44:45 2010 (r5246) @@ -95,6 +95,7 @@ outb(val, RTC_BASE_PORT + offs + 1); } +#if CONFIG_HAVE_OPTION_TABLE static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) { int i; @@ -120,6 +121,7 @@ cmos_write(((sum >> 8) & 0x0ff), cks_loc); cmos_write(((sum >> 0) & 0x0ff), cks_loc+1); } +#endif #if CONFIG_ARCH_X86 #define RTC_CONTROL_DEFAULT (RTC_24H)

1 0

build service results for r5238
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5238 to the coreboot repository. This caused the following changes: Change Log: >From Keith Hui: This patch implements a full SDRAM buffer strength programming algorithm in set_dram_buffer_strength(), checked against my P2B-LS factory BIOS. With this in place, I now have 133MHz (!) stability with three 256MB PC133 modules, and can boot Fedora 11 all the way to the init daemon (actually upstart, but that's another story). Not to login prompt yet. We'll find out why later. This again assumes a 4-DIMM board because that's all I have. I need someone with a 3-DIMM board to test it. As a bonus, there's a big comment block within that illustrates the algorithm. :-) Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5238&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5238&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5238&device=x6dhr_ig2&vend… Compilation of tyan:s2735 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5238&device=s2735&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5244 - trunk/src/southbridge/intel/i82801dx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:37:18 2010 New Revision: 5244 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5244 Log: This patch fixes up the i82801dx_lpc.c code post transition. Boot Tested (bootlog attached) Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Wed Mar 17 04:18:29 2010 (r5243) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Wed Mar 17 04:37:18 2010 (r5244) @@ -36,6 +36,9 @@ extern void i82801dx_enable(device_t dev); #endif +#define IO_APIC_ADDR 0xfec00000 +#define HPET_ADDR 0xfed00000 + #define DEBUG_PERIODIC_SMIS 0 #define MAINBOARD_POWER_OFF 0 @@ -79,8 +82,15 @@ #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C -#define PIRQA_ROUT 0x60 -#define PIRQE_ROUT 0x68 +#define GPIOBASE_ADDR 0x0500 +#define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 +#define PIRQE_ROUT 0x68 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2 @@ -192,4 +202,9 @@ #define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + #endif /* I82801DX_H */ Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:18:29 2010 (r5243) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:37:18 2010 (r5244) @@ -4,6 +4,7 @@ * Copyright (C) 2003 Linux Networx * Copyright (C) 2004 SuSE Linux AG * Copyright (C) 2004 Tyan Computer + * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -32,166 +33,201 @@ #define NMI_OFF 0 -void i82801dx_enable_ioapic(struct device *dev) +typedef struct southbridge_intel_i82801dx_config config_t; + +static void i82801dx_enable_ioapic(struct device *dev) { - u32 dword; - volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010; - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic */ - dword |= (1 << 13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk_debug("ioapic southbridge enabled %x\n", dword); - *ioapic_sba = 0; - *ioapic_sbd = (2 << 24); - //lyh *ioapic_sba=3; - //lyh *ioapic_sbd=1; - *ioapic_sba = 0; - dword = *ioapic_sbd; - printk_debug("Southbridge apic id = %x\n", dword); - if (dword != (2 << 24)) - die(""); - //lyh *ioapic_sba=3; - //lyh dword=*ioapic_sbd; - //lyh printk_debug("Southbridge apic DT = %x\n",dword); - //lyh if(dword!=1) - //lyh die(""); + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; + volatile u32 *ioapic_data = (volatile u32 *)IO_APIC_ADDR + 0x10; + + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Enable ACPI I/O and power management. */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* Enable IOAPIC */ + reg32 |= (1 << 13); /* Coprocessor error enable */ + reg32 |= (1 << 1); /* Delayed transaction enable */ + reg32 |= (1 << 2); /* DMA collection buffer enable */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk_debug("Southbridge APIC ID = %x\n", reg32); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + /* TODO: From i82801ca, needed/useful on other ICH? */ + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } -void i82801dx_enable_serial_irqs(struct device *dev) +static void i82801dx_enable_serial_irqs(struct device *dev) { + /* Set packet length and toggle silent mode bit. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, + (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); } -void i82801dx_lpc_route_dma(struct device *dev, u8 mask) +static void i82801dx_pirq_init(device_t dev) { - u16 word; - int i; - word = pci_read_config16(dev, PCI_DMA_CFG); - word &= ((1 << 10) - (1 << 8)); - for (i = 0; i < 8; i++) { - if (i == 4) - continue; - word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); - } - pci_write_config16(dev, PCI_DMA_CFG, word); + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + } -void i82801dx_rtc_init(struct device *dev) +static void i82801dx_power_options(device_t dev) { u8 byte; - u32 dword; - int rtc_failed; - byte = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = byte & RTC_FAILED; - if (rtc_failed) { - byte &= ~(1 << 1); /* preserve the power fail state */ - pci_write_config8(dev, GEN_PMCON_3, byte); + int pwr_on = -1; + int nmi_option; + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); + printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* Set NMI. */ + outb(byte, 0x70); } - dword = pci_read_config32(dev, GEN_STS); - rtc_failed |= dword & (1 << 2); - rtc_init(rtc_failed); } -void i82801dx_1f0_misc(struct device *dev) +static void gpio_init(device_t dev) { - pci_write_config16(dev, PCICMD, 0x014f); - pci_write_config32(dev, PMBASE, 0x00001001); - pci_write_config8(dev, ACPI_CNTL, 0x10); - pci_write_config32(dev, GPIO_BASE, 0x00001181); + /* This should be done in romstage.c already */ + pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); pci_write_config8(dev, GPIO_CNTL, 0x10); - pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - pci_write_config8(dev, PIRQE_ROUT, 0x07); +} + +static void i82801dx_rtc_init(struct device *dev) +{ + u8 reg8; + u32 reg32; + int rtc_failed; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~(1 << 1); /* Preserve the power fail state. */ + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + reg32 = pci_read_config32(dev, GEN_STS); + rtc_failed |= reg32 & (1 << 2); + rtc_init(rtc_failed); + + /* Enable access to the upper 128 byte bank of CMOS RAM. */ pci_write_config8(dev, RTC_CONF, 0x04); - pci_write_config8(dev, COM_DEC, 0x10); //lyh E0-> - pci_write_config16(dev, LPC_EN, 0x000F); //LYH 000D-> } -static void enable_hpet(struct device *dev) +static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) { - const unsigned long hpet_address = 0xfed00000; + u16 reg16; + int i; - u32 dword; - u32 code = (0 & 0x3); + reg16 = pci_read_config16(dev, PCI_DMA_CFG); + reg16 &= 0x300; + for (i = 0; i < 8; i++) { + if (i == 4) + continue; + reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, reg16); +} - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (1 << 17); /* enable hpet */ - /*Bits [16:15]Memory Address Range - 00 FED0_0000h - FED0_03FFh - 01 FED0_1000h - FED0_13FFh - 10 FED0_2000h - FED0_23FFh - 11 FED0_3000h - FED0_33FFh */ +static void i82801dx_lpc_decode_en(device_t dev) +{ + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); +} - dword &= ~(3 << 15); /* clear it */ - dword |= (code << 15); +static void enable_hpet(struct device *dev) +{ + u32 reg32; + u32 code = (0 & 0x3); - printk_debug("enabling HPET @0x%lx\n", hpet_address | (code << 12)); + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET. */ + /* + * Bits [16:15] Memory Address Range + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh + */ + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + /* TODO: reg32 is never written to anywhere? */ + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); } static void lpc_init(struct device *dev) { - u8 byte; - int pwr_on = -1; - int nmi_option; + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization */ + /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); i82801dx_enable_serial_irqs(dev); -#ifdef SUSPICIOUS_LOOKING_CODE - // The ICH-4 datasheet does not mention this configuration register. - // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge, - // which *does* support this functionality. - - /* posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif + /* Setup the PIRQ. */ + i82801dx_pirq_init(dev); - /* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("set power %s after power fail\n", pwr_on ? "on" : "off"); -#if 0 - /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); -#endif + /* Setup power options. */ + i82801dx_power_options(dev); - /* Set up NMI on errors */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - outb(byte, 0x70); - } + /* Set the state of the GPIO lines. */ + gpio_init(dev); - /* Initialize the real time clock */ + /* Initialize the real time clock. */ i82801dx_rtc_init(dev); + /* Route DMA. */ i82801dx_lpc_route_dma(dev, 0xff); - /* Initialize isa dma */ + /* Initialize ISA DMA. */ isa_dma_init(); - i82801dx_1f0_misc(dev); + /* Setup decode ports and LPC I/F enables. */ + i82801dx_lpc_decode_en(dev); + /* Initialize the High Precision Event Timers */ enable_hpet(dev); } @@ -208,15 +244,15 @@ res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ + res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ + res = new_resource(dev, 3); /* IOAPIC */ res->base = 0xfec00000; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; @@ -229,12 +265,12 @@ } static struct device_operations lpc_ops = { - .read_resources = i82801dx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i82801dx_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801dx_enable, + .read_resources = i82801dx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801dx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801dx_enable, }; /* 82801DB/DBL */

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coreboot March 2010