coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

build service results for r5262
by coreboot information 19 Mar '10

19 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "eswierk" checked in revision 5262 to the coreboot repository. This caused the following changes: Change Log: I ran into a couple of errors while building a mahogany_fam10 target; CONFIG_CAR_FAM10 was renamed some time ago to CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as l3_cache(). Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5262&device=atc-6220&vendo… If something broke during this checkin please be a pain in eswierk's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Fix compile errors in rs780/fam10
by Ed Swierk 19 Mar '10

19 Mar '10

I ran into a couple of errors while building a mahogany_fam10 target; CONFIG_CAR_FAM10 was renamed some time ago to CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as l3_cache(). Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: src/southbridge/amd/rs780/rs780_early_setup.c =================================================================== --- src/southbridge/amd/rs780/rs780_early_setup.c (revision 5260) +++ src/southbridge/amd/rs780/rs780_early_setup.c (working copy) @@ -101,7 +101,7 @@ } } /* family 10 only, for reg > 0xFF */ -#if CONFIG_CAR_FAM10 == 1 +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -270,7 +270,7 @@ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk_info("rs780_htinit: HT3 mode\n"); - #if CONFIG_CAR_FAM10 == 1 /* save some spaces */ + #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -306,11 +306,11 @@ /* Sets Training 0 Time. See T0Time table for encodings */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); /* TODO: */ - #endif /* #if CONFIG_CAR_FAM10 == 1 */ + #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ } } -#if CONFIG_CAR_FAM10 != 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */ /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -364,9 +364,9 @@ } #else #define k8_optimization() do{}while(0) -#endif /* #if CONFIG_CAR_FAM10 != 1 */ +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ -#if CONFIG_CAR_FAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ void fam10_optimization() { device_t cpu_f0, cpu_f2, cpu_f3; @@ -422,7 +422,7 @@ /* L3 Disabled: L3 Enabled: */ /* cores: 2 3 4 2 3 4 */ /* bit8:4 28 26 24 24 20 16 */ - if (!l3Cache()) { + if (!l3_cache()) { Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2); } else { Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4); @@ -430,7 +430,7 @@ } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_CAR_FAM10 == 1 */ +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ /***************************************** * rs780_por_pcicfg_init()

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[commit] r5262 - trunk/src/southbridge/amd/rs780
by repository service 19 Mar '10

19 Mar '10

Author: eswierk Date: Fri Mar 19 22:57:40 2010 New Revision: 5262 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5262 Log: I ran into a couple of errors while building a mahogany_fam10 target; CONFIG_CAR_FAM10 was renamed some time ago to CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as l3_cache(). Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_early_setup.c Fri Mar 19 09:23:50 2010 (r5261) +++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c Fri Mar 19 22:57:40 2010 (r5262) @@ -101,7 +101,7 @@ } } /* family 10 only, for reg > 0xFF */ -#if CONFIG_CAR_FAM10 == 1 +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { @@ -270,7 +270,7 @@ } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk_info("rs780_htinit: HT3 mode\n"); - #if CONFIG_CAR_FAM10 == 1 /* save some spaces */ + #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -306,11 +306,11 @@ /* Sets Training 0 Time. See T0Time table for encodings */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); /* TODO: */ - #endif /* #if CONFIG_CAR_FAM10 == 1 */ + #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ } } -#if CONFIG_CAR_FAM10 != 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */ /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -364,9 +364,9 @@ } #else #define k8_optimization() do{}while(0) -#endif /* #if CONFIG_CAR_FAM10 != 1 */ +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ -#if CONFIG_CAR_FAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ void fam10_optimization() { device_t cpu_f0, cpu_f2, cpu_f3; @@ -422,7 +422,7 @@ /* L3 Disabled: L3 Enabled: */ /* cores: 2 3 4 2 3 4 */ /* bit8:4 28 26 24 24 20 16 */ - if (!l3Cache()) { + if (!l3_cache()) { Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2); } else { Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4); @@ -430,7 +430,7 @@ } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_CAR_FAM10 == 1 */ +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ /***************************************** * rs780_por_pcicfg_init()

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[PATCH] let fam10 machines calculate correct link offsets
by Maximilian Thuermer 19 Mar '10

19 Mar '10

Hi all, I am working with a Tyan S2912 board and fam10 Opterons and recently updated my coreboot environment. I stumbled across an error which I thought was already removed a while ago. The HT link offsets reported by function "AMD_CpuFindCapability" in init_cpus.c are not correct (they always evaluate to 0x08) and therefore do not comply with link offsets as specified by AMDs BKDG. Below is a simple fix which produces correct behavior - at least on my box. Dont know what side effects this might have on systems other than the PHY electrical settings and erratas not getting applied. Best regards, Maximilian Thuermer Index: src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- src/cpu/amd/model_10xxx/init_cpus.c (revision 5256) +++ src/cpu/amd/model_10xxx/init_cpus.c (working copy) @@ -702,29 +702,32 @@ */ BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) { + u32 reg; u32 val; - + /* get start of CPU HT Host Capabilities */ val = pci_read_config32(NODE_PCI(node, 0), 0x34); - val &= 0xFF; + val &= 0xFF; //reg offset of first link cap_count++; /* Traverse through the capabilities. */ do { - val = pci_read_config32(NODE_PCI(node, 0), val); + reg = pci_read_config32(NODE_PCI(node, 0), val); /* Is the capability block a HyperTransport capability block? */ - if ((val & 0xFF) == 0x08) { + if ((reg & 0xFF) == 0x08) { /* Is the HT capability block an HT Host Capability? */ - if ((val & 0xE0000000) == (1 << 29)) + if ((reg & 0xE0000000) == (1 << 29)) cap_count--; } - if (cap_count) - val = (val >> 8) & 0xFF; + + if(cap_count) + val = (reg >> 8) & 0xFF; //update reg offset } while (cap_count && val); *offset = (u8) val; + /* If requested capability found val != 0 */ if (!cap_count) return TRUE;

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brief presentation of GSOC 2010
by Jason Wang 19 Mar '10

19 Mar '10

Hi all Since i will have a brief talking about GSOC 2010 in a Open Source Community(http://www.linuxfb.org/) this Sunday. I prepared a small presentation. Any advices will be welcome. Thanks all -- Wang Qing Pei MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> Phone:86+13426369984

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[PATCH]: Fix memset calling error
by Bao, Zheng 19 Mar '10

19 Mar '10

The parameters of memset() should be memset(addr, value, size), right? It is an obvious bug created at r5201. I am wondering why it doesnt trouble you. I took a quike look at other files and didnt find other calling error. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- src/cpu/amd/model_fxx/model_fxx_init.c (revision 5260) +++ src/cpu/amd/model_fxx/model_fxx_init.c (working copy) @@ -238,7 +238,7 @@ /* clear memory 2M (limitk - basek) */ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10)); - memset(addr, size, 0); + memset(addr, 0, size); } static void init_ecc_memory(unsigned node_id) Index: src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- src/cpu/amd/car/post_cache_as_ram.c (revision 5260) +++ src/cpu/amd/car/post_cache_as_ram.c (working copy) @@ -95,9 +95,9 @@ print_debug("Clearing initial memory region: "); #if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0); + memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0); + memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); #endif print_debug("Done\r\n");

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[commit] r5261 - in trunk/src/cpu/amd: car model_fxx
by repository service 19 Mar '10

19 Mar '10

Author: zbao Date: Fri Mar 19 09:23:50 2010 New Revision: 5261 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5261 Log: The parameters of memset() should be memset(addr, value, size), right? It is an obvious bug created at r5201. I am wondering why it doesnt trouble you. I took a quick look at other files and didnt find other calling error. Trailing white spaces are also deleted. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/model_fxx/model_fxx_init.c Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Mar 19 03:33:40 2010 (r5260) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Mar 19 09:23:50 2010 (r5261) @@ -1,4 +1,4 @@ -/* 2005.6 by yhlu +/* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ #include "cpu/amd/car/disable_cache_as_ram.c" @@ -55,13 +55,13 @@ unsigned testx = 0x5a5a5a5a; print_debug_pcar("testx = ", testx); - /* copy data from cache as ram to + /* copy data from cache as ram to ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead. */ #if CONFIG_RAMTOP <= 0x100000 #error "You need to set CONFIG_RAMTOP greater than 1M" #endif - + /* So we can access RAM from [1M, CONFIG_RAMTOP) */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); @@ -90,14 +90,14 @@ print_debug_pcar("testx = ", testx); print_debug("Disabling cache as ram now \r\n"); - disable_cache_as_ram_bsp(); + disable_cache_as_ram_bsp(); print_debug("Clearing initial memory region: "); #if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ - memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0); + memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); #else - memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0); + memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE)); #endif print_debug("Done\r\n"); Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Fri Mar 19 03:33:40 2010 (r5260) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Fri Mar 19 09:23:50 2010 (r5261) @@ -5,7 +5,7 @@ * 2005.02 yhlu add e0 memory hole support * Copyright 2005 AMD - * 2005.08 yhlu add microcode support + * 2005.08 yhlu add microcode support */ #include <console/console.h> #include <cpu/x86/msr.h> @@ -199,7 +199,7 @@ enable_cache(); } -static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) +static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) { unsigned long limitk; unsigned long size; @@ -226,7 +226,7 @@ #if 0 /* couldn't happen, memory must on 2M boundary */ if(limitk>endk) { - limitk = enk; + limitk = enk; } #endif size = (limitk - basek) << 10; @@ -238,7 +238,7 @@ /* clear memory 2M (limitk - basek) */ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10)); - memset(addr, size, 0); + memset(addr, 0, size); } static void init_ecc_memory(unsigned node_id) @@ -278,7 +278,7 @@ (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0)); printk_debug("Scrubbing Disabled\n"); } - + /* If ecc support is not enabled don't touch memory */ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW); @@ -292,7 +292,7 @@ #if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) + if (!is_cpu_pre_e0()) { #endif @@ -305,7 +305,7 @@ } #endif #endif - + /* Don't start too early */ begink = startk; @@ -337,10 +337,10 @@ clear_2M_ram(basek, &mtrr_state); } } - else + else #endif for(basek = begink; basek < endk; - basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) + basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) { clear_2M_ram(basek, &mtrr_state); } @@ -385,7 +385,7 @@ msr = rdmsr_amd(DC_CFG_MSR); msr.lo |= (1 << 10); wrmsr_amd(DC_CFG_MSR, msr); - + } /* I can't touch this msr on early buggy cpus */ if (!is_cpu_pre_b3()) { @@ -393,10 +393,10 @@ /* Erratum 89 ... */ msr = rdmsr(NB_CFG_MSR); msr.lo |= 1 << 3; - + if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { /* D0 later don't need it */ - /* Erratum 86 Disable data masking on C0 and + /* Erratum 86 Disable data masking on C0 and * later processor revs. * FIXME this is only needed if ECC is enabled. */ @@ -404,14 +404,14 @@ } wrmsr(NB_CFG_MSR, msr); } - + /* Erratum 97 ... */ if (!is_cpu_pre_c0() && is_cpu_pre_d0()) { msr = rdmsr_amd(DC_CFG_MSR); msr.lo |= 1 << 3; wrmsr_amd(DC_CFG_MSR, msr); - } - + } + /* Erratum 94 ... */ if (is_cpu_pre_d0()) { msr = rdmsr_amd(IC_CFG_MSR); @@ -440,7 +440,7 @@ #endif #if CONFIG_K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) + if (!is_cpu_pre_e0()) #endif { /* Erratum 110 ... */ @@ -478,12 +478,12 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 struct cpuinfo_x86 c; - + get_fms(&c, dev->device); #endif #if CONFIG_USBDEBUG_DIRECT - if(!ehci_debug_addr) + if(!ehci_debug_addr) ehci_debug_addr = get_ehci_debug(); set_ehci_debug(0); #endif @@ -501,7 +501,7 @@ model_fxx_update_microcode(dev->device); disable_cache(); - + /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; @@ -510,15 +510,15 @@ } k8_errata(); - + /* Set SMMLOCK to avoid exploits messing with SMM */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - + /* Set the processor name string */ init_processor_name(); - + enable_cache(); /* Enable the local cpu apics */ @@ -529,17 +529,17 @@ if(siblings>0) { msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; + msr.lo |= 1 << 28; wrmsr_amd(CPU_ID_FEATURES_MSR, msr); msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR); - msr.lo = (siblings+1)<<16; + msr.lo = (siblings+1)<<16; wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr); msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1<<(33-32); + msr.hi |= 1<<(33-32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } + } #endif

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build service results for r5261
by coreboot information 19 Mar '10

19 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 5261 to the coreboot repository. This caused the following changes: Change Log: The parameters of memset() should be memset(addr, value, size), right? It is an obvious bug created at r5201. I am wondering why it doesnt trouble you. I took a quick look at other files and didnt find other calling error. Trailing white spaces are also deleted. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5261&device=atc-6220&vendo… If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5260
by coreboot information 19 Mar '10

19 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5260 to the coreboot repository. This caused the following changes: Change Log: Get rid of a few warnings: 1. Add some more prototypes to lib.h 2. Include console.h when not using romcc 3. Eliminate an unused function 4. Set a default for SSE2, since it is just for ramtest performance Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5260&device=atc-6220&vendo… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 1

[commit] r5260 - in trunk/src: arch/i386/lib cpu include lib mainboard/tyan/s2892 pc80
by repository service 19 Mar '10

19 Mar '10

Author: myles Date: Fri Mar 19 03:33:40 2010 New Revision: 5260 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5260 Log: Get rid of a few warnings: 1. Add some more prototypes to lib.h 2. Include console.h when not using romcc 3. Eliminate an unused function 4. Set a default for SSE2, since it is just for ramtest performance Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/arch/i386/lib/console.c trunk/src/cpu/Kconfig trunk/src/include/lib.h trunk/src/lib/generic_sdram.c trunk/src/lib/ramtest.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/pc80/serial.c Modified: trunk/src/arch/i386/lib/console.c ============================================================================== --- trunk/src/arch/i386/lib/console.c Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/arch/i386/lib/console.c Fri Mar 19 03:33:40 2010 (r5260) @@ -4,6 +4,7 @@ #if CONFIG_USE_PRINTK_IN_CAR == 0 #include "console_print.c" #else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ +#include <console/console.h> #include "console_printk.c" #endif /* CONFIG_USE_PRINTK_IN_CAR */ Modified: trunk/src/cpu/Kconfig ============================================================================== --- trunk/src/cpu/Kconfig Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/cpu/Kconfig Fri Mar 19 03:33:40 2010 (r5260) @@ -48,6 +48,7 @@ config SSE2 bool + default n help Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built Modified: trunk/src/include/lib.h ============================================================================== --- trunk/src/include/lib.h Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/include/lib.h Fri Mar 19 03:33:40 2010 (r5260) @@ -19,8 +19,15 @@ /* This file is for "nuisance prototypes" that have no other home. */ +#ifndef __LIB_H__ +#define __LIB_H__ + +#ifndef __ROMCC__ /* romcc doesn't support prototypes. */ + +#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */ /* Defined in src/lib/clog2.c */ unsigned long log2(unsigned long x); +#endif /* Defined in src/lib/lzma.c */ unsigned long ulzma(unsigned char *src, unsigned char *dst); @@ -28,3 +35,18 @@ /* Defined in src/arch/i386/boot/gdt.c */ void move_gdt(void); +/* Defined in src/lib/ramtest.c */ +void ram_check(unsigned long start, unsigned long stop); + +/* Defined in src/pc80/serial.c */ +void uart_init(void); + +/* Defined in romstage.c */ +#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX +void cache_as_ram_main(void); +#else +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +#endif + +#endif /* __ROMCC__ */ +#endif /* __LIB_H__ */ Modified: trunk/src/lib/generic_sdram.c ============================================================================== --- trunk/src/lib/generic_sdram.c Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/lib/generic_sdram.c Fri Mar 19 03:33:40 2010 (r5260) @@ -1,3 +1,4 @@ +#include <lib.h> /* Prototypes */ #ifndef RAMINIT_SYSINFO #define RAMINIT_SYSINFO 0 @@ -12,14 +13,6 @@ #endif } -void sdram_no_memory(void) -{ - print_err("No memory!!\r\n"); - while(1) { - hlt(); - } -} - /* Setup SDRAM */ #if RAMINIT_SYSINFO == 1 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) Modified: trunk/src/lib/ramtest.c ============================================================================== --- trunk/src/lib/ramtest.c Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/lib/ramtest.c Fri Mar 19 03:33:40 2010 (r5260) @@ -1,3 +1,5 @@ +#include <lib.h> /* Prototypes */ + static void write_phys(unsigned long addr, unsigned long value) { // Assembler in lib/ is very ugly. But we properly guarded Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/mainboard/tyan/s2892/romstage.c Fri Mar 19 03:33:40 2010 (r5260) @@ -17,7 +17,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#define post_code(x) outb(x, 0x80) #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" Modified: trunk/src/pc80/serial.c ============================================================================== --- trunk/src/pc80/serial.c Thu Mar 18 21:58:41 2010 (r5259) +++ trunk/src/pc80/serial.c Fri Mar 19 03:33:40 2010 (r5260) @@ -1,3 +1,5 @@ +#include <lib.h> /* Prototypes */ + /* Base Address */ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3f8

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2007

2006

2005

2004

2003

2002

coreboot March 2010