coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

FW: VGA rom can not be loaded by SEABIOS
by Wang, Qingpei 18 Mar '10

18 Mar '10

Hi Kevin, I have already found the reason. It is only because "791F != 791f". I just use 791F in cbfs. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD) ________________________________ From: Jason Wang [mailto:wangqingpei@gmail.com] Sent: Thursday, March 18, 2010 12:05 PM To: Wang, Qingpei Subject: Fwd: [coreboot] VGA rom can not be loaded by SEABIOS ---------- Forwarded message ---------- From: Kevin O'Connor <kevin(a)koconnor.net> Date: Wed, Mar 17, 2010 at 11:33 PM Subject: Re: [coreboot] VGA rom can not be loaded by SEABIOS To: Jason Wang <wangqingpei(a)gmail.com> On Wed, Mar 17, 2010 at 11:29:33PM +0800, Jason Wang wrote: > the log which i attached is because of the CONFIG_COREBOOT_FLASH. but after > i set that, i will post the new log tomorrow. > By the way, after CONFIG_COREBOOT_FLASH is set. seabios will load the vgarom > by the file name prefix with "vgaroms/" right? It will load both "pciVVVV,DDDD.rom" and "vgaroms/*" - the pciVVVV,DDDD.rom format is preferred. -Kevin -- Wang Qing Pei MSN:wangqingpei@hotmail.com <mailto:MSN%3Awangqingpei@hotmail.com> Gmail:wangqingpei@gmail.com <mailto:Gmail%3Awangqingpei@gmail.com> Phone:86+13426369984

5 4

iasl failure
by Marc Jones 18 Mar '10

18 Mar '10

The latest IASL from acpica.org fails. http://www.acpica.org/downloads/unix_source_code.php It seems like the name substitution no longer works, but I am uncertain if this is an IASL or coreboot issue. Thoughts? IASL build/mainboard/amd/mahogany/dsdt.o Intel ACPI Component Architecture ASL Optimizing Compiler version 20100304 [Mar 18 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0 /home/marc/svn/coreboot/build/mainboard/amd/mahogany/dsdt.asl 1296: Name (_ADR, Zero) Error 4080 - Invalid object type for reserved name, must be ^ (Integer) ASL Input: /home/marc/svn/coreboot/build/mainboard/amd/mahogany/dsdt.asl - 1827 lines, 35334 bytes, 1008 keywords Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 362 Optimizations make: *** [/home/marc/svn/coreboot/build/mainboard/amd/mahogany/dsdt.o] Error 255 Marc -- http://se-eng.com

3 4

Re: [coreboot] Patch (GSOC 2010)
by Arun Pandian 18 Mar '10

18 Mar '10

Hi, I am a graduate student planning to submit a proposal for GSOC 2010 to work on a project for Coreboot. I found on the project web site that sending a valid patch to the list is required to demonstrate my ability to work with the code base. Can any one suggest a simple task that I could work on? Thanks in advance. Regards, Arun Pandian

2 1

[PATCH]: AMD RS780/SB700 support
by Bao, Zheng 18 Mar '10

18 Mar '10

Please see the comment and Signed-off-by line in each patch file. Zheng

13 14

[commit] r5259 - in trunk/src: . cpu/amd/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/x86/car include lib mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah mainb...
by repository service 18 Mar '10

18 Mar '10

Author: oxygene Date: Thu Mar 18 21:58:41 2010 New Revision: 5259 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5259 Log: Remove remaining uses of HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/Kconfig trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/x86/car/cache_as_ram.inc trunk/src/include/fallback.h trunk/src/lib/fallback_boot.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9282/Kconfig trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -272,22 +272,6 @@ int default 0 -config HAVE_FALLBACK_BOOT - bool - default y - -config USE_FALLBACK_IMAGE - bool - default y - -config HAVE_FAILOVER_BOOT - bool - default n - -config USE_FAILOVER_IMAGE - bool - default n - config HAVE_HARD_RESET bool default y if BOARD_HAS_HARD_RESET Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Mar 18 21:58:41 2010 (r5259) @@ -71,9 +71,6 @@ cvtsi2sd %eax, %xmm2 cvtsd2si %xmm3, %ebx - /* hope we can skip the double set for normal part */ -#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx rdmsr @@ -248,15 +245,6 @@ xorl %edx, %edx movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr -#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/ - -#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) - /* disable cache */ - movl %cr0, %eax - orl $(0x1 << 30), %eax - movl %eax, %cr0 - -#endif #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place @@ -283,7 +271,6 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ -#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Set the default memory type and enable fixed and variable MTRRs */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx @@ -296,7 +283,6 @@ rdmsr orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax wrmsr -#endif movb $0xA1, %al outb %al, $0x80 @@ -318,7 +304,6 @@ movb $0xA2, %al outb %al, $0x80 -#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) /* Read the range with lodsl*/ cld movl $CacheBase, %esi @@ -331,8 +316,6 @@ xorl %eax, %eax rep stosl -#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/ - /* set up the stack pointer */ movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl %eax, %esp Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Thu Mar 18 21:58:41 2010 (r5259) @@ -29,8 +29,6 @@ movl %eax, %ebp cache_as_ram: -#if CONFIG_USE_FALLBACK_IMAGE == 1 - post_code(0x20) /* Send INIT IPI to all excluding ourself */ @@ -134,7 +132,6 @@ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax movl %eax, %cr0 -#endif /* Set up stack pointer */ #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Mar 18 21:58:41 2010 (r5259) @@ -29,8 +29,6 @@ movl %eax, %ebp cache_as_ram: -#if CONFIG_USE_FALLBACK_IMAGE == 1 - post_code(0x20) /* Send INIT IPI to all excluding ourself */ @@ -123,7 +121,6 @@ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax movl %eax, %cr0 -#endif /* Set up stack pointer */ #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Mar 18 21:58:41 2010 (r5259) @@ -29,8 +29,6 @@ movl %eax, %ebp cache_as_ram: -#if CONFIG_USE_FALLBACK_IMAGE == 1 - post_code(0x20) /* Send INIT IPI to all excluding ourself */ @@ -130,7 +128,6 @@ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax movl %eax, %cr0 -#endif /* Set up stack pointer */ #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) Modified: trunk/src/cpu/x86/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.inc Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/cpu/x86/car/cache_as_ram.inc Thu Mar 18 21:58:41 2010 (r5259) @@ -36,9 +36,6 @@ movl %eax, %ebp CacheAsRam: - /* hope we can skip the double set for normal part */ -#if CONFIG_USE_FALLBACK_IMAGE == 1 - // Check whether the processor has HT capability movl $01, %eax cpuid @@ -191,14 +188,6 @@ simplemask CacheSize, 0 wrmsr -#else - /* disable cache */ - movl %cr0, %eax - orl $(0x1 << 30), %eax - movl %eax, %cr0 - -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ - #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE @@ -225,8 +214,6 @@ andl $0x9fffffff, %eax movl %eax, %cr0 -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Read the range with lodsl*/ movl $CacheBase, %esi cld @@ -283,8 +270,6 @@ .xout1x: #endif -#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ - movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp @@ -319,7 +304,6 @@ .long 0x20C, 0x20D, 0x20E, 0x20F .long 0x000 /* NULL, end of table */ -#if CONFIG_USE_FALLBACK_IMAGE == 1 .align 0x1000 .code16 .global LogicalAP_SIPI @@ -349,5 +333,4 @@ hlt jmp Halt_LogicalAP .code32 -#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ .CacheAsRam_out: Modified: trunk/src/include/fallback.h ============================================================================== --- trunk/src/include/fallback.h Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/include/fallback.h Thu Mar 18 21:58:41 2010 (r5259) @@ -3,12 +3,7 @@ #ifndef ASSEMBLY -#if CONFIG_HAVE_FALLBACK_BOOT == 1 void set_boot_successful(void); -#else -#define set_boot_successful() -#endif - void boot_successful(void); #endif /* ASSEMBLY */ Modified: trunk/src/lib/fallback_boot.c ============================================================================== --- trunk/src/lib/fallback_boot.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/lib/fallback_boot.c Thu Mar 18 21:58:41 2010 (r5259) @@ -5,7 +5,6 @@ #include <arch/io.h> -#if CONFIG_HAVE_FALLBACK_BOOT == 1 void set_boot_successful(void) { /* Remember I succesfully booted by setting @@ -26,7 +25,6 @@ byte &= 0x0f; outb(byte, RTC_PORT(1)); } -#endif void boot_successful(void) { Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -58,14 +58,12 @@ outb(value, 0x80); } -#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -80,8 +78,6 @@ #include "cpu/x86/bist.h" -#if (CONFIG_USE_FAILOVER_IMAGE == 0) - static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" @@ -128,13 +124,10 @@ #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ - #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -#if (CONFIG_USE_FAILOVER_IMAGE==0) //#include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -306,5 +299,3 @@ post_code(0x43); // Should never see this post code. } - -#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -43,21 +43,18 @@ #endif } #endif -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -152,13 +149,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -336,4 +330,3 @@ post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } -#endif Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -58,7 +58,6 @@ outb(value, 0x80); } -#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" @@ -66,7 +65,6 @@ #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -80,8 +78,6 @@ #include "cpu/x86/bist.h" -#if (CONFIG_USE_FAILOVER_IMAGE == 0) - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -141,13 +137,10 @@ #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" -#if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -316,5 +309,3 @@ } - -#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -47,8 +47,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - /* Used by ck894_early_setup(). */ #define CK804_NUM 1 @@ -96,8 +94,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* CONFIG_USE_FAILOVER_IMAGE */ - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -118,7 +114,6 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -#if CONFIG_USE_FAILOVER_IMAGE == 0 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -200,4 +195,3 @@ post_cache_as_ram(); } -#endif /* CONFIG_USE_FAILOVER_IMAGE */ Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -75,16 +75,6 @@ default n depends on BOARD_GIGABYTE_GA_2761GXDK -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_GIGABYTE_GA_2761GXDK - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_GIGABYTE_GA_2761GXDK - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -56,7 +56,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -73,15 +72,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -150,8 +145,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "northbridge/amd/amdk8/early_ht.c" @@ -175,8 +168,6 @@ pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); } -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -303,5 +294,3 @@ } - -#endif Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -78,16 +78,6 @@ default n depends on BOARD_GIGABYTE_M57SLI -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_GIGABYTE_M57SLI - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_GIGABYTE_M57SLI - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -70,15 +69,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8716f/it8716f_early_serial.c" #include "superio/ite/it8716f/it8716f_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -148,8 +143,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -175,8 +168,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -316,5 +307,3 @@ } - -#endif Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -61,7 +61,6 @@ #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -73,8 +72,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -83,8 +80,6 @@ #include "superio/nsc/pc87417/pc87417_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -153,8 +148,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "northbridge/amd/amdk8/early_ht.c" #if 0 @@ -195,8 +188,6 @@ } #endif -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -312,4 +303,3 @@ } -#endif Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -216,9 +216,7 @@ RCBA32(0x2034) = reg32; } -#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801gx/cmos_failover.c" -#endif #include <cbmem.h> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -121,9 +121,7 @@ #include "northbridge/intel/i3100/reset_test.c" #include "debug.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i3100/cmos_failover.c" -#endif void early_config(void) { device_t dev; Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -32,21 +32,17 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -128,13 +124,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -260,4 +253,3 @@ post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } -#endif Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -32,21 +32,17 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -128,13 +124,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -260,4 +253,3 @@ post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } -#endif Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -32,21 +32,16 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#endif - - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "cpu/x86/bist.h" #include "lib/delay.c" @@ -128,13 +123,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -260,4 +252,3 @@ post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } -#endif Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -352,9 +352,7 @@ RCBA32(0x2034) = reg32; } -#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801gx/cmos_failover.c" -#endif #include <cbmem.h> Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms7135/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -47,8 +47,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - /* Used by ck804_early_setup(). */ #define CK804_NUM 1 #define CK804_USE_NIC 1 @@ -98,8 +96,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#endif /* CONFIG_USE_FAILOVER_IMAGE */ - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -121,7 +117,6 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -#if CONFIG_USE_FAILOVER_IMAGE == 0 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -204,4 +199,3 @@ post_cache_as_ram(); } -#endif /* CONFIG_USE_FAILOVER_IMAGE */ Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms7260/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -76,16 +76,6 @@ default n depends on BOARD_MSI_MS7260 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_MSI_MS7260 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_MSI_MS7260 - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -58,8 +58,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -73,15 +71,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE == 0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -129,8 +123,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -152,8 +144,6 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); } -#if CONFIG_USE_FAILOVER_IMAGE == 0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { @@ -282,4 +272,3 @@ post_cache_as_ram(); } -#endif Modified: trunk/src/mainboard/msi/ms9282/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9282/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms9282/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -70,16 +70,6 @@ default n depends on BOARD_MSI_MS9282 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_MSI_MS9282 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_MSI_MS9282 - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -42,26 +42,6 @@ default 0x1F depends on BOARD_MSI_MS9652_FAM10 -config USE_FALLBACK_IMAGE - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config HAVE_FALLBACK_BOOT - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config CONFIG_USE_FAILOVER_IMAGE - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - -config CONFIG_HAVE_FAILOVER_BOOT - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - config GENERATE_PIRQ_TABLE bool default y Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" @@ -68,14 +67,10 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -143,8 +138,6 @@ #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -163,7 +156,6 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -323,5 +315,3 @@ post_code(0x43); // Should never see this post code. } - -#endif Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -76,16 +76,6 @@ default n depends on BOARD_NVIDIA_L1_2PVV -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_NVIDIA_L1_2PVV - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_NVIDIA_L1_2PVV - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -70,15 +69,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "superio/winbond/w83627ehg/w83627ehg_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -148,8 +143,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -175,7 +168,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -301,5 +293,3 @@ } - -#endif Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -259,9 +259,7 @@ RCBA32(0x2034) = reg32; } -#if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/intel/i82801gx/cmos_failover.c" -#endif static void init_artec_dongle(void) { Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -52,7 +52,6 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -64,15 +63,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -191,8 +186,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -225,8 +218,6 @@ #define RC0 (2<<8) #define RC1 (1<<8) -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we @@ -371,4 +362,3 @@ } -#endif Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -55,7 +55,6 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -67,15 +66,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -137,8 +132,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -167,8 +160,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -291,5 +282,3 @@ } - -#endif Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -65,15 +64,11 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -133,8 +128,6 @@ #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -163,7 +156,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -317,5 +309,3 @@ } - -#endif Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -65,15 +64,11 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -136,8 +131,6 @@ #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -166,7 +159,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -360,5 +352,3 @@ } - -#endif Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/tyan/s2895/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -19,7 +19,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" @@ -32,8 +31,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" @@ -42,8 +39,6 @@ #define SUPERIO_GPIO_IO_BASE 0x400 -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -114,8 +109,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#endif - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -147,8 +140,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -226,4 +217,3 @@ post_cache_as_ram(); } -#endif Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/tyan/s2912/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -76,16 +76,6 @@ default n depends on BOARD_TYAN_S2912 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_TYAN_S2912 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_TYAN_S2912 - config HW_MEM_HOLE_SIZEK hex default 0x100000 Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -54,7 +54,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -70,15 +69,11 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -146,8 +141,6 @@ #include "cpu/amd/model_fxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -174,8 +167,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { @@ -299,5 +290,3 @@ } - -#endif Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Mar 18 21:58:41 2010 (r5259) @@ -38,26 +38,6 @@ default 0x04000 depends on BOARD_TYAN_S2912_FAM10 -config USE_FALLBACK_IMAGE - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config HAVE_FALLBACK_BOOT - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config CONFIG_USE_FAILOVER_IMAGE - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config CONFIG_HAVE_FAILOVER_BOOT - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - config APIC_ID_OFFSET hex default 0 @@ -97,16 +77,6 @@ bool default n depends on BOARD_TYAN_S2912_FAM10 - -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_TYAN_S2912_FAM10 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_TYAN_S2912_FAM10 config HW_MEM_HOLE_SIZEK hex Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Mar 18 21:58:41 2010 (r5259) @@ -53,7 +53,6 @@ outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -68,15 +67,11 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -142,8 +137,6 @@ #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -168,7 +161,6 @@ } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -317,5 +309,3 @@ post_code(0x43); // Should never see this post code. } - -#endif Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Thu Mar 18 17:46:50 2010 (r5258) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Thu Mar 18 21:58:41 2010 (r5259) @@ -3,8 +3,6 @@ * by yinghai.lu(a)amd.com */ -#if CONFIG_USE_FALLBACK_IMAGE == 1 - static void bcm5785_enable_rom(void) { unsigned char byte; @@ -42,8 +40,6 @@ byte |=(1<<1)|(1<<0); pci_write_config8(dev, 0x48, byte); } -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - static void bcm5785_enable_wdt_port_cf9(void) {

1 0

[PATCH]Remove {HAVE, USE}_{FALLBACK, FAILOVER}_* and its uses
by Patrick Georgi 18 Mar '10

18 Mar '10

Hi, attached patch removes the remaining uses of HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE This effort (which is finalized by this patch) should simplify the code flow, so it's easier to figure out what's going on and where. It mightalso fix some boards that had obsolete assumptions about the config flags above. The change is abuild tested, but not boot tested, I hope I didn't break anything. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[commit] r5258 - in trunk/src/mainboard: amd/dbm690t amd/mahogany amd/mahogany_fam10 amd/pistachio amd/serengeti_cheetah amd/serengeti_cheetah_fam10 arima/hdama asus/a8n_e asus/a8v-e_se broadcom/bl...
by repository service 18 Mar '10

18 Mar '10

Author: oxygene Date: Thu Mar 18 17:46:50 2010 New Revision: 5258 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5258 Log: Rework boolean expression (DeMorgan and all) for better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Deleted: trunk/src/mainboard/dell/s1850/failover.c trunk/src/mainboard/emulation/qemu-x86/failover.c trunk/src/mainboard/intel/jarrell/failover.c trunk/src/mainboard/intel/xe7501devkit/failover.c trunk/src/mainboard/olpc/btest/failover.c trunk/src/mainboard/olpc/rev_a/failover.c trunk/src/mainboard/supermicro/x6dai_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g2/failover.c trunk/src/mainboard/supermicro/x6dhr_ig/failover.c trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c trunk/src/mainboard/via/epia-m/failover.c trunk/src/mainboard/via/epia-n/failover.c Modified: trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -111,7 +111,7 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -111,7 +111,7 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -156,7 +156,7 @@ u32 val; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -107,7 +107,7 @@ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -189,7 +189,7 @@ struct cpuid_result cpuid1; #endif - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -160,7 +160,7 @@ u32 val; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -114,7 +114,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -134,7 +134,7 @@ unsigned nodes, bsp_apicid = 0; struct mem_controller ctrl[8]; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -201,7 +201,7 @@ print_info("now booting... fallback\r\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -125,7 +125,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -193,7 +193,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -194,7 +194,7 @@ unsigned bsp_apicid = 0; uint8_t tmp = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -216,7 +216,7 @@ int needs_reset; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -123,7 +123,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -122,7 +122,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -154,7 +154,7 @@ int needs_reset; int i; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -154,7 +154,7 @@ int needs_reset; int i; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -154,7 +154,7 @@ int needs_reset; int i; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -113,7 +113,7 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/msi/ms7135/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -137,7 +137,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -170,7 +170,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -174,7 +174,7 @@ int needs_reset; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -175,7 +175,7 @@ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -178,7 +178,7 @@ u32 wants_reset; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -128,7 +128,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -192,7 +192,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -161,7 +161,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -252,7 +252,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -185,7 +185,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -177,7 +177,7 @@ u32 wants_reset; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -220,7 +220,7 @@ u32 wants_reset; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -114,7 +114,7 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -112,7 +112,7 @@ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -112,7 +112,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -114,7 +114,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -115,7 +115,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -118,7 +118,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -118,7 +118,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -118,7 +118,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -127,7 +127,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -116,7 +116,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2895/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -166,7 +166,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -192,7 +192,7 @@ int needs_reset = 0; unsigned bsp_apicid = 0; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -182,7 +182,7 @@ u32 wants_reset; msr_t msr; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -165,7 +165,7 @@ int needs_reset; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) +++ trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 17:46:50 2010 (r5258) @@ -145,7 +145,7 @@ struct mem_controller ctrl[8]; unsigned nodes; - if (!((cpu_init_detectedx) || (!boot_cpu()))) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */

1 0

[PATCH]Remove fallback/normal decision from mainboards' romstage.c
by Patrick Georgi 18 Mar '10

18 Mar '10

Hi, this is a follow up patch to my previous patch. While the previous one handled the boards with support for old-style failover, this one take care of the other boards (that "only" did normal/fallback) It's abuild tested and boot-tested with kontron/986lcd-m (which is affected due to the changes in src/cpu/intel) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

4 8

[commit] r5257 - in trunk/src: arch/i386 arch/i386/lib cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/pistachio mainboard/a...
by repository service 18 Mar '10

18 Mar '10

Author: oxygene Date: Thu Mar 18 17:18:58 2010 New Revision: 5257 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5257 Log: Remove fallback/normal handling in mainboards' romstage.c like r5255 did for failover/fallback/normal mainboards. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Deleted: trunk/src/arch/i386/lib/failover.c trunk/src/arch/i386/lib/failover.lds trunk/src/mainboard/amd/mahogany/cache_as_ram_auto.c Modified: trunk/src/arch/i386/Makefile.inc trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/dell/s1850/failover.c trunk/src/mainboard/emulation/qemu-x86/failover.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/intel/jarrell/failover.c trunk/src/mainboard/intel/xe7501devkit/failover.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/olpc/btest/failover.c trunk/src/mainboard/olpc/rev_a/failover.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/x6dai_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g/failover.c trunk/src/mainboard/supermicro/x6dhe_g2/failover.c trunk/src/mainboard/supermicro/x6dhr_ig/failover.c trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-m/failover.c trunk/src/mainboard/via/epia-n/failover.c Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/arch/i386/Makefile.inc Thu Mar 18 17:18:58 2010 (r5257) @@ -87,7 +87,6 @@ crt0s := ldscripts := ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb -ldscripts += $(src)/arch/i386/lib/failover.lds ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/entry16.inc ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -160,12 +159,6 @@ ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds endif -ifeq ($(CONFIG_BIG_BOOTBLOCK),y) -ifeq ($(CONFIG_ROMCC),y) -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc -endif -endif - ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/i386/llshell/llshell.inc endif @@ -196,10 +189,6 @@ ifeq ($(CONFIG_ROMCC),y) ROMCCFLAGS ?= -mcpu=p2 -O2 -$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - printf " ROMCC failover.inc\n" - $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h printf " ROMCC romstage.inc\n" $(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@ Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -25,30 +25,6 @@ { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -27,30 +27,6 @@ { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Thu Mar 18 17:18:58 2010 (r5257) @@ -27,30 +27,6 @@ { unsigned int cpu_reset = 0; -#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK -#if CONFIG_USE_FALLBACK_IMAGE == 1 - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } else { - /* This is the primary cpu how should I boot? */ - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - fallback_image: -#endif -#endif - real_main(bist); /* No servicable parts below this line .. */ Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,14 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb700_lpc_port80(); */ - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -161,6 +111,15 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb700_lpc_port80(); */ + sb700_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -94,60 +94,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sb600_lpc_port80(); - /* sb600_pci_port80(); */ - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - normal_image: - post_code(0x01); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */ - - fallback_image: - post_code(0x02); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -157,6 +107,15 @@ (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sb600_lpc_port80(); + /* sb600_pci_port80(); */ + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/arima/hdama/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -95,66 +95,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -169,6 +114,15 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -176,68 +176,8 @@ pnp_exit_ext_func_mode(GPIO_DEV); } -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* unsigned last_boot_normal_x = last_boot_normal(); */ - /* FIXME */ - unsigned last_boot_normal_x = 1; - - sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - enable_rom_decode(); - - print_info("now booting... fallback\r\n"); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU, how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - /* print_info("JMP normal image\r\n"); */ - - __asm__ __volatile__("jmp __normal_image": - :"a" (bist), "b" (cpu_init_detectedx)); - -fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, @@ -254,6 +194,21 @@ sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\r\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); enable_rom_decode(); Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/broadcom/blast/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -106,74 +106,10 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -189,6 +125,20 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/dell/s1850/failover.c ============================================================================== --- trunk/src/mainboard/dell/s1850/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/dell/s1850/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -15,35 +15,5 @@ static unsigned long main(unsigned long bist) { /* skip all this nonsense as we are not doing fallback yet */ - goto fallback_image; - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/emulation/qemu-x86/failover.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/emulation/qemu-x86/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -10,20 +10,5 @@ static void main(void) { -#if 0 - /* Is this a cpu reset? */ - if (cpu_init_detected()) { - if (last_boot_normal()) { - asm("jmp __normal_image"); - } else { - asm("jmp __cpu_reset"); - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - asm("jmp __normal_image"); - } -#endif } Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/ibm/e325/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -93,67 +93,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +123,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/ibm/e326/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -92,68 +92,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -179,6 +122,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/intel/jarrell/failover.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/intel/jarrell/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/intel/xe7501devkit/failover.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/intel/xe7501devkit/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -13,36 +13,5 @@ static unsigned long main(unsigned long bist) { - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - - check_cmos_failed(); - - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); -#if 0 - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); -#endif - fallback_image: return bist; } Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -101,60 +101,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ device_t dev; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; @@ -163,6 +113,14 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -153,73 +153,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - bcm5785_enable_rom(); - - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; - -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, @@ -237,6 +174,20 @@ int needs_reset; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + bcm5785_enable_rom(); + + bcm5785_enable_lpc(); + + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -133,8 +133,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -156,68 +154,12 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. #define RC0 (2<<8) #define RC1 (1<<8) -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, @@ -233,6 +175,18 @@ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); char *p ; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { //init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/newisys/khepri/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -108,71 +108,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -188,6 +128,16 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/olpc/btest/failover.c ============================================================================== --- trunk/src/mainboard/olpc/btest/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/olpc/btest/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } Modified: trunk/src/mainboard/olpc/rev_a/failover.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/olpc/rev_a/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -112,8 +112,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -146,65 +144,8 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -220,6 +161,18 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/supermicro/x6dai_g/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dai_g/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/supermicro/x6dhe_g/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhe_g/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/supermicro/x6dhe_g2/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhe_g2/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/supermicro/x6dhr_ig/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhr_ig/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -14,34 +14,5 @@ static unsigned long main(unsigned long bist) { - /* Did just the cpu reset? */ - if (memory_initialized()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: return bist; } Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -103,61 +103,10 @@ #include "tn_post_code.c" #include "speaker.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -165,6 +114,15 @@ struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + technexion_post_code_init(); technexion_post_code(LED_MESSAGE_START); Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -100,60 +100,10 @@ #include "cpu/amd/model_fxx/fidvid.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -162,6 +112,15 @@ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2735/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -80,53 +80,7 @@ #include "cpu/x86/car/copy_and_run.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -#include "southbridge/intel/i82801ex/cmos_failover.c" - -void real_main(unsigned long bist); - -void amd64_main(unsigned long bist) -{ - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else { - check_cmos_failed(); - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - ); - cpu_reset: -// post_code(0x24); -#if 0 - //CPU reset will reset memtroller ??? - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - ); -#endif - - fallback_image: -// post_code(0x25); - real_main(bist); -} -void real_main(unsigned long bist) -#else void amd64_main(unsigned long bist) -#endif { static const struct mem_controller memctrl[] = { { Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2850/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -93,72 +93,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -173,6 +112,16 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2875/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -84,69 +84,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx)/* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +114,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -85,68 +85,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -172,6 +115,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2881/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -98,72 +98,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -88,68 +88,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -175,6 +118,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2885/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -98,72 +98,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the amd8111 */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -179,6 +118,16 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the amd8111 */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2891/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -77,8 +77,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -112,68 +110,8 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -189,6 +127,18 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s2892/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -82,8 +82,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -101,66 +99,8 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -176,6 +116,18 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s4880/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -111,68 +111,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const struct mem_controller cpu[] = { { .node_id = 0, @@ -222,6 +165,15 @@ int needs_reset; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/tyan/s4882/romstage.c Thu Mar 18 17:18:58 2010 (r5257) @@ -119,67 +119,11 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#if CONFIG_USE_FALLBACK_IMAGE == 1 - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */ - ); - - fallback_image: - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, @@ -201,6 +145,15 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/via/epia-m/failover.c ============================================================================== --- trunk/src/mainboard/via/epia-m/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/via/epia-m/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; } Modified: trunk/src/mainboard/via/epia-n/failover.c ============================================================================== --- trunk/src/mainboard/via/epia-n/failover.c Thu Mar 18 06:57:32 2010 (r5256) +++ trunk/src/mainboard/via/epia-n/failover.c Thu Mar 18 17:18:58 2010 (r5257) @@ -9,27 +9,5 @@ static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }

1 0

[PATCH] use memset
by Myles Watson 18 Mar '10

18 Mar '10

I was having trouble with stack corruption. Using memset (C) instead of clear_memory(asm) speeds it up by almost a factor of 2 for a 1M region. TSC difference with clear_memory 0xFA884D TSC difference with memset 0x826742 Anyway, this patch removes a couple of files that don't need to exist anymore, given that only K8 was using clear_memory. SIgned-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 4

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coreboot March 2010