coreboot March 2010

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[commit] r5254 - in trunk/src: cpu/amd/model_lx northbridge/amd/lx southbridge/amd/cs5536 southbridge/amd/sb600 southbridge/amd/sb700
by repository service 18 Mar '10

18 Mar '10

Author: stepan Date: Wed Mar 17 23:09:26 2010 New Revision: 5254 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5254 Log: more warnings gone... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/amd/lx/northbridgeinit.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c trunk/src/southbridge/amd/sb600/sb600_hda.c trunk/src/southbridge/amd/sb600/sb600_sata.c trunk/src/southbridge/amd/sb600/sb600_usb.c trunk/src/southbridge/amd/sb700/sb700_hda.c trunk/src/southbridge/amd/sb700/sb700_usb.c Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c ============================================================================== --- trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:09:26 2010 (r5254) @@ -290,7 +290,7 @@ if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) { printk_err("do_vsmbios: Failed to load VSA.\n"); } - buf = VSA2_BUFFER; + buf = (unsigned char *)VSA2_BUFFER; printk_debug("buf %p *buf %d buf[256k] %d\n", buf, buf[0], buf[SMM_SIZE * 1024]); printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", @@ -501,15 +501,15 @@ printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n", ebp, esp, edi, esi); printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n", - ip, cs, flags); + (u32)ip, (u32)cs, (u32)flags); printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n", - gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff); + (u16)(gsfs >> 16), (u16)(gsfs & 0xffff), (u16)(dses >> 16), (u16)(dses & 0xffff)); // cases in a good compiler are just as good as your own tables. switch (intnumber) { case 0 ... 15: // These are not BIOS service, but the CPU-generated exceptions - printk_info("biosint: Oops, exception %u\n", intnumber); + printk_info("biosint: Oops, exception 0x%x\n", (u32)intnumber); if (esp < 0x1000) { printk_debug("Stack contents: "); while (esp < 0x1000) { @@ -537,7 +537,7 @@ &ebx, &edx, &ecx, &eax, &flags); break; default: - printk_info("BIOSINT: Unsupport int #0x%x\n", intnumber); + printk_info("BIOSINT: Unsupported int #0x%x\n", (u32)intnumber); break; } if (ret) @@ -617,16 +617,7 @@ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; - unsigned long eax = *peax; - unsigned long flags = *pflags; - unsigned short func = (unsigned short)eax; + unsigned short func = (unsigned short)*peax; int retval = 0; unsigned short devid, vendorid, devfn; short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ @@ -740,7 +731,7 @@ unsigned long *ecx, unsigned long *eax, unsigned long *flags) { int res = -1; - printk_debug("handleint21, eax 0x%x\n", *eax); + printk_debug("handleint21, eax 0x%x\n", (u32)*eax); switch (*eax & 0xffff) { case 0x5f19: break; Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:09:26 2010 (r5254) @@ -253,16 +253,16 @@ } iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); iol = inl(GPIOL_EVENTS_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); iol = inl(GPIOL_INPUT_INVERT_ENABLE); - printk_debug("IOR 0x%08X is now 0x%08X\n", + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); iol = inl(GPIO_MAPPER_X); - printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, + printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); #endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } Modified: trunk/src/northbridge/amd/lx/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridgeinit.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/northbridgeinit.c Wed Mar 17 23:09:26 2010 (r5254) @@ -107,7 +107,7 @@ msr.lo = gl->lo; msr.hi = gl->hi; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3 + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); // GX3 } static void ShadowInit(struct gliutable *gl) @@ -147,7 +147,7 @@ msr.lo = sizebytes; wrmsr(gl->desc_name, msr); // MSR - see table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -173,7 +173,7 @@ msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -190,7 +190,7 @@ msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff; wrmsr(gl->desc_name, msr); // MSR - See table above - printk_debug("%s: MSR 0x%08x, val 0x%08x:0x%08x\n", __func__, + printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/northbridge/amd/lx/raminit.c Wed Mar 17 23:09:26 2010 (r5254) @@ -27,12 +27,13 @@ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; -void banner(char *s) +void banner(const char *s) { print_debug("==========================="); print_debug(s); print_debug("======================================\r\n"); } + void hcf(void) { print_emerg("DIE\r\n"); Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Wed Mar 17 23:09:26 2010 (r5254) @@ -35,7 +35,7 @@ #include "cs5536.h" struct msrinit { - uint32_t msrnum; + u32 msrnum; msr_t msr; }; @@ -61,8 +61,8 @@ }; struct acpiinit { - uint16_t ioreg; - uint32_t regdata; + u16 ioreg; + u32 regdata; }; struct acpiinit acpi_init_table[] = { @@ -95,7 +95,7 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -111,8 +111,8 @@ /* ***************************************************************************/ static void pmChipsetInit(void) { - uint32_t val = 0; - uint16_t port; + u32 val = 0; + u16 port; port = (PMS_IO_BASE + 0x010); val = 0x0E00; /* 1ms */ @@ -427,7 +427,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint8_t *bar; + u32 bar; msr_t msr; device_t dev; @@ -443,7 +443,7 @@ /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); @@ -455,7 +455,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); @@ -483,8 +483,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UDCDEVCTL, read32(bar + UDCDEVCTL) | UDC_SD_SET); @@ -493,8 +492,7 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint8_t *) pci_read_config32(dev, - PCI_BASE_ADDRESS_0); + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); } @@ -524,7 +522,7 @@ { device_t dev; msr_t msr; - uint32_t msrnum; + u32 msrnum; struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; struct msrinit *csi; Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Mar 17 23:09:26 2010 (r5254) @@ -32,13 +32,11 @@ /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ msr.hi = msr.lo = 0x00000000; - if (CS5536_GLINK_PORT_NUM <= 4) { - msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); - } else { - msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); - } +#if CS5536_GLINK_PORT_NUM <= 4 + msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); +#else + msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); +#endif wrmsr(GLPCI_ExtMSR, msr); } Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_hda.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_hda.c Wed Mar 17 23:09:26 2010 (r5254) @@ -30,7 +30,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -static int set_bits(u8 * port, u32 mask, u32 val) +static int set_bits(u32 port, u32 mask, u32 val) { u32 dword; int count; @@ -59,7 +59,7 @@ return 0; } -static u32 codec_detect(u8 * base) +static u32 codec_detect(u32 base) { u32 dword; @@ -172,7 +172,7 @@ * no response would imply that the codec is non-operative */ -static int wait_for_ready(u8 *base) +static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -195,7 +195,7 @@ * is non-operative */ -static int wait_for_valid(u8 *base) +static int wait_for_valid(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -212,7 +212,7 @@ return 1; } -static void codec_init(u8 * base, int addr) +static void codec_init(u32 base, int addr) { u32 dword; u32 *verb; @@ -254,7 +254,7 @@ printk_debug("verb loaded!\n"); } -static void codecs_init(u8 * base, u32 codec_mask) +static void codecs_init(u32 base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -267,7 +267,7 @@ { u8 byte; u32 dword; - u8 *base; + u32 base; struct resource *res; u32 codec_mask; device_t sm_dev; @@ -301,8 +301,8 @@ if (!res) return; - base = (u8 *) ((u32)res->base); - printk_debug("base = %p\n", base); + base = ((u32)res->base); + printk_debug("base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: trunk/src/southbridge/amd/sb600/sb600_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sata.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_sata.c Wed Mar 17 23:09:26 2010 (r5254) @@ -27,7 +27,7 @@ #include <arch/io.h> #include "sb600.h" -int sata_drive_detect(int portnum, u16 iobar) +static int sata_drive_detect(int portnum, u16 iobar) { u8 byte, byte2; int i = 0; @@ -59,7 +59,7 @@ u8 byte; u16 word; u32 dword; - u8 *sata_bar5; + u32 sata_bar5; u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; @@ -84,7 +84,7 @@ pci_write_config8(sm_dev, 0xaf, byte); /* get base addresss */ - sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF); + sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; @@ -96,7 +96,7 @@ printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ + printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; Modified: trunk/src/southbridge/amd/sb600/sb600_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_usb.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb600/sb600_usb.c Wed Mar 17 23:09:26 2010 (r5254) @@ -88,13 +88,13 @@ u8 byte; u16 word; u32 dword; - u8 *usb2_bar0; + u32 usb2_bar0; /* dword = pci_read_config32(dev, 0xf8); */ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ - usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%p\n", usb2_bar0); + usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; + printk_info("usb2_bar0=0x%x\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; Modified: trunk/src/southbridge/amd/sb700/sb700_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_hda.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb700/sb700_hda.c Wed Mar 17 23:09:26 2010 (r5254) @@ -30,7 +30,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -static int set_bits(u8 * port, u32 mask, u32 val) +static int set_bits(u32 port, u32 mask, u32 val) { u32 dword; int count; @@ -59,7 +59,7 @@ return 0; } -static u32 codec_detect(u8 * base) +static u32 codec_detect(u32 base) { u32 dword; @@ -94,7 +94,7 @@ * Wait 50usec for for the codec to indicate it is ready * no response would imply that the codec is non-operative */ -static int wait_for_ready(u8 *base) +static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -116,7 +116,7 @@ * the previous command. No response would imply that the code * is non-operative */ -static int wait_for_valid(u8 *base) +static int wait_for_valid(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -133,7 +133,7 @@ return 1; } -static void codec_init(u8 * base, int addr) +static void codec_init(u32 base, int addr) { u32 dword; @@ -153,7 +153,7 @@ printk_debug("%x(th) codec viddid: %08x\n", addr, dword); } -static void codecs_init(u8 * base, u32 codec_mask) +static void codecs_init(u32 base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -166,7 +166,7 @@ { u8 byte; u32 dword; - u8 *base; + u32 base; struct resource *res; u32 codec_mask; device_t sm_dev; @@ -202,8 +202,8 @@ if (!res) return; - base = (u8 *) ((u32)res->base); - printk_debug("base = %p\n", base); + base = (u32)res->base; + printk_debug("base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Wed Mar 17 23:08:51 2010 (r5253) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Wed Mar 17 23:09:26 2010 (r5254) @@ -34,7 +34,6 @@ { u8 byte; u16 word; - u32 dword; /* 6.1 Enable OHCI0-4 and EHCI Controllers */ device_t sm_dev; @@ -70,10 +69,8 @@ static void usb_init2(struct device *dev) { - u8 byte; - u16 word; u32 dword; - u8 *usb2_bar0; + u32 usb2_bar0; device_t sm_dev; u8 rev; @@ -84,8 +81,8 @@ /* dword |= 40; */ /* pci_write_config32(dev, 0xf8, dword); */ - usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF); - printk_info("usb2_bar0=%p\n", usb2_bar0); + usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; + printk_info("usb2_bar0=0x%x\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; @@ -123,6 +120,9 @@ /* Each step below causes the linux crashes. Leave them here * for future debugging. */ #if 0 + u8 byte; + u16 word; + /* RPR6.16 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); byte |= (1 << 6);

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[commit] r5256 - in trunk/src/southbridge/amd: rs780 sb600
by repository service 18 Mar '10

18 Mar '10

Author: zbao Date: Thu Mar 18 06:57:32 2010 New Revision: 5256 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5256 Log: trivial. Delelte double blank line. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c trunk/src/southbridge/amd/sb600/Kconfig Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_cmn.c Wed Mar 17 23:44:39 2010 (r5255) +++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Thu Mar 18 06:57:32 2010 (r5256) @@ -350,4 +350,3 @@ pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); } - Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Wed Mar 17 23:44:39 2010 (r5255) +++ trunk/src/southbridge/amd/sb600/Kconfig Thu Mar 18 06:57:32 2010 (r5256) @@ -20,4 +20,3 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC -

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[commit] r5255 - in trunk/src: arch/i386/lib mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8n_e mainboard/gigabyte/ga_2761gxdk m...
by repository service 17 Mar '10

17 Mar '10

Author: oxygene Date: Wed Mar 17 23:44:39 2010 New Revision: 5255 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5255 Log: Remove failover/fallback/normal handling in mainboards' romstage.c. That's newconfig stuff. 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/arch/i386/lib/failover_failover.lds trunk/src/mainboard/tyan/s2895/failover.c Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -131,80 +131,9 @@ #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - int last_boot_normal_flag = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_flag) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sb700_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_flag) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - #if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) - #endif - ; -} -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ - - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if (CONFIG_USE_FAILOVER_IMAGE==0) //#include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" @@ -218,7 +147,7 @@ #define DIMM2 0x52 #define DIMM3 0x53 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -227,6 +156,16 @@ u32 val; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sb700_pci_port80(); + } + post_code(0x30); if (bist == 0) { Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -154,82 +154,12 @@ #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -259,6 +189,16 @@ struct cpuid_result cpuid1; #endif + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -144,88 +144,15 @@ #endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - int last_boot_normal_flag = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_flag) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - /* mov bsp to bus 0xff when > 8 nodes */ - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_flag) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - #if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) - #endif - ; -} -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ - - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - - #if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -233,6 +160,17 @@ u32 val; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + /* mov bsp to bus 0xff when > 8 nodes */ + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + post_code(0x30); if (bist == 0) { Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -98,9 +98,6 @@ #endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ - || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -121,79 +118,8 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - - /* This is the primary CPU. How should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - -#if CONFIG_HAVE_FAILOVER_BOOT == 1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} - -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT == 1 -#if CONFIG_USE_FAILOVER_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE == 0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, @@ -208,6 +134,17 @@ unsigned nodes, bsp_apicid = 0; struct mem_controller ctrl[8]; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -152,9 +152,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - -#include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -178,77 +175,9 @@ pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the sis966 */ - sis966_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -264,6 +193,18 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the sis966 */ + sis966_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -150,8 +150,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -176,77 +174,10 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -263,6 +194,18 @@ unsigned bsp_apicid = 0; uint8_t tmp = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -155,8 +155,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "northbridge/amd/amdk8/early_ht.c" #if 0 @@ -197,78 +195,9 @@ } #endif - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { // RTC already inited - goto normal_image; //normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - //enable RTC - pc87417_enable_dev(RTC_DEV); - - /* Is this a deliberate reset by the bios */ - - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; - -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -287,6 +216,17 @@ int needs_reset; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + bcm5785_enable_rom(); + bcm5785_enable_lpc(); + //enable RTC + pc87417_enable_dev(RTC_DEV); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -130,82 +130,12 @@ #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -224,6 +154,16 @@ int needs_reset; int i; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -130,82 +130,12 @@ #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -224,6 +154,16 @@ int needs_reset; int i; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -130,82 +130,12 @@ #include "cpu/amd/model_fxx/fidvid.c" #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node @@ -224,6 +154,16 @@ int needs_reset; int i; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the rom access for 4M */ + amd8111_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -100,9 +100,6 @@ #endif /* CONFIG_USE_FAILOVER_IMAGE */ -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \ - || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -124,79 +121,8 @@ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - - /* This is the primary CPU. How should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - -fallback_image: - -#if CONFIG_HAVE_FAILOVER_BOOT == 1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} - -#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT == 1 -#if CONFIG_USE_FAILOVER_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE == 0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 1, 0, 0, @@ -211,6 +137,17 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/msi/ms7260/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -131,8 +131,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -154,74 +152,9 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned int last_boot_normal_x = last_boot_normal(); - - /* Is this a CPU only reset? Or is this a secondary CPU? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) - goto normal_image; - else - goto fallback_image; - } - - /* Nothing special needs to be done to find bus 0. */ - /* Allow the HT devices to be found. */ - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the MCP55. */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the BIOS? */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary CPU. How should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - -normal_image: - __asm__ volatile ("jmp __normal_image": - :"a" (bist), "b"(cpu_init_detectedx) - ); - -fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image": - :"a" (bist), "b"(cpu_init_detectedx) - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT == 1 -#if CONFIG_USE_FAILOVER_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE == 0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, @@ -237,6 +170,17 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the MCP55. */ + mcp55_enable_rom(); + } + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -145,8 +145,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -165,81 +163,12 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -249,6 +178,19 @@ u32 wants_reset; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + post_code(0x30); if (bist == 0) { Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -150,8 +150,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -177,77 +175,8 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -263,6 +192,18 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -193,8 +193,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -223,78 +221,13 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 -#if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); -#else - real_main(bist, cpu_init_detectedx); -#endif -#else -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -#endif -} - /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */ #define RC0 (2<<8) #define RC1 (1<<8) #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we don't know how to switch the SMBus to decode the CPU0 SPDs. So, The @@ -319,6 +252,18 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -139,8 +139,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -169,77 +167,9 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -255,6 +185,18 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -135,8 +135,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -165,81 +163,12 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -248,6 +177,19 @@ u32 wants_reset; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + post_code(0x30); if (bist == 0) { Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -138,8 +138,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -168,75 +166,6 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" @@ -282,7 +211,7 @@ pnp_exit_ext_func_mode(GPIO3_DEV); } -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -291,6 +220,19 @@ u32 wants_reset; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + post_code(0x30); if (bist == 0) { Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/tyan/s2895/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -116,8 +116,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -149,81 +147,9 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ -// post_code(0x22); - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: -// post_code(0x23); - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -// post_code(0x25); -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -240,6 +166,18 @@ struct mem_controller ctrl[8]; unsigned nodes; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/tyan/s2912/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -148,8 +148,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -176,77 +174,9 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, @@ -262,6 +192,18 @@ int needs_reset = 0; unsigned bsp_apicid = 0; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Mar 17 23:09:26 2010 (r5254) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Mar 17 23:44:39 2010 (r5255) @@ -144,8 +144,6 @@ #endif -#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -170,81 +168,12 @@ } -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - unsigned last_boot_normal_x = last_boot_normal(); - - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - set_bsp_node_CHtExtNodeCfgEn(); - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the mcp55 */ - mcp55_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ); - - fallback_image: -#if CONFIG_HAVE_FAILOVER_BOOT==1 - __asm__ volatile ("jmp __fallback_image" - : /* outputs */ - : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ - ) -#endif - ; -} -#endif -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ -#if CONFIG_HAVE_FAILOVER_BOOT==1 - #if CONFIG_USE_FAILOVER_IMAGE==1 - failover_process(bist, cpu_init_detectedx); - #else - real_main(bist, cpu_init_detectedx); - #endif -#else - #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); - #endif - real_main(bist, cpu_init_detectedx); -#endif -} - #if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); @@ -253,6 +182,19 @@ u32 wants_reset; msr_t msr; + if (!((cpu_init_detectedx) || (!boot_cpu()))) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + set_bsp_node_CHtExtNodeCfgEn(); + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the mcp55 */ + mcp55_enable_rom(); + } + post_code(0x30); if (bist == 0) {

1 0

[PATCH]: Configure the GFX mode of RS780
by Bao, Zheng 17 Mar '10

17 Mar '10

This patch configures the toppology of rs780 graphics. The new gfx_dual_slot option 2 is for the board which can configure the double/single mode. In that case, we need to know whether a device is plugged behind DEV 3. So the is_dev3_present() is needed. This doesn't help mahogany much. You will need in the future. Add an option for HDMI display. If you need it, just uncomment it. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/mainboard/amd/mahogany_fam10/mainboard.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 5223) +++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy) @@ -35,6 +35,12 @@ uint64_t uma_memory_base, uma_memory_size; +/* This function is stub for mahogany. */ +u8 is_dev3_present() +{ + return 0; +} + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. Index: src/mainboard/amd/mahogany_fam10/mainboard.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 5223) +++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy) @@ -35,6 +35,12 @@ uint64_t uma_memory_base, uma_memory_size; +/* This function is stub for mahogany. */ +u8 is_dev3_present() +{ + return 0; +} + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. Index: src/southbridge/amd/rs780/rs780_gfx.c =================================================================== --- src/southbridge/amd/rs780/rs780_gfx.c (revision 5223) +++ src/southbridge/amd/rs780/rs780_gfx.c (working copy) @@ -37,6 +37,7 @@ void set_pcie_reset(); void set_pcie_dereset(); +u8 is_dev3_present(); #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC @@ -430,7 +431,8 @@ //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1; vgainfo.ulBootUpReqDisplayVector = 0; //? vgainfo.ulOtherDisplayMisc = 0; //? - vgainfo.ulDDISlot1Config = 0x000c0011; //0; //? + vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA + //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI vgainfo.ulDDISlot2Config = 0x00130022; //0; //? vgainfo.ucMemoryType = 2; /* UMA Channel Number: 1 or 2. */ @@ -989,20 +991,6 @@ /* GFX Core Initialization */ //if (port == 2) return; - /* step 1, lane reversal (only need if CMOS option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); - } - printk_info("rs780_gfx_init step1.\n"); - - /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ - /* AMD calls the configuration CrossFire */ - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); - /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { } @@ -1182,11 +1170,70 @@ /* Single-port/Dual-port configureation. */ switch (cfg->gfx_dual_slot) { case 0: - single_port_configuration(nb_dev, dev); + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk_info("rs780_gfx_init step1.\n"); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk_info("If dev3.., single port. Do nothing.\n"); + } + break; case 1: + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk_info("rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; + /* Some boards are special, the single and dual slots can be configured and + * the graphics behind dev 3 can be detected. */ + case 2: + if(is_dev3_present()){ + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk_info("rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk_info("rs780_gfx_init step2.\n"); + + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); + dual_port_configuration(nb_dev, dev); + }else{ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk_info("rs780_gfx_init step1.\n"); + printk_info("rs780_gfx_init step2.\n"); + + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk_info("If dev3.., single port. Do nothing.\n"); + } + } + break; default: printk_info("Incorrect configuration of external gfx slot.\n"); break;

2 1

[PATCH]Remove failover/fallback/normal decision from mainboards' romstage.c
by Patrick Georgi 17 Mar '10

17 Mar '10

Hi, attached patch removes the failover/fallback/normal decision from romstage.c files of mainboards that did failover. It is the first part of a larger effort. This mechanism was used by newconfig style builds and is not useful anymore since we dropped newconfig. In fact, in rare circumstances it might lead to coreboot hanging early on boot (when normal is selected - this should fix itself by three reboots, as coreboot reverts to fallback then) The code assumes that various places are visited twice on boot. That's not true anymore for Kconfig builds, no matter if the boards is using romstage as bootblock, or the tiny bootblock. Removing these assumptions simplifies the code and should help the user when trying to track the code flow. The change looks big, but it's really a couple of simple and relatively mechanical steps repeated for lots of boards: 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) As those changes are quite mechanical, but not easily automated, I'd prefer some additional eyeballs that look if the end result of the boards looks alike (they should be more similar to each other than before). The patch is build tested and boot tested on amd/serengeti_cheetah in SimNow. After the changes, the entire hardware init is ran on cold boot, on warm reset the hardware init that used to be in failover_process is skipped. The affected boards do not use __fallback_image or __normal_image anymore. The next step will a comparable change to the remaining boards. After that, I'll aim for the removal of the remaining uses of HAVE_FALLBACK_BOOT, USE_FALLBACK_IMAGE, HAVE_FAILOVER_BOOT, USE_FAILOVER_IMAGE and their definition in Kconfig. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[commit] r5253 - trunk/src/southbridge/intel/i82801dx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 23:08:51 2010 New Revision: 5253 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5253 Log: revert the faulty part of r5252 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 18:50:48 2010 (r5252) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 23:08:51 2010 (r5253) @@ -177,6 +177,30 @@ pci_write_config16(dev, LPC_EN, 0x300F); } +/* ICH4 does not mention HPET in the docs, but + * all ICH3 and ICH4 do have HPETs built in. + */ +static void enable_hpet(struct device *dev) +{ + u32 reg32; + u32 code = (0 & 0x3); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET. */ + /* + * Bits [16:15] Memory Address Range + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh + */ + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + pci_write_config32(dev, GEN_CNTL, reg32); + + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); +} + static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ @@ -207,6 +231,9 @@ /* Setup decode ports and LPC I/F enables. */ i82801dx_lpc_decode_en(dev); + + /* Initialize the High Precision Event Timers */ + enable_hpet(dev); } static void i82801dx_lpc_read_resources(device_t dev)

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ICH HPET
by Joseph Smith 17 Mar '10

17 Mar '10

FYI, The HPET code in i82801ex, does absolutely nothing. It reads the reg and configs it but does not write it back to the reg....... And ICH 0-4 does not support HPET and should be removed from code.... -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 3

[commit] r5252 - in trunk/src/southbridge/intel: i82801ax i82801bx i82801dx i82801ex
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 18:50:48 2010 New Revision: 5252 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5252 Log: fix HPET on some ICH southbridges Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Wed Mar 17 05:40:15 2010 (r5251) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Wed Mar 17 18:50:48 2010 (r5252) @@ -272,28 +272,6 @@ } } -static void enable_hpet(struct device *dev) -{ -#ifdef HPET_PRESENT - uint32_t reg32; - uint32_t code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -#endif -} - static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); @@ -326,9 +304,6 @@ /* Setup decode ports and LPC I/F enables. */ i82801ax_lpc_decode_en(dev, ich_model); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(dev); } static void i82801ax_lpc_read_resources(device_t dev) Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Mar 17 05:40:15 2010 (r5251) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Mar 17 18:50:48 2010 (r5252) @@ -272,28 +272,6 @@ } } -static void enable_hpet(struct device *dev) -{ -#ifdef HPET_PRESENT - uint32_t reg32; - uint32_t code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -#endif -} - static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); @@ -326,9 +304,6 @@ /* Setup decode ports and LPC I/F enables. */ i82801bx_lpc_decode_en(dev, ich_model); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(dev); } static void i82801bx_lpc_read_resources(device_t dev) Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 05:40:15 2010 (r5251) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 18:50:48 2010 (r5252) @@ -177,27 +177,6 @@ pci_write_config16(dev, LPC_EN, 0x300F); } -static void enable_hpet(struct device *dev) -{ - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - pci_write_config32(dev, GEN_CNTL, reg32); - - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -} - static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ @@ -228,9 +207,6 @@ /* Setup decode ports and LPC I/F enables. */ i82801dx_lpc_decode_en(dev); - - /* Initialize the High Precision Event Timers */ - enable_hpet(dev); } static void i82801dx_lpc_read_resources(device_t dev) Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 05:40:15 2010 (r5251) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 18:50:48 2010 (r5252) @@ -231,6 +231,7 @@ dword &= ~(3 << 15); /* clear it */ dword |= (code<<15); + pci_write_config32(dev, GEN_CNTL, dword); printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) ); }

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[PATCH] More i82801dx_lpc fixups
by Joseph Smith 17 Mar '10

17 Mar '10

More fixups for i82801dx_lpc.c code including, fixing i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL works, and get rid of HPET, ICH4 does not support it (btw, ICH5 is the first to support HPET). Build and boot tested. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Gigabyte GA-MA78GM-UD2H (rev. 1.0)
by Sebastian Fleer 17 Mar '10

17 Mar '10

Tiago Marques mentioned the Gigabyte GA-MA78GM-UD2H (rev. 1.0) as a possible coreboot target. Although I'd love to see coreboot support for my board I don't know if it is a very good candidate, since I can't find it for sale anymore (at least in Germany). Anyway, here is the output of flashrom, dmidecode, superiotool and lspci. Greetings Sebastian

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coreboot March 2010