coreboot March 2010

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[PATCH] printk cleanups
by Stefan Reinauer 22 Mar '10

22 Mar '10

See patch...

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build service results for r5265
by coreboot information 21 Mar '10

21 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5265 to the coreboot repository. This caused the following changes: Change Log: drop dead code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5265&device=atc-6220&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5265 - trunk/util/inteltool
by repository service 21 Mar '10

21 Mar '10

Author: stepan Date: Mon Mar 22 00:33:36 2010 New Revision: 5265 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5265 Log: drop dead code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/cpu.c Modified: trunk/util/inteltool/cpu.c ============================================================================== --- trunk/util/inteltool/cpu.c Sun Mar 21 23:35:58 2010 (r5264) +++ trunk/util/inteltool/cpu.c Mon Mar 22 00:33:36 2010 (r5265) @@ -154,10 +154,6 @@ //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO }; - static const msr_entry_t model6bx_per_core_msrs[] = { - // single core only - }; - static const msr_entry_t model6ex_global_msrs[] = { { 0x0017, "IA32_PLATFORM_ID" }, { 0x002a, "EBL_CR_POWERON" },

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Re: [coreboot] coreboot on "acer aspire 1520"
by Paweł Stawicki 21 Mar '10

21 Mar '10

W dniu 16 marca 2010 18:43 użytkownik Rudolf Marek <r.marek(a)assembler.cz>napisał: > Hi, > > Uh it has VT8235, so gen older then I expected, perhaps this chip is not so > well supported like vt8237 but it is quite similar. > > All it looks like a lot of work but without much gain for the community, of > course you can do that but it will take lot of time to make it work, maybe 6 > months or even more. > > Do you know how the EC is connected or what kind of embedded controller the > board has? > > Rudolf > 6 months seems long but I ready for that challenge :-) its a good chance to become familiar with the PC architecture. displaying logs only, took me 2 weeks so I'm prepared for that. ok, the EC is a M38857 chip (Renesas M3885 family) I don't know the board connections of it but I have a multimeter and a oscilloscope - so maybe I while figure it out in the future :-)

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build service results for r5264
by coreboot information 21 Mar '10

21 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5264 to the coreboot repository. This caused the following changes: Change Log: fix "make" after "rm -rf build" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5264&device=atc-6220&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5264 - trunk
by repository service 21 Mar '10

21 Mar '10

Author: stepan Date: Sun Mar 21 23:35:58 2010 New Revision: 5264 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5264 Log: fix "make" after "rm -rf build" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Mar 21 22:22:51 2010 (r5263) +++ trunk/Makefile Sun Mar 21 23:35:58 2010 (r5264) @@ -124,9 +124,11 @@ chmod +x .ccwrap scan-build $(CONFIG_SCANBUILD_REPORT_LOCATION) -analyze-headers --use-cc=$(top)/.ccwrap --use-c++=$(top)/.ccwrap $(MAKE) INNER_SCANBUILD=y else -all: coreboot +all: $(obj)/config.h coreboot endif +$(obj)/config.h: + $(MAKE) oldconfig ####################################################################### # Build the tools

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superiotool Makefile patch
by Christian Ruppert 21 Mar '10

21 Mar '10

Hey guys, please apply/commit my patch to the superiotool directory. Signed-off and brief description can be found in the patch itself. For further information please take a look at [1] and [2]. [1] http://www.gentoo.org/proj/en/qa/asneeded.xml [2] http://blog.flameeyes.eu/tag/asneeded/ -- Regards, Christian Ruppert Gentoo Linux Developer and Bugzilla Admin Fingerprint: 9B50 01DF E873 A0E4 126D 6C16 8B17 B68E 7FAE 7D38

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build service results for r5263
by coreboot information 21 Mar '10

21 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5263 to the coreboot repository. This caused the following changes: Change Log: Don't abuse LDFLAGS and fix linking with -Wl,--as-needed. Signed-off-by: Christian Ruppert <idl0r(a)gentoo.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5263&device=atc-6220&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5263 - trunk/util/superiotool
by repository service 21 Mar '10

21 Mar '10

Author: stepan Date: Sun Mar 21 22:22:51 2010 New Revision: 5263 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5263 Log: Don't abuse LDFLAGS and fix linking with -Wl,--as-needed. Signed-off-by: Christian Ruppert <idl0r(a)gentoo.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/Makefile Modified: trunk/util/superiotool/Makefile ============================================================================== --- trunk/util/superiotool/Makefile Fri Mar 19 22:57:40 2010 (r5262) +++ trunk/util/superiotool/Makefile Sun Mar 21 22:22:51 2010 (r5263) @@ -36,7 +36,7 @@ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) -LDFLAGS = -framework IOKit -framework DirectIO -lpci -lz +LIBS = -framework IOKit -framework DirectIO -lpci -lz endif # Support for PCI-attached "Super I/Os" (e.g. in VIA VT82686A/B). @@ -44,7 +44,7 @@ ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT -LDFLAGS += -lpci +LIBS += -lpci OBJS += pci.o via.o endif @@ -53,7 +53,7 @@ superiotool.o: *.c superiotool.h $(PROGRAM): $(OBJS) superiotool.h - $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) + $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin

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RFC porting of SB7x00/RS78x boards
by Rudolf Marek 21 Mar '10

21 Mar '10

Hi all, I went bit more through the code, looks overall very good! Thanks AMD! Before we start the porting efforts here is the list of stuff needs to be done. Is there anyone with spare time? 1) move fadt.c into sb700 directory 2) split ACPI dsl into smaller chunks, similar as we have for ICH7/945 3) Check why resourcemap.c is needed. The only change from default is change for maximum bus number settings which is set to 8. Not sure if we really need any limit here? 4) some DSDT methods are doing checks for Linux and do something with AC97 codec, I think it does not work anyway because Linux tells it is Windows to ACPI :) Some DSDT values should be generated using ACPIgen namely HPET and something else I forgot already. The ITE code should go to separate file, the _PTS method is doing something to SMI, which we don't want because we dont have any SMI trap handler. 5) The GFX reset stuff The Mahagony board has separate GFX reset GPIO because some PCIe 16x are shared with displayport. I think this has to be checked for each board if such GPIO reset is needed. 6) GPIO for IDE cable This is also board dependent and must be find out. 7) PCIe lanes setup. The RS780 has very flexible setup for PCIe lanes, some for them can be multiplexed for Display Port, some for HDMI etc... There is something written in the DS of RS780 but it is hard to understand that how it suppose to work. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 Each board can setup this differently, gpp_configuration = 0 means read it from STRAP which is good because we dont have to set it up. Is dual_slot - crossfire? Does TMDS here means DVI/HDMI? I try to get more ideas how this is supposed to work, maybe AMD folks can also help ;) Rudolf

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coreboot March 2010