coreboot March 2010

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build service results for r5277
by coreboot information 23 Mar '10

23 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5277 to the coreboot repository. This caused the following changes: Change Log: Fix reading HT link offsets. pci_read_config32 overwrites the real value, use another variable for that. Signed-off-by: Maximilian Thuermer <maximilian.thuermer(a)ziti.uni-heidelberg.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5277&device=sy-6ba-plus-ii… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] coreboot on "acer aspire 1520"
by Paweł Stawicki 23 Mar '10

23 Mar '10

Hm, The reason for the: noapic acpi=off is that I don't know how to make the acpi part for my board. 2010/3/23 Stefan Reinauer <stepan(a)coresystems.de> > On 3/22/10 12:41 AM, Paweł Stawicki wrote: > > /boot/vmlinuz-2.6.28.10 ro earlyprintk=serial,0x2f8,9600n8,keep no-hlt > noapic acpi=off > > > I was going to say it sure looks like an interrupt problem until I saw the > line which kind of makes it certain... > > any reason for noapic acpi=off? > >

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build service results for r5276
by coreboot information 23 Mar '10

23 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5276 to the coreboot repository. This caused the following changes: Change Log: Use coreboot-internal version of x86emu for the vgabios utility. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Build Log: Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5276&device=sy-6ba-plus-ii… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5275
by coreboot information 23 Mar '10

23 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5275 to the coreboot repository. This caused the following changes: Change Log: Prepare for using coreboot x86emu in userspace utility "vgabios" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Build Log: Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5275&device=sy-6ba-plus-ii… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5277 - trunk/src/cpu/amd/model_10xxx
by repository service 23 Mar '10

23 Mar '10

Author: oxygene Date: Tue Mar 23 16:58:29 2010 New Revision: 5277 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5277 Log: Fix reading HT link offsets. pci_read_config32 overwrites the real value, use another variable for that. Signed-off-by: Maximilian Thuermer <maximilian.thuermer(a)ziti.uni-heidelberg.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Mar 23 16:53:38 2010 (r5276) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Mar 23 16:58:29 2010 (r5277) @@ -702,25 +702,27 @@ */ BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) { + u32 reg; u32 val; /* get start of CPU HT Host Capabilities */ val = pci_read_config32(NODE_PCI(node, 0), 0x34); - val &= 0xFF; + val &= 0xFF; //reg offset of first link cap_count++; /* Traverse through the capabilities. */ do { - val = pci_read_config32(NODE_PCI(node, 0), val); + reg = pci_read_config32(NODE_PCI(node, 0), val); /* Is the capability block a HyperTransport capability block? */ - if ((val & 0xFF) == 0x08) { + if ((reg & 0xFF) == 0x08) { /* Is the HT capability block an HT Host Capability? */ - if ((val & 0xE0000000) == (1 << 29)) + if ((reg & 0xE0000000) == (1 << 29)) cap_count--; } - if (cap_count) - val = (val >> 8) & 0xFF; + + if(cap_count) + val = (reg >> 8) & 0xFF; //update reg offset } while (cap_count && val); *offset = (u8) val;

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[commit] r5276 - in trunk/util/vgabios: . include include/arch include/console x86emu
by repository service 23 Mar '10

23 Mar '10

Author: stepan Date: Tue Mar 23 16:53:38 2010 New Revision: 5276 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5276 Log: Use coreboot-internal version of x86emu for the vgabios utility. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Added: trunk/util/vgabios/include/ trunk/util/vgabios/include/arch/ trunk/util/vgabios/include/arch/io.h trunk/util/vgabios/include/console/ trunk/util/vgabios/include/console/console.h Deleted: trunk/util/vgabios/x86emu/ Modified: trunk/util/vgabios/Makefile trunk/util/vgabios/helper_exec.c trunk/util/vgabios/test.h trunk/util/vgabios/testbios.c Modified: trunk/util/vgabios/Makefile ============================================================================== --- trunk/util/vgabios/Makefile Tue Mar 23 16:49:44 2010 (r5275) +++ trunk/util/vgabios/Makefile Tue Mar 23 16:53:38 2010 (r5276) @@ -7,29 +7,27 @@ # CC = gcc -CFLAGS = -Wall -Ix86emu/include -O2 -g +CFLAGS = -Wall -Iinclude -I../../src/devices/oprom/include/ -O2 -g -INTOBJS = int10.o int15.o int16.o int1a.o inte6.o -OBJECTS = testbios.o helper_exec.o helper_mem.o $(INTOBJS) - -LIBS = x86emu/src/x86emu/libx86emu.a +INTOBJS = int10.o int15.o int16.o int1a.o inte6.o +X86EMUOBJS = sys.o decode.o ops.o ops2.o prim_ops.o fpu.o debug.o +OBJS = testbios.o helper_exec.o helper_mem.o $(INTOBJS) $(X86EMUOBJS) # user space pci is the only option right now. -OBJECTS += pci-userspace.o +OBJS += pci-userspace.o + +LIBS=-lpci all: testbios -testbios: $(OBJECTS) $(LIBS) - $(CC) -o testbios $(OBJECTS) $(LIBS) -lpci +testbios: $(OBJS) + $(CC) $(CFLAGS) -o $@ $^ $(LIBS) helper_exec.o: helper_exec.c test.h -x86emu/src/x86emu/libx86emu.a: - $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux - clean: - $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux clean rm -f *.o *~ testbios -distclean: clean - $(MAKE) -C x86emu/src/x86emu/ -f makefile.linux clean +%.o: ../../src/devices/oprom/x86emu/%.c + $(CC) $(CFLAGS) -include stdio.h -c -o $@ $^ + Modified: trunk/util/vgabios/helper_exec.c ============================================================================== --- trunk/util/vgabios/helper_exec.c Tue Mar 23 16:49:44 2010 (r5275) +++ trunk/util/vgabios/helper_exec.c Tue Mar 23 16:53:38 2010 (r5276) @@ -14,7 +14,7 @@ * in xf86EnableIO(). Otherwise we won't trap * on PIO. */ -#include <x86emu.h> +#include <x86emu/x86emu.h> #include "helper_exec.h" #include "test.h" #include <sys/io.h> Added: trunk/util/vgabios/include/arch/io.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/vgabios/include/arch/io.h Tue Mar 23 16:53:38 2010 (r5276) @@ -0,0 +1,4 @@ +#ifndef _ASM_IO_H +#define _ASM_IO_H +#include <sys/io.h> +#endif Added: trunk/util/vgabios/include/console/console.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/vgabios/include/console/console.h Tue Mar 23 16:53:38 2010 (r5276) @@ -0,0 +1,3 @@ +#ifndef _CONSOLE_CONSOLE_H +#define _CONSOLE_CONSOLE_H +#endif Modified: trunk/util/vgabios/test.h ============================================================================== --- trunk/util/vgabios/test.h Tue Mar 23 16:49:44 2010 (r5275) +++ trunk/util/vgabios/test.h Tue Mar 23 16:53:38 2010 (r5276) @@ -6,7 +6,7 @@ */ #ifndef XF86X86EMU_H_ #define XF86X86EMU_H_ -#include <x86emu.h> +#include <x86emu/x86emu.h> #define M _X86EMU_env Modified: trunk/util/vgabios/testbios.c ============================================================================== --- trunk/util/vgabios/testbios.c Tue Mar 23 16:49:44 2010 (r5275) +++ trunk/util/vgabios/testbios.c Tue Mar 23 16:53:38 2010 (r5276) @@ -10,7 +10,7 @@ #define die(x) { perror(x); exit(1); } #define warn(x) { perror(x); } -#include <x86emu.h> +#include <x86emu/x86emu.h> #include "helper_exec.h" #include "test.h" #include "pci-userspace.h" @@ -139,7 +139,6 @@ unsigned short initialip = 0, initialcs = 0, devfn = 0; X86EMU_intrFuncs intFuncs[256]; void X86EMU_setMemBase(void *base, size_t size); - void X86EMU_setabseg(void *abseg); void x86emu_dump_xregs(void); int X86EMU_set_debug(int debug); int debugflag = 0; @@ -277,7 +276,7 @@ current = &p; X86EMU_setMemBase(biosmem, sizeof(biosmem)); - X86EMU_setabseg(abseg); + M.abseg = (unsigned long)abseg; X86EMU_setupPioFuncs(&myfuncs); ioperm(0, 0x400, 1);

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[commit] r5275 - trunk/src/devices/oprom/x86emu
by repository service 23 Mar '10

23 Mar '10

Author: stepan Date: Tue Mar 23 16:49:44 2010 New Revision: 5275 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5275 Log: Prepare for using coreboot x86emu in userspace utility "vgabios" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/src/devices/oprom/x86emu/debug.h Modified: trunk/src/devices/oprom/x86emu/debug.h ============================================================================== --- trunk/src/devices/oprom/x86emu/debug.h Tue Mar 23 14:23:40 2010 (r5274) +++ trunk/src/devices/oprom/x86emu/debug.h Tue Mar 23 16:49:44 2010 (r5275) @@ -42,8 +42,10 @@ /*---------------------- Macros and type definitions ----------------------*/ +#ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVEL /* printf is not available in coreboot... use printk */ #define printf(x...) printk(BIOS_DEBUG, x) +#endif /* checks to be enabled for "runtime" */

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fam10 patch (offset calculation)
by Maximilian Thuermer 23 Mar '10

23 Mar '10

Sorry this took so long, here's the patch again with a sign off: Index: src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- src/cpu/amd/model_10xxx/init_cpus.c (revision 5256) +++ src/cpu/amd/model_10xxx/init_cpus.c (working copy) @@ -702,29 +702,32 @@ */ BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) { + u32 reg; u32 val; - + /* get start of CPU HT Host Capabilities */ val = pci_read_config32(NODE_PCI(node, 0), 0x34); - val &= 0xFF; + val &= 0xFF; //reg offset of first link cap_count++; /* Traverse through the capabilities. */ do { - val = pci_read_config32(NODE_PCI(node, 0), val); + reg = pci_read_config32(NODE_PCI(node, 0), val); /* Is the capability block a HyperTransport capability block? */ - if ((val & 0xFF) == 0x08) { + if ((reg & 0xFF) == 0x08) { /* Is the HT capability block an HT Host Capability? */ - if ((val & 0xE0000000) == (1 << 29)) + if ((reg & 0xE0000000) == (1 << 29)) cap_count--; } - if (cap_count) - val = (val >> 8) & 0xFF; + + if(cap_count) + val = (reg >> 8) & 0xFF; //update reg offset } while (cap_count && val); *offset = (u8) val; + /* If requested capability found val != 0 */ if (!cap_count) return TRUE; Signed-off-by: Maximilian Thuermer <maximilian.thuermer(a)ziti.uni-heidelberg.de>

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build service results for r5274
by coreboot information 23 Mar '10

23 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5274 to the coreboot repository. This caused the following changes: Change Log: fix newly introduced printk_foo warnings.. Interesting enough, console_printk was only used in a single place and duplicated a large part of console.h which is included in the same place. Thus, just drop console_printk.c and we're one down with console complexity Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5274&device=sy-6ba-plus-ii… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5274 - in trunk/src: arch/i386/lib include/console southbridge/amd/rs780 southbridge/intel/i82801dx
by repository service 23 Mar '10

23 Mar '10

Author: stepan Date: Tue Mar 23 14:23:40 2010 New Revision: 5274 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5274 Log: fix newly introduced printk_foo warnings.. Interesting enough, console_printk was only used in a single place and duplicated a large part of console.h which is included in the same place. Thus, just drop console_printk.c and we're one down with console complexity Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/arch/i386/lib/console_printk.c Modified: trunk/src/arch/i386/lib/console.c trunk/src/include/console/console.h trunk/src/include/console/loglevel.h trunk/src/southbridge/amd/rs780/rs780_gfx.c trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/arch/i386/lib/console.c ============================================================================== --- trunk/src/arch/i386/lib/console.c Tue Mar 23 07:49:16 2010 (r5273) +++ trunk/src/arch/i386/lib/console.c Tue Mar 23 14:23:40 2010 (r5274) @@ -5,7 +5,6 @@ #include "console_print.c" #else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ #include <console/console.h> -#include "console_printk.c" #endif /* CONFIG_USE_PRINTK_IN_CAR */ void console_init(void) Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Tue Mar 23 07:49:16 2010 (r5273) +++ trunk/src/include/console/console.h Tue Mar 23 14:23:40 2010 (r5274) @@ -29,104 +29,86 @@ extern int console_loglevel; int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define printk(x...) do_printk(x) - -#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) -#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg) -#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg) -#define printk_err(fmt, arg...) do_printk(BIOS_ERR ,fmt, ##arg) -#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) -#define printk_notice(fmt, arg...) do_printk(BIOS_NOTICE ,fmt, ##arg) -#define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) -#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) -#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg) - -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_EMERG -#undef printk_emerg -#define printk_emerg(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_ALERT -#undef printk_alert -#define printk_alert(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_CRIT -#undef printk_crit -#define printk_crit(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_ERR -#undef printk_err -#define printk_err(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_WARNING -#undef printk_warning -#define printk_warning(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_NOTICE -#undef printk_notice -#define printk_notice(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_INFO -#undef printk_info -#define printk_info(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_DEBUG -#undef printk_debug -#define printk_debug(fmt, arg...) do {} while(0) -#endif -#if CONFIG_MAXIMUM_CONSOLE_LOGLEVEL < BIOS_SPEW -#undef printk_spew -#define printk_spew(fmt, arg...) do {} while(0) -#endif - -#define print_emerg(STR) printk_emerg ("%s", (STR)) -#define print_alert(STR) printk_alert ("%s", (STR)) -#define print_crit(STR) printk_crit ("%s", (STR)) -#define print_err(STR) printk_err ("%s", (STR)) -#define print_warning(STR) printk_warning("%s", (STR)) -#define print_notice(STR) printk_notice ("%s", (STR)) -#define print_info(STR) printk_info ("%s", (STR)) -#define print_debug(STR) printk_debug ("%s", (STR)) -#define print_spew(STR) printk_spew ("%s", (STR)) - -#define print_emerg_char(CH) printk_emerg ("%c", (CH)) -#define print_alert_char(CH) printk_alert ("%c", (CH)) -#define print_crit_char(CH) printk_crit ("%c", (CH)) -#define print_err_char(CH) printk_err ("%c", (CH)) -#define print_warning_char(CH) printk_warning("%c", (CH)) -#define print_notice_char(CH) printk_notice ("%c", (CH)) -#define print_info_char(CH) printk_info ("%c", (CH)) -#define print_debug_char(CH) printk_debug ("%c", (CH)) -#define print_spew_char(CH) printk_spew ("%c", (CH)) - -#define print_emerg_hex8(HEX) printk_emerg ("%02x", (HEX)) -#define print_alert_hex8(HEX) printk_alert ("%02x", (HEX)) -#define print_crit_hex8(HEX) printk_crit ("%02x", (HEX)) -#define print_err_hex8(HEX) printk_err ("%02x", (HEX)) -#define print_warning_hex8(HEX) printk_warning("%02x", (HEX)) -#define print_notice_hex8(HEX) printk_notice ("%02x", (HEX)) -#define print_info_hex8(HEX) printk_info ("%02x", (HEX)) -#define print_debug_hex8(HEX) printk_debug ("%02x", (HEX)) -#define print_spew_hex8(HEX) printk_spew ("%02x", (HEX)) - -#define print_emerg_hex16(HEX) printk_emerg ("%04x", (HEX)) -#define print_alert_hex16(HEX) printk_alert ("%04x", (HEX)) -#define print_crit_hex16(HEX) printk_crit ("%04x", (HEX)) -#define print_err_hex16(HEX) printk_err ("%04x", (HEX)) -#define print_warning_hex16(HEX) printk_warning("%04x", (HEX)) -#define print_notice_hex16(HEX) printk_notice ("%04x", (HEX)) -#define print_info_hex16(HEX) printk_info ("%04x", (HEX)) -#define print_debug_hex16(HEX) printk_debug ("%04x", (HEX)) -#define print_spew_hex16(HEX) printk_spew ("%04x", (HEX)) - -#define print_emerg_hex32(HEX) printk_emerg ("%08x", (HEX)) -#define print_alert_hex32(HEX) printk_alert ("%08x", (HEX)) -#define print_crit_hex32(HEX) printk_crit ("%08x", (HEX)) -#define print_err_hex32(HEX) printk_err ("%08x", (HEX)) -#define print_warning_hex32(HEX) printk_warning("%08x", (HEX)) -#define print_notice_hex32(HEX) printk_notice ("%08x", (HEX)) -#define print_info_hex32(HEX) printk_info ("%08x", (HEX)) -#define print_debug_hex32(HEX) printk_debug ("%08x", (HEX)) -#define print_spew_hex32(HEX) printk_spew ("%08x", (HEX)) +#undef WE_CLEANED_UP_ALL_SIDE_EFFECTS +/* We saw some strange effects in the past like coreboot crashing while + * disabling cache as ram for a maximum console log level of 6 and above while + * it worked fine without. In order to catch such issues reliably we are + * always doing a function call to do_printk with the full number of arguments. + * This slightly increases the code size and some unprinted strings will end + * up in the final coreboot binary (most of them compressed). If you want to + * avoid this, do a + * #define WE_CLEANED_UP_ALL_SIDE_EFFECTS + */ +#ifdef WE_CLEANED_UP_ALL_SIDE_EFFECTS + +#define printk(LEVEL, fmt, args...) \ + do { \ + if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ + do_printk(LEVEL, fmt, ##args); \ + } \ + } while(0) + +#else + +#define printk(LEVEL, fmt, args...) \ + do { \ + if (CONFIG_MAXIMUM_CONSOLE_LOGLEVEL >= LEVEL) { \ + do_printk(LEVEL, fmt, ##args); \ + } else { \ + do_printk(BIOS_NEVER, fmt, ##args); \ + } \ + } while(0) +#endif + +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) + +#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) +#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) +#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) +#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) +#define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) +#define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) +#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) +#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) +#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) + +#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) +#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) +#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) +#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) +#define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) +#define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) +#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) +#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) +#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) #if CONFIG_CONSOLE_VGA == 1 void vga_console_init(void); Modified: trunk/src/include/console/loglevel.h ============================================================================== --- trunk/src/include/console/loglevel.h Tue Mar 23 07:49:16 2010 (r5273) +++ trunk/src/include/console/loglevel.h Tue Mar 23 14:23:40 2010 (r5274) @@ -15,6 +15,7 @@ #define BIOS_NOTICE 5 /* normal but significant condition */ #define BIOS_INFO 6 /* informational */ #define BIOS_DEBUG 7 /* debug-level messages */ -#define BIOS_SPEW 8 /* Way too many details */ +#define BIOS_SPEW 8 /* way too many details */ +#define BIOS_NEVER 9 /* these messages are never printed */ #endif /* LOGLEVEL_H */ Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Mar 23 07:49:16 2010 (r5273) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Mar 23 14:23:40 2010 (r5274) @@ -55,7 +55,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -67,7 +67,7 @@ */ static void rs780_gfx_read_resources(device_t dev) { - printk(BIOS_INFO, "rs780_gfx_read_resources.\n"); + printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -307,7 +307,7 @@ deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); command = pci_read_config16(dev, 0x04); @@ -583,10 +583,10 @@ u32 FB_Start, FB_End; #endif - printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); + printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); sysmem = rdmsr(0xc001001a); - printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); + printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); /* The system top memory in 780. */ pci_write_config32(nb_dev, 0x90, sysmem.lo); @@ -824,12 +824,12 @@ struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -866,11 +866,11 @@ break; } } - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n"); } static void dual_port_configuration(device_t nb_dev, device_t dev) @@ -980,7 +980,7 @@ struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* GFX Core Initialization */ @@ -1003,7 +1003,7 @@ set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 1 << 6 | 1 << 8 | 1 << 10); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_INFO, "misc 28 = %x\n", reg32); + printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); @@ -1021,7 +1021,7 @@ set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 0); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk(BIOS_INFO, "misc 28 = %x\n", reg32); + printk(BIOS_DEBUG, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); @@ -1062,7 +1062,7 @@ /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk(BIOS_INFO, "rs780_gfx_init step7.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step7.\n"); return; } @@ -1070,11 +1070,11 @@ /* 5.9.12.1 sets RCB timeout to be 25ms */ /* 5.9.12.2. RCB Cpl timeout on link down. */ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n"); /* step 5.9.12.3 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n"); /* step 5.9.12.4 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); @@ -1096,7 +1096,7 @@ /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n"); /* 5.9.12.10 Sets the timer in Config state from 20us to */ /* 5.9.12.11 De-asserts RX_EN in L0s. */ @@ -1169,15 +1169,14 @@ if (cfg->gfx_lane_reversal) { set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); } - printk_info("rs780_gfx_init step1.\n"); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - printk_info("device = %x\n", dev->path.pci.devfn >> 3); - if((dev->path.pci.devfn >> 3) == 2) + printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); + if((dev->path.pci.devfn >> 3) == 2) { single_port_configuration(nb_dev, dev); - else{ + } else { set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ - printk_info("If dev3.., single port. Do nothing.\n"); + printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3 } break; @@ -1187,17 +1186,17 @@ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs780_gfx_init step1.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); - printk_info("device = %x\n", dev->path.pci.devfn >> 3); + printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; default: - printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); break; } } Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Tue Mar 23 07:49:16 2010 (r5273) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Tue Mar 23 14:23:40 2010 (r5274) @@ -133,7 +133,7 @@ reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("Set power %s after power failure.\n", state); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -147,10 +147,10 @@ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ } else { - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); /* Disable NMI. */ } outb(reg8, 0x70); @@ -232,7 +232,7 @@ u32 reg32, hpet, val; /* Set HPET base address and enable it */ - printk_debug("Enabling HPET at 0x%x\n", HPET_ADDR); + printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR); reg32 = pci_read_config32(dev, GEN_CNTL); /* * Bit 17 is HPET enable bit. @@ -253,9 +253,9 @@ val &= 0x7; if ((val & 0x4) && (hpet == (val & 0x3))) { - printk_debug("HPET enabled at 0x%x\n", HPET_ADDR); + printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR); } else { - printk_err("HPET was not enabled correctly\n"); + printk(BIOS_WARNING, "HPET was not enabled correctly\n"); reg32 &= ~(1 << 17); /* Clear Enable */ pci_write_config32(dev, GEN_CNTL, reg32); }

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coreboot March 2010