coreboot March 2010

coreboot@coreboot.org

61 participants
434 discussions

Re: [coreboot] [flashrom] succesful flash write on Supermicro X8DTT-F
by Carl-Daniel Hailfinger 23 Mar '10

23 Mar '10

Hi, it seems superiotool doesn't detect this chip. On 23.03.2010 13:29, Taylan Develioglu wrote: > Supermicro X8DTT-F > http://www.supermicro.com/products/system/2U/6026/SYS-6026TT-TF.cfm > Winbond W83527HG > No public datasheet... > superiotool r5263 > Probing for ALi Super I/O at 0x3f0... > Failed. Returned data: id=0xffff, rev=0xff > Probing for ALi Super I/O at 0x370... > Failed. Returned data: id=0xffff, rev=0xff > Probing for Fintek Super I/O at 0x2e... > Failed. Returned data: vid=0x4000, id=0x73b0 > Possible ID. > Probing for Fintek Super I/O at 0x4e... > Failed. Returned data: vid=0x0000, id=0x111a > Possible ID. > Probing for ITE Super I/O (init=standard) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8761e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=it8228e) at 0x2e... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id=0xb073, rev=0xf > Possible ID. > Probing for ITE Super I/O (init=standard) at 0x4e... > Failed. Returned data: id=0x1a11, rev=0x0 > Probing for ITE Super I/O (init=it8761e) at 0x4e... > Failed. Returned data: id=0x1a11, rev=0x0 > Probing for ITE Super I/O (init=it8228e) at 0x4e... > Failed. Returned data: id=0x1a11, rev=0x0 > Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id=0x1a11, rev=0x0 > Possible ID. > Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... > Failed. Returned data: id=0xffff, rev=0xf > Probing for NSC Super I/O at 0x2e... > Failed. Returned data: port=0xff, port+1=0xff > Probing for NSC Super I/O at 0x4e... > Failed. Returned data: sid=0x1a, srid=0x00 > Probing for NSC Super I/O at 0x15c... > Failed. Returned data: port=0xff, port+1=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... > Failed. Returned data: id=0x1a, rev=0x11 > Possible ID. > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... > Failed. Returned data: id=0x00, rev=0x00 > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... > Failed. Returned data: id=0xff, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... > Failed. Returned data: id/oldid=0xb0/0x0f, rev=0x73 > Possible ID. > Probing for Winbond Super I/O (init=0x88) at 0x4e... > Failed. Returned data: id/oldid=0x1a/0x00, rev=0x11 > Probing for Winbond Super I/O (init=0x89) at 0x4e... > Failed. Returned data: id/oldid=0x1a/0x00, rev=0x11 > Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... > Failed. Returned data: id/oldid=0x1a/0x00, rev=0x11 > Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... > Failed. Returned data: id/oldid=0x1a/0x00, rev=0x11 > Possible ID. > Probing for Winbond Super I/O (init=0x88) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x88) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x89) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... > Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff > Probing for VIA Super I/O at 0x3f0... > PCI device 1106:0686 not found. > No Super I/O found > Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH] util/vgabios without own copy of x86emu
by Stefan Reinauer 23 Mar '10

23 Mar '10

See patch

2 3

h8qme-2+ won't compile anymore
by Knut Kujat 23 Mar '10

23 Mar '10

Morning, I downloaded the latest revision and tried to compile it for my board (supermicro h8qme-2+) but it fails compiling with: /home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/mainboard/supermicro/h8qme_fam10/crt0.initobj.o: In function `console_init': romstage.c:(.rom.text+0xcd23): undefined reference to `printk_info' /home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/mainboard/supermicro/h8qme_fam10/crt0.initobj.o: In function `mctAutoInitMCT_D': romstage.c:(.rom.text+0xcf19): undefined reference to `printk_debug' /home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/mainboard/supermicro/h8qme_fam10/crt0.initobj.o: In function `raminit_amdmct': romstage.c:(.rom.text+0xd58d): undefined reference to `printk_debug' romstage.c:(.rom.text+0xd5b3): undefined reference to `printk_debug' /home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/mainboard/supermicro/h8qme_fam10/crt0.initobj.o: In function `cache_as_ram_main': romstage.c:(.rom.text+0xdae4): undefined reference to `printk_debug' romstage.c:(.rom.text+0xddd2): undefined reference to `printk_info' romstage.c:(.rom.text+0xe0e6): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe10f): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe4de): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe4f0): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe501): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe7ba): undefined reference to `printk_info' romstage.c:(.rom.text+0xe8fc): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe93e): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe966): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe9c0): undefined reference to `printk_debug' romstage.c:(.rom.text+0xe9e7): undefined reference to `printk_debug' /home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/mainboard/supermicro/h8qme_fam10/crt0.initobj.o:romstage.c:(.rom.text+0xea2b): more undefined references to `printk_debug' follow collect2: ld returned 1 exit status make: *** [/home/knut/Documents/Coreboot/NewBuildSystem/5coreboot/build/coreboot.romstage] Error 1 thx, Knut Kujat.

4 4

[commit] r5270 - trunk/src/southbridge/intel/i82801dx
by repository service 23 Mar '10

23 Mar '10

Author: linux_junkie Date: Tue Mar 23 00:10:53 2010 New Revision: 5270 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5270 Log: Fix i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL works, and rewrite HPET code. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Mon Mar 22 17:35:38 2010 (r5269) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Tue Mar 23 00:10:53 2010 (r5270) @@ -37,6 +37,14 @@ #endif #define IO_APIC_ADDR 0xfec00000 + +/* + * HPET Memory Address Range. Possible values: + * 0xfed00000 for FED0_0000h - FED0_03FFh + * 0xfed01000 for FED0_1000h - FED0_13FFh + * 0xfed02000 for FED0_2000h - FED0_23FFh + * 0xfed03000 for FED0_3000h - FED0_33FFh + */ #define HPET_ADDR 0xfed00000 #define DEBUG_PERIODIC_SMIS 0 @@ -202,6 +210,10 @@ #define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ +#define GEN_PMCON_1 0xa0 +#define GEN_PMCON_2 0xa2 +#define GEN_PMCON_3 0xa4 + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Mon Mar 22 17:35:38 2010 (r5269) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Tue Mar 23 00:10:53 2010 (r5270) @@ -64,7 +64,6 @@ if (reg32 != (1 << 25)) die("APIC Error\n"); - /* TODO: From i82801ca, needed/useful on other ICH? */ *ioapic_index = 3; /* Select Boot Configuration register. */ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } @@ -91,37 +90,85 @@ pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); - } static void i82801dx_power_options(device_t dev) { - u8 byte; - int pwr_on = -1; + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + + int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; int nmi_option; - /* power after power fail */ - /* FIXME this doesn't work! */ /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = MAINBOARD_POWER_ON; + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + reg8 &= 0xfe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg8 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg8 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg8 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ + + pci_write_config8(dev, GEN_PMCON_3, reg8); + printk_info("Set power %s after power failure.\n", state); /* Set up NMI on errors. */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + reg8 = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - byte &= ~(1 << 7); /* Set NMI. */ - outb(byte, 0x70); + printk_info ("NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk_info ("NMI sources disabled.\n"); + reg8 |= ( 1 << 7); /* Disable NMI. */ } + outb(reg8, 0x70); + + /* Set SMI# rate down and enable CPU_SLP# */ + reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 |= (1 << 5); // CPUSLP_EN Desktop only + pci_write_config16(dev, GEN_PMCON_1, reg16); + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + /* Set up power management block and determine sleep mode */ + reg32 = inl(pmbase + 0x04); // PM1_CNT + + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 0); // SCI_EN + outl(reg32, pmbase + 0x04); } static void gpio_init(device_t dev) @@ -182,23 +229,36 @@ */ static void enable_hpet(struct device *dev) { - u32 reg32; - u32 code = (0 & 0x3); + u32 reg32, hpet, val; + /* Set HPET base address and enable it */ + printk_debug("Enabling HPET at 0x%x\n", HPET_ADDR); reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh + * Bit 17 is HPET enable bit. + * Bit 16:15 control the HPET base address. */ reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); + + hpet = HPET_ADDR >> 12; + hpet &= 0x3; + + reg32 |= (hpet << 15); + reg32 |= (1 << 17); /* Enable HPET. */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + /* Check to see whether it took */ + reg32 = pci_read_config32(dev, GEN_CNTL); + val = reg32 >> 15; + val &= 0x7; + + if ((val & 0x4) && (hpet == (val & 0x3))) { + printk_debug("HPET enabled at 0x%x\n", HPET_ADDR); + } else { + printk_err("HPET was not enabled correctly\n"); + reg32 &= ~(1 << 17); /* Clear Enable */ + pci_write_config32(dev, GEN_CNTL, reg32); + } } static void lpc_init(struct device *dev)

3 4

[PATCH] Remove warnings of Mahogany(_fam10)
by Bao, Zheng 23 Mar '10

23 Mar '10

Remove the building warnings. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/mainboard/amd/mahogany/mptable.c =================================================================== --- src/mainboard/amd/mahogany/mptable.c (revision 5265) +++ src/mainboard/amd/mahogany/mptable.c (working copy) @@ -39,6 +39,8 @@ extern void get_bus_conf(void); +void *smp_write_config_table(void *v); + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; Index: src/mainboard/amd/mahogany/acpi_tables.c =================================================================== --- src/mainboard/amd/mahogany/acpi_tables.c (revision 5265) +++ src/mainboard/amd/mahogany/acpi_tables.c (working copy) @@ -101,6 +101,7 @@ extern void get_bus_conf(void); +#if CONFIG_ACPI_SSDTX_NUM >= 1 static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; @@ -122,6 +123,7 @@ /* FIXME: need to update the GSI id in the ssdtx too */ } +#endif unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); Index: src/mainboard/amd/mahogany/mainboard.c =================================================================== --- src/mainboard/amd/mahogany/mainboard.c (revision 5265) +++ src/mainboard/amd/mahogany/mainboard.c (working copy) @@ -35,6 +35,10 @@ uint64_t uma_memory_base, uma_memory_size; +void set_pcie_dereset(void); +void set_pcie_reset(void); +void add_mainboard_resources(struct lb_memory *mem); + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. @@ -65,42 +69,16 @@ pci_write_config16(sm_dev, 0xA8, word); } -/******************************************************** -* mahogany uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66() -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} - /************************************************* * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -void mahogany_enable(device_t dev) +static void mahogany_enable(device_t dev) { - struct mainboard_config *mainboard = + /* leave it here for future. */ + /*struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - + */ printk_info("Mainboard MAHOGANY Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -144,17 +122,16 @@ #endif set_pcie_dereset(); - /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) +void add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", - uma_memory_base, uma_memory_size); + printk_info("uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif Index: src/mainboard/amd/mahogany/get_bus_conf.c =================================================================== --- src/mainboard/amd/mahogany/get_bus_conf.c (revision 5265) +++ src/mainboard/amd/mahogany/get_bus_conf.c (working copy) @@ -63,6 +63,8 @@ static u32 get_bus_conf_done = 0; +void get_bus_conf(void); + void get_bus_conf(void) { u32 apicid_base; Index: src/mainboard/amd/mahogany_fam10/acpi_tables.c =================================================================== --- src/mainboard/amd/mahogany_fam10/acpi_tables.c (revision 5265) +++ src/mainboard/amd/mahogany_fam10/acpi_tables.c (working copy) @@ -92,7 +92,8 @@ extern void get_bus_conf(void); extern void update_ssdt(void *ssdt); - +/* not tested yet. */ +#if 0 /* #if 0 //CONFIG_ACPI_SSDTX_NUM >= 1 */ static void update_ssdtx(void *ssdtx, int i) { u8 *PCI; @@ -115,6 +116,7 @@ /* FIXME: need to update the GSI id in the ssdtx too */ } +#endif unsigned long write_acpi_tables(unsigned long start) { @@ -129,11 +131,7 @@ acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; - acpi_header_t *ssdtx; - u8 *p; - int i; - get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn /* Align ACPI tables to 16 bytes */ Index: src/mainboard/amd/mahogany_fam10/devicetree.cb =================================================================== --- src/mainboard/amd/mahogany_fam10/devicetree.cb (revision 5265) +++ src/mainboard/amd/mahogany_fam10/devicetree.cb (working copy) @@ -143,5 +143,3 @@ # end end - - Index: src/mainboard/amd/mahogany_fam10/mptable.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mptable.c (revision 5265) +++ src/mainboard/amd/mahogany_fam10/mptable.c (working copy) @@ -39,6 +39,8 @@ extern void get_bus_conf(void); +void *smp_write_config_table(void *v); + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; Index: src/mainboard/amd/mahogany_fam10/mainboard.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mainboard.c (revision 5265) +++ src/mainboard/amd/mahogany_fam10/mainboard.c (working copy) @@ -35,6 +35,10 @@ uint64_t uma_memory_base, uma_memory_size; +void set_pcie_dereset(void); +void set_pcie_reset(void); +void add_mainboard_resources(struct lb_memory *mem); + /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. @@ -65,42 +69,16 @@ pci_write_config16(sm_dev, 0xA8, word); } -/******************************************************** -* mahogany uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66() -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} - /************************************************* * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -void mahogany_enable(device_t dev) +static void mahogany_enable(device_t dev) { - struct mainboard_config *mainboard = + /* leave it here for future. */ + /*struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; - + */ printk_info("Mainboard MAHOGANY Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -144,17 +122,16 @@ #endif set_pcie_dereset(); - /* get_ide_dma66(); */ } -int add_mainboard_resources(struct lb_memory *mem) +void add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) - printk_info("uma_memory_start=0x%x, uma_memory_size=0x%x \n", - uma_memory_base, uma_memory_size); + printk_info("uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif

1 1

[commit] r5273 - trunk/src/southbridge/amd/sb700
by repository service 23 Mar '10

23 Mar '10

Author: zbao Date: Tue Mar 23 07:49:16 2010 New Revision: 5273 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5273 Log: Remove the building warnings. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sata.c trunk/src/southbridge/amd/sb700/sb700_smbus.h Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Tue Mar 23 07:46:01 2010 (r5272) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Tue Mar 23 07:49:16 2010 (r5273) @@ -94,7 +94,6 @@ static void sb700_lpc_set_resources(struct device *dev) { struct resource *res; - u8 byte; pci_dev_set_resources(dev); Modified: trunk/src/southbridge/amd/sb700/sb700_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sata.c Tue Mar 23 07:46:01 2010 (r5272) +++ trunk/src/southbridge/amd/sb700/sb700_sata.c Tue Mar 23 07:49:16 2010 (r5273) @@ -26,7 +26,7 @@ #include <arch/io.h> #include "sb700.h" -int sata_drive_detect(int portnum, u16 iobar) +static int sata_drive_detect(int portnum, u16 iobar) { u8 byte, byte2; int i = 0; @@ -59,7 +59,7 @@ u16 word; u32 dword; u8 rev_id; - u8 *sata_bar5; + u32 sata_bar5; u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; @@ -89,7 +89,7 @@ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; /* get base addresss */ - sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF); + sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; @@ -101,7 +101,7 @@ printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ + printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* disable combined mode */ byte = pci_read_config8(sm_dev, 0xAD); Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Mar 23 07:46:01 2010 (r5272) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Mar 23 07:49:16 2010 (r5273) @@ -58,5 +58,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); + #endif

1 0

[commit] r5272 - trunk/src/southbridge/amd/rs780
by repository service 23 Mar '10

23 Mar '10

Author: zbao Date: Tue Mar 23 07:46:01 2010 New Revision: 5272 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5272 Log: Remove the building warnings. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/rs780/rs780.c trunk/src/southbridge/amd/rs780/rs780_cmn.c trunk/src/southbridge/amd/rs780/rs780_gfx.c trunk/src/southbridge/amd/rs780/rs780_pcie.c Modified: trunk/src/southbridge/amd/rs780/rs780.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780.c Tue Mar 23 07:25:55 2010 (r5271) +++ trunk/src/southbridge/amd/rs780/rs780.c Tue Mar 23 07:46:01 2010 (r5272) @@ -107,12 +107,12 @@ set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8); } -u32 get_vid_did(device_t dev) +static u32 get_vid_did(device_t dev) { return pci_read_config32(dev, 0); } -void rs780_nb_pci_table(device_t nb_dev) +static void rs780_nb_pci_table(device_t nb_dev) { /* NBPOR_InitPOR function. */ u8 temp8; u16 temp16; @@ -191,7 +191,7 @@ #endif } -void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) +static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24; @@ -214,27 +214,27 @@ pci_write_config8(dev, 0x04, 0x02); /* Program Straps. */ - strap = MMIOBase + 0x15020; + strap = (volatile u32 *)(MMIOBase + 0x15020); #if (CONFIG_GFXUMA == 1) *strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */ #else *strap = 0; /* 128M SP memory, 000 -> 128MB */ #endif - strap = MMIOBase + 0x15000; + strap = (volatile u32 *)(MMIOBase + 0x15000); *strap = 0x2c006300; - strap = MMIOBase + 0x15010; + strap = (volatile u32 *)(MMIOBase + 0x15010); *strap = 0x03015330; - //strap = MMIOBase + 0x15020; + //strap = (volatile u32 *)(MMIOBase + 0x15020); //*strap |= 0x00000040; /* Disable HDA device. */ - strap = MMIOBase + 0x15030; + strap = (volatile u32 *)(MMIOBase + 0x15030); *strap = 0x00001002; - strap = MMIOBase + 0x15040; + strap = (volatile u32 *)(MMIOBase + 0x15040); *strap = 0x00000000; - strap = MMIOBase + 0x15050; + strap = (volatile u32 *)(MMIOBase + 0x15050); *strap = 0x00000000; - strap = MMIOBase + 0x15220; + strap = (volatile u32 *)(MMIOBase + 0x15220); *strap = 0x03c03800; - strap = MMIOBase + 0x15060; + strap = (volatile u32 *)(MMIOBase + 0x15060); *strap = 0x00000000; /* BIF switches into normal functional mode. */ Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_cmn.c Tue Mar 23 07:25:55 2010 (r5271) +++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Tue Mar 23 07:46:01 2010 (r5272) @@ -252,8 +252,8 @@ u32 lc_state, reg, current_link_width, lane_mask; int8_t current, res = 0; u32 gfx_gpp_sb_sel; - void set_pcie_dereset(); - void set_pcie_reset(); + void set_pcie_dereset(void); + void set_pcie_reset(void); switch (port) { case 2 ... 3: @@ -265,6 +265,9 @@ case 9 ... 10: gfx_gpp_sb_sel = PCIE_CORE_INDEX_GPP; break; + default: + gfx_gpp_sb_sel = -1; + return 0; } while (count--) { Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Mar 23 07:25:55 2010 (r5271) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Mar 23 07:46:01 2010 (r5272) @@ -35,8 +35,8 @@ #include <cpu/x86/msr.h> #include "rs780.h" -void set_pcie_reset(); -void set_pcie_dereset(); +void set_pcie_reset(void); +void set_pcie_dereset(void); #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC @@ -89,7 +89,7 @@ MMIORANGE MMIO[8], CreativeMMIO[8]; -MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) +static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; for (i=0; i<8; i++) @@ -99,7 +99,7 @@ } return 0; } -void FreeMMIO(MMIORANGE* pMMIO) +static void FreeMMIO(MMIORANGE* pMMIO) { pMMIO->Base = 0; pMMIO->Limit = 0; @@ -115,7 +115,7 @@ #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 #define MMIO_ATTRIB_SKIP_ZERO 1<<2 -u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) +static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; MMIORANGE * TempRange; @@ -139,7 +139,7 @@ return 0; } -u8 FinalizeMMIO(MMIORANGE *pMMIO) +static u8 FinalizeMMIO(MMIORANGE *pMMIO) { int i, j, n = 0; for(i=0; i<8; i++) @@ -173,7 +173,7 @@ return n; } -CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) +static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { CIM_STATUS Status = CIM_UNSUPPORTED; u8 Bus, Dev, Reg, BusStart, BusEnd; @@ -241,11 +241,10 @@ return Status; } -void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) +static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) { int i, j, n = 7; device_t k8_f1; - u32 temp32; k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -296,17 +295,15 @@ volatile u32 * pointer; int i; u16 command; - u32 value, temp, Base32, Limit32; - CIM_STATUS Status; + u32 value; u16 deviceid, vendorid; device_t nb_dev = dev_find_slot(0, 0); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); - device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4)); - struct southbridge_amd_rs780_config *cfg = - (struct southbridge_amd_rs780_config *)dev->chip_info; + /* We definetely will use this in future. Just leave it here. */ + /*struct southbridge_amd_rs780_config *cfg = + (struct southbridge_amd_rs780_config *)dev->chip_info;*/ deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); @@ -430,7 +427,8 @@ //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1; vgainfo.ulBootUpReqDisplayVector = 0; //? vgainfo.ulOtherDisplayMisc = 0; //? - vgainfo.ulDDISlot1Config = 0x000c0011; //0; //? + vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA + //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI vgainfo.ulDDISlot2Config = 0x00130022; //0; //? vgainfo.ucMemoryType = 2; /* UMA Channel Number: 1 or 2. */ @@ -978,7 +976,6 @@ */ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) { - u16 reg16; u32 reg32; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; @@ -989,20 +986,6 @@ /* GFX Core Initialization */ //if (port == 2) return; - /* step 1, lane reversal (only need if CMOS option is enabled) */ - if (cfg->gfx_lane_reversal) { - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); - } - printk(BIOS_INFO, "rs780_gfx_init step1.\n"); - - /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ - /* AMD calls the configuration CrossFire */ - if (cfg->gfx_dual_slot) - set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk(BIOS_INFO, "rs780_gfx_init step2.\n"); - /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { } @@ -1182,9 +1165,35 @@ /* Single-port/Dual-port configureation. */ switch (cfg->gfx_dual_slot) { case 0: - single_port_configuration(nb_dev, dev); + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk_info("rs780_gfx_init step1.\n"); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk_info("If dev3.., single port. Do nothing.\n"); + } + break; case 1: + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk_info("rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk_info("rs780_gfx_init step2.\n"); + + printk_info("device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; default: Modified: trunk/src/southbridge/amd/rs780/rs780_pcie.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_pcie.c Tue Mar 23 07:25:55 2010 (r5271) +++ trunk/src/southbridge/amd/rs780/rs780_pcie.c Tue Mar 23 07:46:01 2010 (r5272) @@ -101,20 +101,6 @@ } } -static void pcie_init(struct device *dev) -{ - /* Enable pci error detecting */ - u32 dword; - - printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n"); - - /* System error enable */ - dword = pci_read_config32(dev, 0x04); - dword |= (1 << 8); /* System error enable */ - dword |= (1 << 30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); -} - /********************************************************************** **********************************************************************/ static void switching_gppsb_configurations(device_t nb_dev, device_t sb_dev) @@ -249,9 +235,6 @@ *****************************************/ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) { - u8 reg8; - u16 reg16; - device_t sb_dev; u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; @@ -406,44 +389,3 @@ switching_gpp_configurations(nb_dev, sb_dev); ValidatePortEn(nb_dev); } - -/***************************************** -* Compliant with CIM_33's PCIEMiscClkProg -*****************************************/ -void pcie_config_misc_clk(device_t nb_dev) -{ - u32 reg; - struct bus pbus; /* fake bus for dev0 fun1 */ - - reg = pci_read_config32(nb_dev, 0x4c); - reg |= 1 << 0; - pci_write_config32(nb_dev, 0x4c, reg); - - if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { - /* TXCLK Clock Gating */ - set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); - set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); - - /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); - reg &= ~(1 << 16); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); - } - - if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { - /* TXCLK Clock Gating */ - set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4); - set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); - set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6); - - /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); - reg &= ~(1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); - } - - reg = pci_read_config32(nb_dev, 0x4c); - reg &= ~(1 << 0); - pci_write_config32(nb_dev, 0x4c, reg); -}

1 0

[commit] r5271 - in trunk/src/southbridge/amd: rs690 sb600
by repository service 23 Mar '10

23 Mar '10

Author: zbao Date: Tue Mar 23 07:25:55 2010 New Revision: 5271 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5271 Log: Removing build warning of sb600 & rs690. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/rs690/rs690_early_setup.c trunk/src/southbridge/amd/sb600/sb600_smbus.h Modified: trunk/src/southbridge/amd/rs690/rs690_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs690/rs690_early_setup.c Tue Mar 23 00:10:53 2010 (r5270) +++ trunk/src/southbridge/amd/rs690/rs690_early_setup.c Tue Mar 23 07:25:55 2010 (r5271) @@ -128,7 +128,7 @@ /* * Compliant with CIM_33's ATINB_PrepareInit */ -static void get_cpu_rev() +static void get_cpu_rev(void) { u32 eax, ebx, ecx, edx; __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) @@ -171,7 +171,7 @@ * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ -static void rs690_htinit() +static void rs690_htinit(void) { /* * About HT, it has been done in enumerate_ht_chain(). @@ -229,7 +229,7 @@ * Function2: DRAM and HT technology Trace mode configuration * Function3: Miscellaneous configuration *******************************************************/ -static void k8_optimization() +static void k8_optimization(void) { device_t k8_f0, k8_f2, k8_f3; msr_t msr; @@ -443,7 +443,7 @@ } /* enable CFG access to Dev8, which is the SB P2P Bridge */ -static void enable_rs690_dev8() +static void enable_rs690_dev8(void) { set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); } @@ -453,14 +453,14 @@ /* * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). */ -static void rs690_before_pci_init() +static void rs690_before_pci_init(void) { } /* * The calling sequence is same as CIM. */ -static void rs690_early_setup() +static void rs690_early_setup(void) { device_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs690_early_setup()\n"); Modified: trunk/src/southbridge/amd/sb600/sb600_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_smbus.h Tue Mar 23 00:10:53 2010 (r5270) +++ trunk/src/southbridge/amd/sb600/sb600_smbus.h Tue Mar 23 07:25:55 2010 (r5271) @@ -58,5 +58,7 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); #endif

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Re: [coreboot] W83977EF vs. ASUS P2B-L vs. PS/2 keyboard vs. VGA BIOS - keyboard win
by Keith Hui 23 Mar '10

23 Mar '10

> I had the same problem with a P2B. > > news://news.gmane.org:119/hj1sjv$elg$1@ger.gmane.org > > I never got a reply :-( > > The function "pnp_enable" only ever disables functions, yet the keyboard > function of the superio starts off disabled. This is documented > behavior in the Winbond data sheet. > > The simplest fix is to change this function to actually do the enable / > disable. I don't have the code to hand, but if you grep for this > function name it should be obvious. > > MM > > PS. > The internet has the source: > > http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/devices/pnp_dev… > > Change > > 152 void pnp_enable(device_t dev) > 153 { > 154 if (!dev->enabled) { > 155 pnp_set_logical_device(dev); > 156 pnp_set_enable(dev, 0); > 157 } > 158 } > > To > > 152 void pnp_enable(device_t dev) > 153 { > 155 pnp_set_logical_device(dev); > 156 pnp_set_enable(dev, dev->enabled); > 158 } > > (This is from memory. I don't really understand all of this code, this > might not be the best fix.) I don't know for sure either, but this change sure did the trick. I can now log in through my trusty model M. Yay. :D Logical device 8 (GPIO 2) is still not enabled. But that can wait until we figure out what it does on a P2B. Also, COM2 works on P2B-L! That means it works on all boards with this superio chip. Now a word of warning. If serial port is enabled in both coreboot in SeaBIOS and they are different, it may end up booting extremely .s.l.o.w.l.y. through SeaBIOS. It is so slow I can see its messages ("Starting SeaBIOS...") appearing letter by letter like an old TTY. Very retroish. :-P --- My ATI 3D Rage 2C card, besides making a few PCI BIOS calls, is also making a int 0x42 call that isn't supported. oprom: INT# 0x42 oprom: eax: 00000007 ebx: 00001004 ecx: 00000000 edx: 001203c2 oprom: ebp: 00110000 esp: 00000fda edi: 0000ffff esi: 00000000 oprom: ip: 3e3d cs: c000 flags: 00000006 Unsupported software interrupt #0x42 error! Ralf Brown's Interrupt List #61 lists it as: INT 42 - VIDEO - RELOCATED DEFAULT INT 10 VIDEO SERVICES (EGA,VGA) Desc: contains the address of the original INT 10 handler which an EGA+ video adapter replaces with its own on-board BIOS code So the above call should change video mode to 0x07, the mono text mode. This happens before loading a payload so this isn't SeaBIOS' responsibility, yet. Can we implement a stub to suppress this error? Cheers Keith

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remove some warning of sb600
by Jason Wang 23 Mar '10

23 Mar '10

Index: src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- src/southbridge/amd/rs690/rs690_early_setup.c (revision 5266) +++ src/southbridge/amd/rs690/rs690_early_setup.c (working copy) @@ -128,7 +128,7 @@ /* * Compliant with CIM_33's ATINB_PrepareInit */ -static void get_cpu_rev() +static void get_cpu_rev(void) { u32 eax, ebx, ecx, edx; __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) @@ -171,7 +171,7 @@ * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ -static void rs690_htinit() +static void rs690_htinit(void) { /* * About HT, it has been done in enumerate_ht_chain(). @@ -229,7 +229,7 @@ * Function2: DRAM and HT technology Trace mode configuration * Function3: Miscellaneous configuration *******************************************************/ -static void k8_optimization() +static void k8_optimization(void) { device_t k8_f0, k8_f2, k8_f3; msr_t msr; @@ -443,7 +443,7 @@ } /* enable CFG access to Dev8, which is the SB P2P Bridge */ -static void enable_rs690_dev8() +static void enable_rs690_dev8(void) { set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); } @@ -453,14 +453,14 @@ /* * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). */ -static void rs690_before_pci_init() +static void rs690_before_pci_init(void) { } /* * The calling sequence is same as CIM. */ -static void rs690_early_setup() +static void rs690_early_setup(void) { device_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs690_early_setup()\n"); Index: src/southbridge/amd/sb600/sb600_smbus.h =================================================================== --- src/southbridge/amd/sb600/sb600_smbus.h (revision 5267) +++ src/southbridge/amd/sb600/sb600_smbus.h (working copy) @@ -58,5 +58,7 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); #endif -- Wang Qing Pei MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> Phone:86+13426369984

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coreboot March 2010