coreboot March 2010

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434 discussions

440BX DRAM buffer strength patch status / My roadmap / Have fun
by Keith Hui 17 Mar '10

17 Mar '10

Is someone out there still having fun with my 440BX patch? It contains no arrays and won't crash romcc again - it still compiles fine after romcc went to hell and back. :-P I am happy to see RS780 support added too. I have one such board - ASUS M4A785TD-M EVO. But I'll need to build an SPI adapter for my Willem before I can start participating. After I add as much BX support as I can, it will be time to attack SIS 630 (aka port it from coreboot v1), but datasheet for that thing isn't the easiest to find. Also I want to see if I can do Intel 430HX - this supports Pentium/MMX/K6, and predates BX for a few years. I have datasheet, but this chipset hasn't been done before. Because I have a board of each chipset. I'm going on vacation for the next 3 days. In the meantime, have fun. Keith

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build service results for r5234
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5234 to the coreboot repository. This caused the following changes: Change Log: remove warnings from cs5530 driver. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5234&device=s1850&vendor=d… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[Patch] SSE & SSE2
by Myles Watson 17 Mar '10

17 Mar '10

This patch selects SSE & SSE2 in the socket if one exists (except for AMD since there are many sockets for two models). The reasoning is that sockets can support multiple models of CPUS for intel, and SSE & SSE2 settings need to be based on the least capable CPU. It's all correct as far as Google tells me. Socket PGA370 - SSE but not SSE2 (supports PIII) Slot 1 - SSE but not SSE2 Slot 2 - SSE but not SSE2 Via C3 - SSE but not SSE2 Via C7 - SSE and SSE2 Qemu - not SSE2 (I don't know about SSE, so I didn't set it) Geode - not SSE or SSE2 intel ep80579 SSE and SSE2 Socket 441 SSE and SSE2 Socket mPGA479M SSE and SSE2 Socket mPGA604 SSE and SSE2 Socket BGA956 MMX and SSE and SSE2 Socket mFCPGA478 MMX and SSE and SSE2 Socket mPGA478 MMX and SSE and SSE2 Socket mPGA603 MMX and SSE and SSE2 some intel model_f?x Kconfig files weren't being sourced in src/cpu/intel/Kconfig Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[commit] r5238 - trunk/src/northbridge/intel/i440bx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 03:15:07 2010 New Revision: 5238 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5238 Log: >From Keith Hui: This patch implements a full SDRAM buffer strength programming algorithm in set_dram_buffer_strength(), checked against my P2B-LS factory BIOS. With this in place, I now have 133MHz (!) stability with three 256MB PC133 modules, and can boot Fedora 11 all the way to the init daemon (actually upstart, but that's another story). Not to login prompt yet. We'll find out why later. This again assumes a 4-DIMM board because that's all I have. I need someone with a 3-DIMM board to test it. As a bonus, there's a big comment block within that illustrates the algorithm. :-) Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i440bx/raminit.c Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Wed Mar 17 03:09:12 2010 (r5237) +++ trunk/src/northbridge/intel/i440bx/raminit.c Wed Mar 17 03:15:07 2010 (r5238) @@ -431,15 +431,156 @@ static void set_dram_buffer_strength(void) { - /* TODO: This needs to be set according to the DRAM tech - * (x8, x16, or x32). Argh, Intel provides no docs on this! - * Currently, it needs to be pulled from the output of - * lspci -xxx Rx92 + /* To give some breathing room for romcc, + * mbsc0 doubles as drb + * mbsc1 doubles as drb1 + * mbfs0 doubles as i and reg + */ + uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb; + + /* Tally how many rows between rows 0-3 and rows 4-7 are populated. + * This determines how to program MBFS and MBSC. + */ + uint8_t dimm03 = 0; + uint8_t dimm47 = 0; + + mbsc0 = 0; + for (mbfs0 = DRB0; mbfs0 <= DRB7; mbfs0++) { + mbsc1 = pci_read_config8(NB, mbfs0); + if (mbsc0 != mbsc1) { + if (mbfs0 <= DRB3) { + dimm03++; + } else { + dimm47++; + } + mbsc0 = mbsc1; + } + } + + /* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0] + * + * 440BX datasheet says buffer frequency is independent from bus frequency + * and mismatch both ways are possible. This is how it is programmed + * in ASUS P2B-LS. + * + * There are four main conditions to check when programming DRAM buffer + * frequency and strength: + * + * a: >2 rows populated across DIMM0,1 + * b: >2 rows populated across DIMM2,3 + * c: >4 rows populated across all DIMM slots + * and either one of: + * 1: NBXCFG[13] strapped as 100MHz, or + * 6: NBXCFG[13] strapped as 66MHz + * + * CKE0/FENA ----------------------------------------------------------+ + * CKE1/GCKE -------------------[ MBFS ]------------------------+| + * DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+|| + * DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+||| + * DQMB5/CASB5# ---------------------------------------------------+|||| + * DQMA1/CASA1# --------------------------------------------------+||||| + * DQMA5/CASA5# -------------------------------------------------+|||||| + * CSA0-5#,CSB0-5# ----------------------------------------++++++||||||| + * CSA6#/CKE2# -------------------------------------------+||||||||||||| + * CSB6#/CKE4# ------------------------------------------+|||||||||||||| + * CSA7#/CKE3# -----------------------------------------+||||||||||||||| + * CSB7#/CKE5# ----------------------------------------+|||||||||||||||| + * MECC[7:0] #2/#1 (100MHz) -------------------------++||||||||||||||||| + * MD[63:0] #2/#1 (100MHz) ------------------------++||||||||||||||||||| + * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+||||||||||||||||||||| + * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+|||||||||||||||||||||| + * Reserved ------------------------------------+||||||||||||||||||||||| + * |||||||||||||||||||||||| + * 3 32 21 10 0 * 2 21 10 0 + * 9876543210987654321098765432109876543210 * 321098765432109876543210 + * a 10------------------------1010---------- * -1---------------11----- a + *!a 11------------------------1111---------- * -0---------------00----- !a + * b --10--------------------------1010------ * --1----------------11--- b + *!b --11--------------------------1111------ * --0----------------00--- !b + * c ----------------------------------1100-- * ----------------------1- c + *!c ----------------------------------1011-- * ----------------------0- !c + * 1 ----1010101000000000000000------------00 * ---11111111111111----1-0 1 + * 6 ----000000000000000000000010101010----00 * ---1111111111111100000-0 6 + * | | | | | | | | | | ||||||| | | | | | | + * | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA + * | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE + * | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]# + * | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# + * | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# + * | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# + * | | | | | | | | | | ||||||+------------- DQMA5/CASA5# + * | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0=1x;1=2x ] + * | | | | | | | | | +--------------------- CSA6#/CKE2# + * | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4# + * | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3# + * | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5# + * | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (2x) + * | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (2x) + * | | | +--------------------------------- MD[63:0] #1 (2x) + * | | +----------------------------------- MD[63:0] #2 (2x) + * | +------------------------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# + * +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA# + * MBSC[47:40] and MBFS[23] are reserved. * - * Relevant registers: MBSC, MBFS, BUFFC. + * This algorithm is checked against P2B-LS factory BIOS. It has 4 DIMM slots. + * Therefore it assumes a board with 4 slots, and will need testing + * on boards with 3 DIMM slots. */ + + mbsc0 = 0x80; + mbsc1 = 0x2a; + mbfs2 = 0x1f; + if (pci_read_config8(NB, NBXCFG + 1) & 0x30) { + fsb = 66; + mbsc3 = 0x00; + mbsc4 = 0x00; + mbfs0 = 0x80; + } else { + fsb = 100; + mbsc3 = 0xa0; + mbsc4 = 0x0a; + mbfs0 = 0x84; + } + + if (dimm03 > 2) { + mbsc4 = mbsc4 | 0x80; + mbsc1 = mbsc1 | 0x28; + mbfs2 = mbfs2 | 0x40; + mbfs0 = mbfs0 | 0x60; + } else { + mbsc4 = mbsc4 | 0xc0; + if (fsb == 100) { + mbsc1 = mbsc1 | 0x3c; + } + } + if (dimm47 > 2) { + mbsc4 = mbsc4 | 0x20; + mbsc1 = mbsc1 | 0x02; + mbsc0 = mbsc0 | 0x80; + mbfs2 = mbfs2 | 0x20; + mbfs0 = mbfs0 | 0x18; + } else { + mbsc4 = mbsc4 | 0x30; + if (fsb == 100) { + mbsc1 = mbsc1 | 0x03; + mbsc0 = mbsc0 | 0xc0; + } + } + if ((dimm03 + dimm47) > 4) { + mbsc0 = mbsc0 | 0x30; + mbfs0 = mbfs0 | 0x02; + } else { + mbsc0 = mbsc0 | 0x2c; + } - pci_write_config8(NB, MBSC, 0x03); + pci_write_config8(NB, MBSC + 0, mbsc0); + pci_write_config8(NB, MBSC + 1, mbsc1); + pci_write_config8(NB, MBSC + 2, 0x00); + pci_write_config8(NB, MBSC + 3, mbsc3); + pci_write_config8(NB, MBSC + 4, mbsc4); + pci_write_config8(NB, MBFS + 0, mbfs0); + pci_write_config8(NB, MBFS + 1, 0xff); + pci_write_config8(NB, MBFS + 2, mbfs2); } /*-----------------------------------------------------------------------------

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[commit] r5237 - in trunk/src: cpu/intel/model_f0x cpu/intel/model_f1x cpu/intel/model_f2x cpu/intel/model_f3x cpu/intel/model_f4x cpu/intel/socket_mPGA604 mainboard/dell/s1850 southbridge/intel/i8...
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 03:09:12 2010 New Revision: 5237 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5237 Log: fix dell s1850, ROMCC didn't seem to like SSE2 memtest here. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/model_f0x/Kconfig trunk/src/cpu/intel/model_f1x/Kconfig trunk/src/cpu/intel/model_f2x/Kconfig trunk/src/cpu/intel/model_f3x/Kconfig trunk/src/cpu/intel/model_f4x/Kconfig trunk/src/cpu/intel/socket_mPGA604/Kconfig trunk/src/mainboard/dell/s1850/Kconfig trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Modified: trunk/src/cpu/intel/model_f0x/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_f0x/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/model_f0x/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_F0X bool select SMP - select SSE2 Modified: trunk/src/cpu/intel/model_f1x/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_f1x/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/model_f1x/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_F1X bool select SMP - select SSE2 Modified: trunk/src/cpu/intel/model_f2x/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_f2x/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/model_f2x/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_F2X bool select SMP - select SSE2 Modified: trunk/src/cpu/intel/model_f3x/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_f3x/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/model_f3x/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_F3X bool select SMP - select SSE2 Modified: trunk/src/cpu/intel/model_f4x/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_f4x/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/model_f4x/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_F4X bool select SMP - select SSE2 Modified: trunk/src/cpu/intel/socket_mPGA604/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_mPGA604/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/cpu/intel/socket_mPGA604/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -6,3 +6,11 @@ select MMX select SSE select UDELAY_TSC + +# mPGA604 are usually Intel Netburst CPUs which should have SSE2 +# but the ramtest.c code on the Dell S1850 seems to choke on +# enabling it, so disable it for now. +config SSE2 + bool + default n + depends on CPU_INTEL_SOCKET_MPGA604 Modified: trunk/src/mainboard/dell/s1850/Kconfig ============================================================================== --- trunk/src/mainboard/dell/s1850/Kconfig Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/mainboard/dell/s1850/Kconfig Wed Mar 17 03:09:12 2010 (r5237) @@ -11,6 +11,7 @@ select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_1024 select UDELAY_TSC Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Wed Mar 17 02:51:11 2010 (r5236) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_watchdog.c Wed Mar 17 03:09:12 2010 (r5237) @@ -1,4 +1,5 @@ #include <console/console.h> +#include <watchdog.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h>

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build service results for r5233
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5233 to the coreboot repository. This caused the following changes: Change Log: make clean: delete failover.inc and romstage.inc, drop auto.inc (obsolete) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5233&device=s1850&vendor=d… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5236 - in trunk/src: arch/i386/include/arch cpu/x86/smm include/cpu/x86 mainboard/kontron/986lcd-m southbridge/intel/i82801dx southbridge/intel/i82801gx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 02:51:11 2010 New Revision: 5236 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5236 Log: fix a couple of warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/include/arch/romcc_io.h trunk/src/cpu/x86/smm/Makefile.inc trunk/src/cpu/x86/smm/smihandler.c trunk/src/cpu/x86/smm/smiutil.c trunk/src/include/cpu/x86/smm.h trunk/src/include/cpu/x86/tsc.h trunk/src/mainboard/kontron/986lcd-m/mainboard.c trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c Modified: trunk/src/arch/i386/include/arch/romcc_io.h ============================================================================== --- trunk/src/arch/i386/include/arch/romcc_io.h Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/arch/i386/include/arch/romcc_io.h Wed Mar 17 02:51:11 2010 (r5236) @@ -273,7 +273,7 @@ } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_io_locate_device(unsigned pci_id, device_t dev) +static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -285,7 +285,7 @@ return PCI_DEV_INVALID; } -static device_t pci_locate_device(unsigned pci_id, device_t dev) +static inline device_t pci_locate_device(unsigned pci_id, device_t dev) { for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -297,7 +297,7 @@ return PCI_DEV_INVALID; } -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { device_t dev, last; Modified: trunk/src/cpu/x86/smm/Makefile.inc ============================================================================== --- trunk/src/cpu/x86/smm/Makefile.inc Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/cpu/x86/smm/Makefile.inc Wed Mar 17 02:51:11 2010 (r5236) @@ -32,7 +32,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o - $(CONFIG_CROSS_COMPILE)nm -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map + $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm $(obj)/cpu/x86/smm/smm_bin.c: $(obj)/cpu/x86/smm/smm Modified: trunk/src/cpu/x86/smm/smihandler.c ============================================================================== --- trunk/src/cpu/x86/smm/smihandler.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/cpu/x86/smm/smihandler.c Wed Mar 17 02:51:11 2010 (r5236) @@ -25,8 +25,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -void southbridge_smi_set_eos(void); - typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ Modified: trunk/src/cpu/x86/smm/smiutil.c ============================================================================== --- trunk/src/cpu/x86/smm/smiutil.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/cpu/x86/smm/smiutil.c Wed Mar 17 02:51:11 2010 (r5236) @@ -102,7 +102,8 @@ uart_tx_byte(byte); } -void uart_init(void) +#if CONFIG_DEBUG_SMI +static void uart_init(void) { /* disable interrupts */ outb(0x0, CONFIG_TTYS0_BASE + UART_IER); @@ -114,6 +115,7 @@ outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); } +#endif void console_init(void) { Modified: trunk/src/include/cpu/x86/smm.h ============================================================================== --- trunk/src/include/cpu/x86/smm.h Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/include/cpu/x86/smm.h Wed Mar 17 02:51:11 2010 (r5236) @@ -250,10 +250,14 @@ /* SMI handler function prototypes */ +void smi_handler(u32 smm_revision); + void io_trap_handler(int smif); int southbridge_io_trap_handler(int smif); int mainboard_io_trap_handler(int smif); +void southbridge_smi_set_eos(void); + void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); Modified: trunk/src/include/cpu/x86/tsc.h ============================================================================== --- trunk/src/include/cpu/x86/tsc.h Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/include/cpu/x86/tsc.h Wed Mar 17 02:51:11 2010 (r5236) @@ -7,7 +7,7 @@ }; typedef struct tsc_struct tsc_t; -static tsc_t rdtsc(void) +static inline tsc_t rdtsc(void) { tsc_t res; __asm__ __volatile__ ( Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mainboard.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/mainboard/kontron/986lcd-m/mainboard.c Wed Mar 17 02:51:11 2010 (r5236) @@ -21,7 +21,9 @@ #include <device/device.h> #include <console/console.h> #include <boot/tables.h> +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> +#endif #include <pc80/mc146818rtc.h> #include <arch/io.h> #include <arch/coreboot_tables.h> Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/mainboard/kontron/986lcd-m/mainboard_smi.c Wed Mar 17 02:51:11 2010 (r5236) @@ -20,6 +20,7 @@ #include <arch/io.h> #include <arch/romcc_io.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h" /* The southbridge SMI handler checks whether gnvs has a Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smihandler.c Wed Mar 17 02:51:11 2010 (r5236) @@ -588,10 +588,10 @@ #undef IOTRAP } -typedef void (*smi_handler)(unsigned int node, +typedef void (*smi_handler_t)(unsigned int node, smm_state_save_area_t *state_save); -smi_handler southbridge_smi[32] = { +smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved NULL, // [1] reserved NULL, // [2] BIOS_STS Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c Wed Mar 17 02:50:15 2010 (r5235) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c Wed Mar 17 02:51:11 2010 (r5236) @@ -568,10 +568,10 @@ #undef IOTRAP } -typedef void (*smi_handler)(unsigned int node, +typedef void (*smi_handler_t)(unsigned int node, smm_state_save_area_t *state_save); -smi_handler southbridge_smi[32] = { +smi_handler_t southbridge_smi[32] = { NULL, // [0] reserved NULL, // [1] reserved NULL, // [2] BIOS_STS

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[commit] r5235 - trunk
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 02:50:15 2010 New Revision: 5235 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5235 Log: clean some more files in make clean Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Mar 17 02:22:01 2010 (r5234) +++ trunk/Makefile Wed Mar 17 02:50:15 2010 (r5235) @@ -320,6 +320,8 @@ rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm rm -f $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc + rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* + rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm rmdir -p $(alldirs) 2>/dev/null >/dev/null || true $(MAKE) -C util/sconfig clean

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build service results for r5232
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5232 to the coreboot repository. This caused the following changes: Change Log: drop unused variable Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5232&device=s1850&vendor=d… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5234 - trunk/src/southbridge/amd/cs5530
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 02:22:01 2010 New Revision: 5234 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5234 Log: remove warnings from cs5530 driver. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/cs5530/cs5530_vga.c Modified: trunk/src/southbridge/amd/cs5530/cs5530_vga.c ============================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530_vga.c Wed Mar 17 02:18:14 2010 (r5233) +++ trunk/src/southbridge/amd/cs5530/cs5530_vga.c Wed Mar 17 02:22:01 2010 (r5234) @@ -237,7 +237,7 @@ * * The PLL to program here is located in the CS5530 */ -static void cs5530_set_clock_frequency(void *io_base, unsigned long pll_val) +static void cs5530_set_clock_frequency(u32 io_base, unsigned long pll_val) { unsigned long reg; @@ -282,7 +282,7 @@ * - 2 (=2MiB) for XGA * - 4 (=4MiB) for SXGA */ -static void dc_setup_layout(void *gx_base, const struct video_mode *mode) +static void dc_setup_layout(u32 gx_base, const struct video_mode *mode) { u32 base = 0x00000000; @@ -323,7 +323,7 @@ * |#####################################___________________________| line data * |______________________________________________---------_________| YSYNC */ -static void dc_setup_timing(void *gx_base, const struct video_mode *mode) +static void dc_setup_timing(u32 gx_base, const struct video_mode *mode) { u32 hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; u32 vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; @@ -367,7 +367,7 @@ * Must be setup in Geode GX1's chipset. * Note: This routine assumes unlocked DC registers. */ -static void cs5530_activate_mode(void *gx_base, const struct video_mode *mode) +static void cs5530_activate_mode(u32 gx_base, const struct video_mode *mode) { write32(gx_base + DC_GENERAL_CFG, 0x00000080); mdelay(1); @@ -387,7 +387,7 @@ * As we now activate the interface this must be done * in the CS5530 */ -static void cs5530_activate_video(void *io_base, const struct video_mode *mode) +static void cs5530_activate_video(u32 io_base, const struct video_mode *mode) { u32 val; @@ -454,10 +454,10 @@ static void cs5530_vga_init(device_t dev) { const struct video_mode *mode; - void *io_base, *gx_base; + u32 io_base, gx_base; - io_base = (void*)pci_read_config32(dev, 0x10); - gx_base = (void*)GX_BASE; + io_base = pci_read_config32(dev, 0x10); + gx_base = GX_BASE; mode = modes[CONFIG_GX1_VIDEOMODE]; printk_debug("Setting up video mode %dx%d with %d Hz clock\n",

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coreboot March 2010