coreboot March 2010

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[commit] r5245 - trunk/src/southbridge/intel/i82801dx
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:40:23 2010 New Revision: 5245 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5245 Log: bug fix for IOAPIC on i82801dx. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:37:18 2010 (r5244) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:40:23 2010 (r5245) @@ -38,8 +38,8 @@ static void i82801dx_enable_ioapic(struct device *dev) { u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; - volatile u32 *ioapic_data = (volatile u32 *)IO_APIC_ADDR + 0x10; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));

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[commit] r5243 - in trunk/src: mainboard/rca/rm4100 mainboard/thomson/ip1000 northbridge/intel/i82830
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:18:29 2010 New Revision: 5243 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5243 Log: This is kind of a pre CAR patch to properly allocate "shared" graphics memory area. CONFIG_GFXUMA is used in src/cpu/x86/mtrr/mtrr.c which is called by the cpu. Attached is a revised patch which works well. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> See boot snips below: Root Device assign_resources, bus 0 link: 0 8MB IGD UMA Available memory: 581632KB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 ---------------------------- Adding high table area Adding UMA memory area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 0000000000100000-00000000237effff: RAM 3. 00000000237f0000-00000000237fffff: CONFIGURATION TABLES 4. 0000000023800000-0000000023ffffff: RESERVED Modified: trunk/src/mainboard/rca/rm4100/Kconfig trunk/src/mainboard/rca/rm4100/mainboard.c trunk/src/mainboard/thomson/ip1000/Kconfig trunk/src/mainboard/thomson/ip1000/mainboard.c trunk/src/northbridge/intel/i82830/northbridge.c trunk/src/northbridge/intel/i82830/raminit.c Modified: trunk/src/mainboard/rca/rm4100/Kconfig ============================================================================== --- trunk/src/mainboard/rca/rm4100/Kconfig Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/mainboard/rca/rm4100/Kconfig Wed Mar 17 04:18:29 2010 (r5243) @@ -8,9 +8,11 @@ select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC - select BOARD_ROMSIZE_KB_512 + select BOARD_ROMSIZE_KB_1024 + select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select HAVE_SMI_HANDLER + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/rca/rm4100/mainboard.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/mainboard.c Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/mainboard/rca/rm4100/mainboard.c Wed Mar 17 04:18:29 2010 (r5243) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> + * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +19,15 @@ */ #include <device/device.h> +#include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + static void mainboard_init(device_t dev) { // TODO Switch parport LEDs again Modified: trunk/src/mainboard/thomson/ip1000/Kconfig ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Kconfig Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/mainboard/thomson/ip1000/Kconfig Wed Mar 17 04:18:29 2010 (r5243) @@ -10,7 +10,9 @@ select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select HAVE_HARD_RESET + select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER + select GFXUMA config MAINBOARD_DIR string Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/mainboard.c Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/mainboard/thomson/ip1000/mainboard.c Wed Mar 17 04:18:29 2010 (r5243) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> + * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +19,15 @@ */ #include <device/device.h> +#include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" +int add_mainboard_resources(struct lb_memory *mem) +{ + return add_northbridge_resources(mem); +} + static void mainboard_init(device_t dev) { // TODO Switch parport LEDs again Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/northbridge/intel/i82830/northbridge.c Wed Mar 17 04:18:29 2010 (r5243) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> + * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,8 @@ #include <stdlib.h> #include <string.h> #include <bitops.h> +#include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" #include "i82830.h" @@ -88,6 +90,18 @@ return tolm; } +/* IGD memory */ +uint64_t uma_memory_base=0, uma_memory_size=0; + +int add_northbridge_resources(struct lb_memory *mem) +{ + printk_debug("Adding IGD UMA memory area\n"); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_base, uma_memory_size); + + return 0; +} + #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; @@ -106,8 +120,10 @@ if (CONFIG_VIDEO_MB == 512) { igd_memory = (CONFIG_VIDEO_MB); + printk_debug("%dKB IGD UMA\n", igd_memory >> 10); } else { igd_memory = (CONFIG_VIDEO_MB * 1024); + printk_debug("%dMB IGD UMA\n", igd_memory >> 10); } /* Get the value of the highest DRB. This tells the end of @@ -116,7 +132,11 @@ */ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15; tomk -= igd_memory; - printk_debug("Memory detected: %ldKB RAM\n", tomk); + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = igd_memory * 1024ULL; + printk_debug("Available memory: %ldKB\n", tomk); /* Compute the top of low memory. */ tolmk = pci_tolm >> 10; Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Wed Mar 17 04:14:54 2010 (r5242) +++ trunk/src/northbridge/intel/i82830/raminit.c Wed Mar 17 04:18:29 2010 (r5243) @@ -48,7 +48,7 @@ * 0x0 for Refresh Disabled (Self Refresh) * 0x1 for Refresh interval 15.6 us for 133MHz * 0x2 for Refresh interval 7.8 us for 133MHz - * 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode) + * 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode) */ #define RAM_COMMAND_REFRESH 0x1

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build service results for r5237
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5237 to the coreboot repository. This caused the following changes: Change Log: fix dell s1850, ROMCC didn't seem to like SSE2 memtest here. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 has been fixed Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5237&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5237&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5237&device=x6dhr_ig2&vend… Compilation of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5237&device=s2735&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5242 - in trunk/src: cpu/intel/socket_PGA370 include mainboard/digitallogic/adl855pc mainboard/rca/rm4100 mainboard/thomson/ip1000 northbridge/intel/i82830 southbridge/intel/i82801dx supe...
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:14:54 2010 New Revision: 5242 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5242 Log: more warning fixes. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig trunk/src/include/reset.h trunk/src/mainboard/digitallogic/adl855pc/Kconfig trunk/src/mainboard/rca/rm4100/Kconfig trunk/src/mainboard/thomson/ip1000/Kconfig trunk/src/mainboard/thomson/ip1000/mainboard_smi.c trunk/src/northbridge/intel/i82830/vga.c trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c trunk/src/superio/smsc/smscsuperio/superio.c Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/Kconfig Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/cpu/intel/socket_PGA370/Kconfig Wed Mar 17 04:14:54 2010 (r5242) @@ -22,3 +22,10 @@ bool select MMX select UDELAY_TSC + +# Not all CPUs for Socket 370 can do SSE2 +config SSE2 + bool + default n + depends on CPU_INTEL_SOCKET_PGA370 + Modified: trunk/src/include/reset.h ============================================================================== --- trunk/src/include/reset.h Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/include/reset.h Wed Mar 17 04:14:54 2010 (r5242) @@ -1,6 +1,9 @@ #ifndef RESET_H #define RESET_H +#if !defined( __ROMCC__ ) +/* ROMCC can't do function prototypes... */ + #if CONFIG_HAVE_HARD_RESET == 1 void hard_reset(void); #else @@ -9,3 +12,4 @@ void soft_reset(void); #endif +#endif Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/Kconfig Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig Wed Mar 17 04:14:54 2010 (r5242) @@ -7,6 +7,7 @@ select SUPERIO_WINBOND_W83627HF select ROMCC select HAVE_PIRQ_TABLE + select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR Modified: trunk/src/mainboard/rca/rm4100/Kconfig ============================================================================== --- trunk/src/mainboard/rca/rm4100/Kconfig Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/mainboard/rca/rm4100/Kconfig Wed Mar 17 04:14:54 2010 (r5242) @@ -9,6 +9,7 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_HARD_RESET select HAVE_SMI_HANDLER config MAINBOARD_DIR Modified: trunk/src/mainboard/thomson/ip1000/Kconfig ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Kconfig Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/mainboard/thomson/ip1000/Kconfig Wed Mar 17 04:14:54 2010 (r5242) @@ -9,6 +9,7 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 + select HAVE_HARD_RESET select HAVE_SMI_HANDLER config MAINBOARD_DIR Modified: trunk/src/mainboard/thomson/ip1000/mainboard_smi.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/mainboard_smi.c Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/mainboard/thomson/ip1000/mainboard_smi.c Wed Mar 17 04:14:54 2010 (r5242) @@ -22,6 +22,7 @@ #include <arch/io.h> #include <arch/romcc_io.h> #include <console/console.h> +#include <cpu/x86/smm.h> int mainboard_io_trap_handler(int smif) { Modified: trunk/src/northbridge/intel/i82830/vga.c ============================================================================== --- trunk/src/northbridge/intel/i82830/vga.c Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/northbridge/intel/i82830/vga.c Wed Mar 17 04:14:54 2010 (r5242) @@ -25,7 +25,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbfs.h> +#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> +#endif static void vga_init(device_t dev) { Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Wed Mar 17 04:14:54 2010 (r5242) @@ -36,6 +36,8 @@ extern void i82801dx_enable(device_t dev); #endif +#define DEBUG_PERIODIC_SMIS 0 + #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_reset.c Wed Mar 17 04:14:54 2010 (r5242) @@ -18,6 +18,7 @@ */ #include <arch/io.h> +#include <reset.h> void hard_reset(void) { Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_smi.c Wed Mar 17 04:14:54 2010 (r5242) @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <string.h> @@ -237,7 +238,7 @@ extern uint8_t smm_relocation_start, smm_relocation_end; -void smm_relocate(void) +static void smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -317,7 +318,7 @@ outb(0x00, 0xb2); } -void smm_install(void) +static void smm_install(void) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, Modified: trunk/src/superio/smsc/smscsuperio/superio.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/superio.c Wed Mar 17 04:14:28 2010 (r5241) +++ trunk/src/superio/smsc/smscsuperio/superio.c Wed Mar 17 04:14:54 2010 (r5242) @@ -345,7 +345,7 @@ /* Enable the specified devices (if present on the chip). */ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - &pnp_dev_info); + &pnp_dev_info[0]); /* Restore LD_FOO values. */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)

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[commit] r5241 - in trunk/src/southbridge/intel: i82801ax i82801bx i82801dx i82801ex
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 04:14:28 2010 New Revision: 5241 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5241 Log: fix HPET base addressed. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h trunk/src/southbridge/intel/i82801bx/i82801bx.h trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.h Wed Mar 17 04:10:39 2010 (r5240) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Wed Mar 17 04:14:28 2010 (r5241) @@ -115,6 +115,6 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) /* HPET, if present */ -#define HPET_ADDR 0xfed0000 +#define HPET_ADDR 0xfed00000 #endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */ Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx.h Wed Mar 17 04:10:39 2010 (r5240) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Wed Mar 17 04:14:28 2010 (r5241) @@ -115,7 +115,7 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) /* HPET, if present */ -#define HPET_ADDR 0xfed0000 +#define HPET_ADDR 0xfed00000 #endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */ Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:10:39 2010 (r5240) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 04:14:28 2010 (r5241) @@ -114,7 +114,7 @@ static void enable_hpet(struct device *dev) { - const unsigned long hpet_address = 0xfed0000; + const unsigned long hpet_address = 0xfed00000; u32 dword; u32 code = (0 & 0x3); @@ -130,7 +130,7 @@ dword &= ~(3 << 15); /* clear it */ dword |= (code << 15); - printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12)); + printk_debug("enabling HPET @0x%lx\n", hpet_address | (code << 12)); } static void lpc_init(struct device *dev) Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 04:10:39 2010 (r5240) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 04:14:28 2010 (r5241) @@ -214,7 +214,7 @@ static void enable_hpet(struct device *dev) { -const unsigned long hpet_address = 0xfed0000; + const unsigned long hpet_address = 0xfed00000; uint32_t dword; uint32_t code = (0 & 0x3);

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[commit] r5240 - in trunk/src/southbridge/amd: sb600 sb700
by repository service 17 Mar '10

17 Mar '10

Author: zbao Date: Wed Mar 17 04:10:39 2010 New Revision: 5240 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5240 Log: The SB600 also has the BootFailTimer. We should disable it, otherwise it will keeps reboot. The comment was also added in detail to make less confusing when we debug SB600/SB700. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Wed Mar 17 03:48:24 2010 (r5239) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Wed Mar 17 04:10:39 2010 (r5240) @@ -71,8 +71,16 @@ u32 reg32; device_t dev; - /* Enable lpc controller */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ + /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! + * This bit has no meaning if debug strap is not enabled. So if the + * board keeps rebooting and the code fails to reach here, we could + * disable the debug strap first. */ + reg32 = pci_read_config32(dev, 0x4C); + reg32 |= 1 << 31; + pci_write_config32(dev, 0x4C, reg32); + + /* Enable lpc controller */ reg32 = pci_read_config32(dev, 0x64); reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Mar 17 03:48:24 2010 (r5239) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Wed Mar 17 04:10:39 2010 (r5240) @@ -102,8 +102,11 @@ u32 reg32; device_t dev; - /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ + /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! + * This bit has no meaning if debug strap is not enabled. So if the + * board keeps rebooting and the code fails to reach here, we could + * disable the debug strap first. */ reg32 = pci_read_config32(dev, 0x4C); reg32 |= 1 << 31; pci_write_config32(dev, 0x4C, reg32);

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build service results for r5236
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5236 to the coreboot repository. This caused the following changes: Change Log: fix a couple of warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5236&device=s1850&vendor=d… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH]: Disable boot timer in SB600
by Bao, Zheng 17 Mar '10

17 Mar '10

The SB600 also has the BootFailTimer. We should disable it, otherwise it will keeps reboot. The comment was also added in detail to make less confusing when we debug SB600/SB700. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/sb600/sb600_early_setup.c =================================================================== --- src/southbridge/amd/sb600/sb600_early_setup.c (revision 5234) +++ src/southbridge/amd/sb600/sb600_early_setup.c (working copy) @@ -71,8 +71,16 @@ u32 reg32; device_t dev; + dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ + /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! + * This bit has no meaning if debug strap is not enabled. So if the + * board keeps rebooting and the code fails to reach here, we could + * disable the debug strap first. */ + reg32 = pci_read_config32(dev, 0x4C); + reg32 |= 1 << 31; + pci_write_config32(dev, 0x4C, reg32); + /* Enable lpc controller */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ reg32 = pci_read_config32(dev, 0x64); reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); Index: src/southbridge/amd/sb700/sb700_early_setup.c =================================================================== --- src/southbridge/amd/sb700/sb700_early_setup.c (revision 5234) +++ src/southbridge/amd/sb700/sb700_early_setup.c (working copy) @@ -102,8 +102,11 @@ u32 reg32; device_t dev; - /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! */ dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ + /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! + * This bit has no meaning if debug strap is not enabled. So if the + * board keeps rebooting and the code fails to reach here, we could + * disable the debug strap first. */ reg32 = pci_read_config32(dev, 0x4C); reg32 |= 1 << 31; pci_write_config32(dev, 0x4C, reg32);

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[commit] r5239 - in trunk/src: mainboard/dell/s1850 mainboard/supermicro/x6dhe_g2 mainboard/supermicro/x6dhr_ig mainboard/supermicro/x6dhr_ig2 mainboard/tyan/s2735 southbridge/intel/i82801ex southb...
by repository service 17 Mar '10

17 Mar '10

Author: stepan Date: Wed Mar 17 03:48:24 2010 New Revision: 5239 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5239 Log: remove more warnings, and fix some boards (watchdog.h) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/dell/s1850/mptable.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig trunk/src/mainboard/tyan/s2735/Kconfig trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Modified: trunk/src/mainboard/dell/s1850/mptable.c ============================================================================== --- trunk/src/mainboard/dell/s1850/mptable.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/dell/s1850/mptable.c Wed Mar 17 03:48:24 2010 (r5239) @@ -4,7 +4,7 @@ #include <string.h> #include <stdint.h> -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "DELL "; Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/dell/s1850/romstage.c Wed Mar 17 03:48:24 2010 (r5239) @@ -19,7 +19,8 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" -#include "reset.c" +// Remove comment if resets in this file are actually used. +// #include "reset.c" #include "s1850_fixups.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/supermicro/x6dhe_g2/Kconfig Wed Mar 17 03:48:24 2010 (r5239) @@ -12,6 +12,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 + select USE_WATCHDOG_ON_BOOT select DRIVERS_GENERIC_DEBUG config MAINBOARD_DIR Modified: trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig Wed Mar 17 03:48:24 2010 (r5239) @@ -11,6 +11,7 @@ select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig Wed Mar 17 03:48:24 2010 (r5239) @@ -11,6 +11,7 @@ select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR Modified: trunk/src/mainboard/tyan/s2735/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2735/Kconfig Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/mainboard/tyan/s2735/Kconfig Wed Mar 17 03:48:24 2010 (r5239) @@ -13,6 +13,7 @@ select UDELAY_TSC select HAVE_OPTION_TABLE select USE_DCACHE_RAM + select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Wed Mar 17 03:48:24 2010 (r5239) @@ -232,7 +232,7 @@ dword &= ~(3 << 15); /* clear it */ dword |= (code<<15); - printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) ); + printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) ); } static void lpc_init(struct device *dev) Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_pci.c Wed Mar 17 03:48:24 2010 (r5239) @@ -7,7 +7,6 @@ static void pci_init(struct device *dev) { - uint32_t dword; uint16_t word; /* Clear system errors */ @@ -17,6 +16,7 @@ #if 0 /* System error enable */ + uint32_t dword; dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* SERR# Enable */ dword |= (1<<6); /* Parity Error Response */ Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_sata.c Wed Mar 17 03:48:24 2010 (r5239) @@ -7,10 +7,7 @@ static void sata_init(struct device *dev) { - - uint16_t word; - - printk_debug("SATA init\n"); + printk_debug("SATA init\n"); /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.c Wed Mar 17 03:48:24 2010 (r5239) @@ -8,24 +8,28 @@ #include "i82801ex.h" #include "i82801ex_smbus.h" -static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { - unsigned device; + u16 device; struct resource *res; + struct bus *pbus; device = dev->path.i2c.device; - res = find_resource(bus->dev, 0x20); - + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_read_byte(res->base, device, address); } static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; + static struct pci_operations lops_pci = { /* The subsystem id follows the ide controller */ .set_subsystem = 0, }; + static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_smbus.h Wed Mar 17 03:48:24 2010 (r5239) @@ -46,7 +46,7 @@ return loops?0:-1; } -static int smbus_wait_until_blk_done(unsigned smbus_io_base) +static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; Modified: trunk/src/southbridge/intel/pxhd/pxhd_bridge.c ============================================================================== --- trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Wed Mar 17 03:15:07 2010 (r5238) +++ trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Wed Mar 17 03:48:24 2010 (r5239) @@ -64,15 +64,15 @@ } static void pcix_init(device_t dev) { - uint32_t dword; - uint16_t word; - uint8_t byte; - int nmi_option; - /* Bridge control ISA enable */ pci_write_config8(dev, 0x3e, 0x07); +#warning "Please review lots of dead code here." #if 0 + int nmi_option; + uint32_t dword; + uint16_t word; + uint8_t byte; /* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04);

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build service results for r5235
by coreboot information 17 Mar '10

17 Mar '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5235 to the coreboot repository. This caused the following changes: Change Log: clean some more files in make clean Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5235&device=s1850&vendor=d… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot March 2010