coreboot October 2010

coreboot@coreboot.org

55 participants
316 discussions

[PATCH]First attempt at eliminating #include *.c
by Patrick Georgi 04 Oct '10

04 Oct '10

Hi, attached patch removes several "#include *.c" from romstage.c in i945 based boards and moves those files to romstage-srcs instead (ie. separate compilation units). There's one global change, the removal of ramtest.c from CAR romstage.cs It's abuild tested and boot tested on kontron/986lcd-m. Probably should be tested (so that ramtest.c stuff is a separate patch), but the global changes were actually the last change I made. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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Trac reminder: list of new ticket(s)
by coreboot tracker 04 Oct '10

04 Oct '10

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MSI 890GXM-G65
by Mattias Mattsson 03 Oct '10

03 Oct '10

Hi, I'm thinking of trying to port coreboot to MSI 890GXM-G65 (MS-7642): http://www.msi.com/index.php?func=proddesc&prod_no=2012 I do not own it (yet), so I only now the specs from the manual: North Bridge: AMD 890GX chipset South Bridge: AMD SB850 chipset Integrated ATI RadeonTM HD4290 GPU CPU Socket: AM3 Super I/O: Fintek F71889ED ( http://www.motherboards.org/imageview.html?i=/images/reviews/motherboards/2… ) flashrom is supported according to this user report: http://www.flashrom.org/pipermail/flashrom/2010-August/004393.html Does it seems like a good target? (Does coreboot have support for this chipset, if not is documentation available?) Thanks, -mattias

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[PATCH] Add CPP logic to VIA CAR init code.
by Warren Turkal 03 Oct '10

03 Oct '10

VIA/AMD experts, This patch get's the via/vt8454c back to building. However, I am not sure if the code that is being #ifdef'ed out will actually ever be used on a via platform. The code comes straight from the amd CAR implementation. A couple of questions are raised by this: 1) Should we just delete the code from the via file instead of this patch? 2) Should the amd and via CAR code be integrated into one file? Maybe just portions of the files if not the whole files? Also, another happy side effect of this change is that all the c7 boards seem to build with tiny bootblocks. Would everyone be ok with my making that change? Thanks, wt 8<---------------------------------------------------------------------- The execute-in-place (XIP) config options need to be set in order to get XIP functionality, so it needs to be excluded when those settings are not set. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/via/car/cache_as_ram.inc | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index be00fe3..d18ac3a 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -85,6 +85,8 @@ clear_fixed_var_mtrr_out: movl $(~(CacheSize - 1) | 0x800), %eax wrmsr +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) + #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else @@ -106,6 +108,8 @@ clear_fixed_var_mtrr_out: movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr +#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ + /* Set the default memory type and enable fixed and variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ movl $MTRRdefType_MSR, %ecx -- 1.7.1

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mtrr: your BIOS has set up an incorrect mask
by Andreas B. Mundt 03 Oct '10

03 Oct '10

Hi, today, after quite some time running coreboot on my machine (GA-M57SLI-S4), I updated coreboot to the latest revision, 5908. Now, my system complains about "mtrr: your BIOS has set up an incorrect mask, fixing it up." and I get a kernel oops. (See attached dmesg). I looked in my old syslogs, and there I already find "mtrr: type mismatch for e0000000,10000000 old: write-back new: write-combining", but no kernel oops. I have only very limited time to follow up on this, but if there's an easy fix, it would be great. Regards, Andi

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an AMD based platform
by ali hagigat 03 Oct '10

03 Oct '10

I want to ask the experts about an AMD based motherboard to research on Coreboot, what you recommend will be valuable or please tell me what motherboard in the list of supported motherboards of Wiki-Coreboot is more modern and close to the following attributes: I am looking for a motherboard with CPU and chip set similar to Intel. For CPU, I want it to have IA-32 and IA-32e architecture, I mean 32 bit machine with 64 bit extension to support 32 and also 64 bits applications, with Vtx (virtual machine capability), muti-core, and SIMD instructions with front side bus. About Chipset, I want it to have regular logics of USB, SATA, PCIExpress, SDRAM controller, FWH/SPI protocol for BIOS chip, PCI bridge, IOAPIC, Integrated Graphics Controller, real time clock, LPC interface,....a relatively modern board and superio with open documentation. Thank you to read my message.

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Re: [coreboot] BBC EFI story
by ali hagigat 02 Oct '10

02 Oct '10

On Sat, Oct 2, 2010 at 12:04 PM, Stefan Reinauer <stefan.reinauer(a)coresystems.de> wrote: > On 10/2/10 9:49 AM, ali hagigat wrote: >>ordered 4 motherboards, over >> 11000$. > You made a very bad deal on those mainboards if that's USD. If I > remember correctly the list price should rather be 1/10th of that for 4 > mainboards. I have ordered them by Kontron, it is a company in Germany. They do not sell motherboards, they sell a complete case of a computer and the price was nearly 2600$(KISS 2U, KISS 4U). >> gives this information to big BIOS companies ONLY. > Not so true, other people made it, too. I even explained to you how to > do it. Stefan, you are working for a big company and you wrote for me that we could get that privileged license for documentation hardly after one year!! >> At least you could update Wiki pages to state this fact clearly to >> stop people waste money. > I doubt we can keep the world from making bad decisions and seeking the fault in others by just putting a few words in a wiki. > Many may make this mistake because nobody can study Intel documents in details to know that there is unexplained parts in the manual before even getting a board. Now I have made it clear, before i do not think even one person mentioned the issue. >Have you even tried to understand > the public documentation? We have over 50 contributors, so it seems > others have made it, because they tried. Why don't you? My plan was to gather a thorough knowledge of one example of Coreboot. I dislike much to deal with a subject which in incomplete. from Corey Osgood <corey.osgood(a)gmail.com> to ali hagigat <hagigatali(a)gmail.com> cc coreboot(a)coreboot.org date Sat, Oct 2, 2010 at 12:30 PM subject Re: [coreboot] BBC EFI story >Most people don't insist on understanding every single line of chipset >code to port a motherboard. If your chipset is supported, it should be >relatively easy to port a board to it. I do not want to port Coreboot first. My immediate purpose was to study and become proficient in the subject. How I can port Coreboot without even knowing it and researching on it first. >I understand that this can be frustrating, but it's something that the >coreboot project has no control over. >NDA stands for Non-Disclosure Agreement, which means that At least you could add some lines about NDA story and incomplete data sheets in Wiki or you could made the following fact clear : "Anybody who wants to study and learn Coreboot must know that the documentation of hardware is incomplete and there are some hidden cases which will never become clear!!" >Don't blame coreboot for your own misunderstanding. Just because a >project is open source doesn't mean every bit of data on how the code >was written has public documentation. The linux kernel (and I imagine >BSD, solaris, etc) is also open source, but some of the hardware >supported within doesn't have public datasheets, or the datasheets >that are public are incomplete. Linux Kernel contains variety of software structures, techniques and logic except the architecture, Coreboot is about BIOS and it deals with hardware directly and mostly, having a complete hardware documentation is necessary and compulsory for Coreboot while Linux Kernel have many logical sections apart from architecture and they are used and learned independently. They are in two different categories in my opinion.

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Fwd: [nylug-talk] Trac questions
by Gregg Levine 02 Oct '10

02 Oct '10

Hello! Folks, this is from a member of the LUG here in NYC. He addresses the methods that are confusing me, to prevent those spurious tickets from surfacing. Naturally it is forwarded below my comments. Ron that's the group that I was interested in having yourself, or one of the members of the list present a good speech and even a demo or two on coreboot to. (Incidentally, he normally doesn't even want to give me the time of day. Every time I bring up something on the older hardware here, he acts like something resembling people I can't properly describe without using four letter language, and I'm not doing it on this this. I do have here a P4 based system a Dell Optiplex GX170L, and raised some excellent questions for it, to properly get Slackware 13.1 running properly. I received some excellent help and even better advice from several people. And he didn't over react.) ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again." ---------- Forwarded message ---------- From: Ajai Khattri <ajai(a)bitblit.net> Date: Sat, Oct 2, 2010 at 11:51 PM Subject: Re: [nylug-talk] Trac questions To: NYLUG Technical Discussion <nylug-talk(a)nylug.org> On Sat, 2 Oct 2010, Gregg Levine wrote: > I remember participating in a LUG meeting with that as its theme but I > do not recall what it was written with. Or perhaps a related beastie, > but both apply. You probably will need to remove anonymous write access to tickets, the wiki, etc. Very easy if you have the web admin plugin installed. Otherwise it will fequire running tracadmin from the command-line. -- A

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#163: Board still requires RAMBASE <1MB
by coreboot 02 Oct '10

02 Oct '10

#163: Board still requires RAMBASE <1MB -------------------------+-------------------------------------------------- Reporter: oxygene | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Some boards have RAMBASE at 0x4000. For some, it's probably a left-over from old times, but others actually require it. Update the former, and fix the latter. Wyse/s50 requires 0x4000, see http://www.coreboot.org/pipermail/coreboot/2010-May/058080.html (and the log file therein) -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/163> coreboot <http://www.coreboot.org/>

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Trac spam
by Gregg Levine 02 Oct '10

02 Oct '10

Hello! This is getting monotonous. It seems every time a trac entry is updated, it aquires some blockhead's random example of junk. In this case its #163. Now I realize that everyone does know about them, but I am simply bringing it up so that we can get the matter resolved. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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coreboot October 2010