coreboot October 2010

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[PATCH] correct setting of non-posted option in RS780 function ProgK8TempMmioBase
by Scott Duplichan 07 Oct '10

07 Oct '10

RS780 function ProgK8TempMmioBase is setting a reserved bit in the AMD processor 'MMIO Limit Address Register'. I suspect it is because of a typo where 0x80 was entered as 0x8. If 0x80 is used, then the strap configuration register accesses become non-posted, which is how the Shiner reference BIOS does it. Thanks, Scott Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/southbridge/amd/rs780/rs780_cmn.c =================================================================== --- src/southbridge/amd/rs780/rs780_cmn.c (revision 5917) +++ src/southbridge/amd/rs780/rs780_cmn.c (working copy) @@ -204,7 +204,7 @@ if (in_out) { pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8); + 1) >> 8) & 0xffffff00) | 0x80); //non-posted pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, ((mmio_base_add + 0x10000000 -

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[commit] r5919 - in trunk/src/southbridge/amd: rs690 rs780
by repository service 07 Oct '10

07 Oct '10

Author: ruik Date: Thu Oct 7 20:25:04 2010 New Revision: 5919 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5919 Log: RS780 function ProgK8TempMmioBase is setting a reserved bit in the AMD processor 'MMIO Limit Address Register'. I suspect it is because of a typo where 0x80 was entered as 0x8. If 0x80 is used, then the strap configuration register accesses become non-posted, which is how the Shiner reference BIOS does it. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c trunk/src/southbridge/amd/rs780/rs780_cmn.c Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs690/rs690_cmn.c Thu Oct 7 18:24:28 2010 (r5918) +++ trunk/src/southbridge/amd/rs690/rs690_cmn.c Thu Oct 7 20:25:04 2010 (r5919) @@ -206,7 +206,7 @@ if (in_out) { pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8); + 1) >> 8) & 0xffffff00) | 0x80); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, ((mmio_base_add + 0x10000000 - Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_cmn.c Thu Oct 7 18:24:28 2010 (r5918) +++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Thu Oct 7 20:25:04 2010 (r5919) @@ -204,7 +204,7 @@ if (in_out) { pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8); + 1) >> 8) & 0xffffff00) | 0x80); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, ((mmio_base_add + 0x10000000 -

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[PATCH] Geode GX2 auto DRAM detect patch
by Nils 07 Oct '10

07 Oct '10

This patch brings the adapted Geode LX auto DRAM detect code to GX2 , cleans up some files and adds a processor speed setting function in human readable Mhz. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> It is Abuild and boot tested on my Wyse S50 with 3 different SODIMMs (128Mb pc2700, 256Mb pc2100, 512Mb pc2700) and each dimm with all three speed settings. (my S50 runs linux under as well as overclocked at 400Mhz!) Thanks to Jens Rottmann for providing the memory chip types for the Lippert Frontrunner. Thanks, Nils.

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[PATCH] Convert Intel 82371AB/EB/MB boards to TINY_BOOTBLOCK
by Uwe Hermann 07 Oct '10

07 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r5918 - in trunk/src: mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-ds mainboard/asus/p2b-f ma...
by repository service 07 Oct '10

07 Oct '10

Author: uwe Date: Thu Oct 7 18:24:28 2010 New Revision: 5918 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5918 Log: Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK. Also: Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device on various PCI bus:device.function locations. Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. Thus, instead of hardcoding PCI bus:device.function numbers such as PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which works the same on all boards. As an additional benefit this patch also gets rid of one .c file include in romstage.c. Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/southbridge/intel/i82371eb/bootblock.c Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/southbridge/intel/i82371eb/Kconfig trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -27,7 +27,6 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -27,7 +27,6 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -55,9 +54,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p2b/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "southbridge/intel/i82371eb/i82371eb_early_pm.c" #include "northbridge/intel/i440bx/raminit.h" @@ -88,9 +87,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ - enable_smbus(); enable_pm(); Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -54,9 +53,6 @@ report_bist_failure(bist); enable_smbus(); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -56,9 +55,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -54,9 +53,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -55,9 +54,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/msi/ms6119/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/msi/ms6147/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/msi/ms6156/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/nokia/ip530/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -54,9 +53,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/mainboard/tyan/s1846/romstage.c Thu Oct 7 18:24:28 2010 (r5918) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -53,9 +52,6 @@ console_init(); report_bist_failure(bist); - /* Enable access to the full ROM chip, needed very early by CBFS. */ - i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - enable_smbus(); dump_spd_registers(); sdram_set_registers(); Modified: trunk/src/southbridge/intel/i82371eb/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82371eb/Kconfig Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/southbridge/intel/i82371eb/Kconfig Thu Oct 7 18:24:28 2010 (r5918) @@ -1,4 +1,10 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select IOAPIC + select TINY_BOOTBLOCK + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82371eb/bootblock.c" + depends on SOUTHBRIDGE_INTEL_I82371EB Added: trunk/src/southbridge/intel/i82371eb/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82371eb/bootblock.c Thu Oct 7 18:24:28 2010 (r5918) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + i82371eb_enable_rom(); +} Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c Wed Oct 6 21:32:39 2010 (r5917) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c Thu Oct 7 18:24:28 2010 (r5918) @@ -19,11 +19,25 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> #include "i82371eb.h" -static void i82371eb_enable_rom(device_t dev) +static void i82371eb_enable_rom(void) { u16 reg16; + device_t dev; + + /* + * Note: The Intel 82371AB/EB/MB ISA device can be on different + * PCI bus:device.function locations on different boards. + * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. + * But scanning for the PCI IDs (instead of hardcoding + * bus/device/function numbers) works on all boards. + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); /* Enable access to the whole ROM, disable ROM write access. */ reg16 = pci_read_config16(dev, XBCS);

1 0

[PATCH try 3] Reduce duplicate definition in CAR code.
by Warren Turkal 07 Oct '10

07 Oct '10

I added names for the AMD registers and separated each .long onto it's own line to avoid any bugs of the type the caldani mentioned. Comments? Acks? :) Thanks, wt 8<------------------- Macros for the register addresses for the MTRR MSRs are already defined in include/cpu/x86/car.h. This patch uses those macros instead of creating a second instance of that same data. I also combined common MTRR definitions into a macro. I also added a few macros to the amd mtrr.h to make the MSR naming more consistent. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/car/cache_as_ram.inc | 24 ++++----------------- src/cpu/intel/car/cache_as_ram.inc | 17 +++------------ src/cpu/via/car/cache_as_ram.inc | 17 +++------------ src/include/cpu/amd/mtrr.h | 27 +++++++++++++++++++----- src/include/cpu/x86/mtrr.h | 39 ++++++++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 51 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5318272..a8c6972 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -396,23 +396,9 @@ CAR_FAM10_ap_out: post_code(0xaf) /* Should never see this POST code. */ -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - -var_iorr_msr: - .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 - -mem_top: - .long 0xC001001A, 0xC001001D - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +AMD_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM cache_as_ram_setup_out: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index d8465f4..84e2f2f 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -115,7 +115,7 @@ NotHtProcessor: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -128,18 +128,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM clear_fixed_var_mtrr_out: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index d6df4a9..80f8c13 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -47,7 +47,7 @@ CacheAsRam: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -60,18 +60,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(0), %ecx diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index c7b3fca..57a41a4 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -21,16 +21,31 @@ #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define IORR1_BASE 0xC0010018 -#define IORR1_MASK 0xC0010019 -#define TOP_MEM 0xC001001A -#define TOP_MEM2 0xC001001D +#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) +#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) + +#define TOP_MEM_MSR 0xC001001A +#define TOP_MEM2_MSR 0xC001001D +#define TOP_MEM TOP_MEM_MSR +#define TOP_MEM2 TOP_MEM2_MSR #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) +#if defined(ASSEMBLY) +.macro AMD_MTRR_MSRS_TABLE_ENTRIES_ASM + /* Variable IORR MTRR MSRs */ + .long IORRBase_MSR(0) + .long IORRMask_MSR(0) + .long IORRBase_MSR(1) + .long IORRMask_MSR(1) + + /* Top of memory MTRR MSRs */ + .long TOP_MEM_MSR + .long TOP_MEM2_MSR +.endm /* AMD_MTRR_MSRS_TABLE_ENTRIES_ASM */ +#endif /* defined(ASSEMBLY) */ + #if !defined(__PRE_RAM__) && !defined(ASSEMBLY) void amd_setup_mtrrs(void); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index e79c90e..dcb9c9a 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -34,6 +34,45 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f +#if defined (ASSEMBLY) +.macro X86_MTRR_MSRS_TABLE_ENTRIES_ASM + /* fixed mtrr MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var mtrr MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) +.endm /* X86_MTRR_MSRS_TABLE_ENTRIES_ASM */ + +.macro END_MTRR_MSRS_TABLE_ENTRY_ASM + .long 0x000 /* NULL, end of table */ +.endm /* END_MTRR_MSRS_TABLE_ASM */ +#endif /* defined (ASSEMBLY) */ + #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); -- 1.7.1

1 1

PCI register read/mod/write code
by Peter Stuge 07 Oct '10

07 Oct '10

Rudolf just found a bug in the sb700 code: u32 dword; .. dword = pci_read_config8(dev, 0x64); dword |= 1 << 10; pci_write_config8(dev, 0x64, dword); And I'm ranting now, because a pci_set8() macro/function could have found this bug at compile time, and because I don't like these constructs. (Compiler warnings would also have indicated a problem. They're currently disabled for this code.) Carl-Daniel is working on a patch, meanwhile consider this: #define pci_set8(dev, reg, val) do { \ if ((a) & ~0xff) can_only_set_low_8_bits(); \ pci_set8_nocheck((dev), (reg), (val)); \ } while(0) u8 pci_set8_nocheck(device_t dev, u32 reg, u8 val) { u8 tmp = pci_read_config8(dev, reg); tmp |= val; pci_write_config8(dev, reg, tmp); return tmp; } $ gcc -g -o a a.c /tmp/cchpQWSr.o: In function `main': /tmp/a.c:11: undefined reference to `can_only_set_low_8_bits' collect2: ld returned 1 exit status Now, this is ugly, and warnings is the only right way, but I still very much think that one pci_set8() or pci_clear8() call is way better than code to read+mod+write. The reason is that it's how I think about these operations; "set bits xy in reg foo." Read+mod+write is one lower level of abstraction, and not relevant in the context of setting the bits. Ie. I don't want to write/see *how* bits get set, I just want to write/see *that* bits get set. I completely understand that everyone else may not have the same mental model of these operations, but I hope many enough do.. (Yes, we've discussed before and it seemed not to be the case.) Carl-Daniel mentioned that there may be a risk for confusion between pci_set8() and pci_write_config8(), and this was also noted before. Isn't it really reasonable to expect that people can actually keep track of how those two functions are different? I understand that my taste is more terse than most, and if consensus is that _set8 _clear8 etc. names suck, then I'd be happy with other fun names too, as long as read+mod+write blocks can be replaced with single lines of code. Like the CAR thing I think this really helps write- and readability, and even thinkability, for our code. The latter helps make further abstraction easier, which allows more refactoring. Bad goal? //Peter

8 15

[PATCH try 2] Reduce duplicate definition in CAR code.
by Warren Turkal 07 Oct '10

07 Oct '10

Here's another cut at this patch that is more comprehensive. I have included all major vendor car implementations. What do you all think about this approach? Thanks, wt 8<------------ Macros for the register addresses for the MTRR MSRs are already defined in include/cpu/x86/car.h. This patch uses those macros instead of creating a second instance of that same data. I also combined common MTRR definitions into a macro. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/car/cache_as_ram.inc | 24 +++++------------------- src/cpu/intel/car/cache_as_ram.inc | 17 ++++------------- src/cpu/via/car/cache_as_ram.inc | 17 ++++------------- src/include/cpu/amd/mtrr.h | 9 +++++++++ src/include/cpu/x86/mtrr.h | 31 +++++++++++++++++++++++++++++++ 5 files changed, 53 insertions(+), 45 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5318272..a8c6972 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -396,23 +396,9 @@ CAR_FAM10_ap_out: post_code(0xaf) /* Should never see this POST code. */ -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - -var_iorr_msr: - .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 - -mem_top: - .long 0xC001001A, 0xC001001D - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +AMD_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM cache_as_ram_setup_out: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index d8465f4..84e2f2f 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -115,7 +115,7 @@ NotHtProcessor: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -128,18 +128,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM clear_fixed_var_mtrr_out: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index d6df4a9..80f8c13 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -47,7 +47,7 @@ CacheAsRam: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -60,18 +60,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES_ASM +END_MTRR_MSRS_TABLE_ENTRY_ASM clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(0), %ecx diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index c7b3fca..1649632 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -31,6 +31,15 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) +#if defined(ASSEMBLY) +.macro AMD_MTRR_MSRS_TABLE_ENTRIES_ASM + /* Variable IORR MTRR MSRs */ + .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 + /* Top of memory MTRR MSRs */ + .long 0xC001001A, 0xC001001D +.endm /* AMD_MTRR_MSRS_TABLE_ENTRIES_ASM */ +#endif /* defined(ASSEMBLY) */ + #if !defined(__PRE_RAM__) && !defined(ASSEMBLY) void amd_setup_mtrrs(void); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index e79c90e..ba3ab08 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -34,6 +34,37 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f +#if defined (ASSEMBLY) +.macro X86_MTRR_MSRS_TABLE_ENTRIES_ASM + /* fixed mtrr MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var mtrr MSRs */ + .long MTRRphysBase_MSR(0), MTRRphysBase_MSR(1) + .long MTRRphysBase_MSR(2), MTRRphysBase_MSR(3) + .long MTRRphysBase_MSR(4), MTRRphysBase_MSR(5) + .long MTRRphysBase_MSR(6), MTRRphysBase_MSR(7) + .long MTRRphysBase_MSR(8), MTRRphysBase_MSR(9) + .long MTRRphysBase_MSR(10), MTRRphysBase_MSR(11) + .long MTRRphysBase_MSR(12), MTRRphysBase_MSR(13) + .long MTRRphysBase_MSR(14), MTRRphysBase_MSR(15) +.endm /* X86_MTRR_MSRS_TABLE_ENTRIES_ASM */ + +.macro END_MTRR_MSRS_TABLE_ENTRY_ASM + .long 0x000 /* NULL, end of table */ +.endm /* END_MTRR_MSRS_TABLE_ASM */ +#endif /* defined (ASSEMBLY) */ + #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); -- 1.7.1

7 17

Re: [coreboot] RE : RE : RE : [PATCH] Re: RE : RE : First coreboot build for Tyan s2895 K8WE mobo with seabios payload, computer starts, but graphical ubuntu 64bits is crashing
by Myles Watson 07 Oct '10

07 Oct '10

On Wed, Oct 6, 2010 at 10:24 AM, STEMMELIN, FREDERIC (FREDERIC)** CTR ** <frederic.stemmelin(a)alcatel-lucent.com> wrote: > Hello, > > i have just tried, and it fails. Good to know. Thanks. > I created a new folder, downloaded latest coreboot and seabios version (no patching at all). > Build both seabios and coreboot. > > 1) test without network card > OK, but acpi is not working properly as i need to press manually the power button to shutdown the computer > Remark: i forgot to mention this point last time, it was the same last time, so acpi problem is not related to your last change, it was there before. Yes. That's a known problem. > 2) test with network card plugged in PCI-X > computer is hanging after a few seconds, but starts ... Does it matter which PCI-X slot it's plugged into? Probably not. >From src/mainboard/tyan/s2895/dsdt.asl: /* There is no _PRT Here because I don't know what to * put in it. Since the 8131 has its own APIC, it * isn't wired to other IRQs. */ I don't know what it's supposed to look like, and I don't have any PCI-X hardware. This would be a good place to start if you'd like to investigate. You could compare it to the DSDT that came with your factory BIOS. Thanks, Myles

2 1

[commit] r5917 - in trunk/src: cpu/intel/slot_1 mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-ds mainbo...
by repository service 06 Oct '10

06 Oct '10

Author: uwe Date: Wed Oct 6 21:32:39 2010 New Revision: 5917 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5917 Log: Convert all Intel 440BX boards to Cache-as-RAM (CAR). - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/cpu/intel/slot_1/Kconfig trunk/src/cpu/intel/slot_1/Makefile.inc trunk/src/mainboard/a-trend/atc-6220/Kconfig trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/Kconfig trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/Kconfig trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/Kconfig trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/Kconfig trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/Kconfig trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/azza/pt-6ibd/Kconfig trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/biostar/m6tba/Kconfig trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c trunk/src/mainboard/msi/ms6119/Kconfig trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/Kconfig trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/Kconfig trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/tyan/s1846/Kconfig trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/northbridge/intel/i440bx/debug.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Modified: trunk/src/cpu/intel/slot_1/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_1/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/cpu/intel/slot_1/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -19,6 +19,7 @@ config CPU_INTEL_SLOT_1 bool + select CACHE_AS_RAM config DCACHE_RAM_BASE hex Modified: trunk/src/cpu/intel/slot_1/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/slot_1/Makefile.inc Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/cpu/intel/slot_1/Makefile.inc Wed Oct 6 21:32:39 2010 (r5917) @@ -27,3 +27,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc + Modified: trunk/src/mainboard/a-trend/atc-6220/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6220/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/a-trend/atc-6240/Kconfig ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6240/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/abit/be6-ii_v2_0/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: It's a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: It's a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -27,16 +27,15 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -48,12 +47,9 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) { - early_mtrr_init(); - enable_lapic(); /* FIXME? */ - } + enable_lapic(); /* FIXME? */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -27,16 +27,15 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -48,12 +47,9 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) { - early_mtrr_init(); - enable_lapic(); /* FIXME? */ - } + enable_lapic(); /* FIXME? */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p2b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-f/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-f/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p2b-ls/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ls/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -48,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -63,10 +59,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p2b/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p2b/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/asus/p3b-f/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p3b-f/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p3b-f/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "southbridge/intel/i82371eb/i82371eb_early_pm.c" @@ -34,10 +33,10 @@ #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -81,11 +80,8 @@ outb(0x67, PM_IO_BASE + 0x37); } -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -100,12 +96,10 @@ enable_spd(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ disable_spd(); } - Modified: trunk/src/mainboard/azza/pt-6ibd/Kconfig ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/azza/pt-6ibd/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: It's a Winbond W83977EF, actually. */ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> /* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: It's a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/biostar/m6tba/Kconfig ============================================================================== --- trunk/src/mainboard/biostar/m6tba/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/biostar/m6tba/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ /* Enable access to the full ROM chip, needed very early by CBFS. */ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ select SOUTHBRIDGE_INTEL_I82371EB # should be SUPERIO_NSC_PC97307! select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,17 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include "superio/nsc/pc97317/pc97317_early_serial.c" +#include <lib.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1) @@ -49,11 +48,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - /* FIXME: Should be PC97307! */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -64,10 +60,8 @@ i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxc/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) @@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +58,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxe/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -26,7 +26,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +static void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) @@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_48mhz_clkin(); it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -62,9 +59,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/msi/ms6119/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6119/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6119/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6119/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/msi/ms6147/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6147/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6147/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6147/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/x86/bist.h> #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -45,13 +44,10 @@ } #include "northbridge/intel/i440bx/raminit.c" -/* #include "northbridge/intel/i440bx/debug.c" */ +#include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,17 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); -#if 0 - ram_check(0, 640 * 1024); /* DOS-area */ - ram_check(0x00100000, 0x00400000); /* 1MB to 4MB */ - ram_check(0x00100000, 0x03ffffff); /* 1MB to 64MB- */ - ram_check(0x03fff000, 0x04000010); /* Across 64MB boundary */ - ram_check(0x07ffff00, 0x07fffff0); /* Just below 128MB */ - ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */ -#endif } - Modified: trunk/src/mainboard/msi/ms6156/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms6156/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6156/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/msi/ms6156/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/nokia/ip530/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,9 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_ITE_IT8671F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,16 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +void it8671f_48mhz_clkin(void); #include "superio/ite/it8671f/it8671f_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1) @@ -47,11 +47,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +58,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/mainboard/tyan/s1846/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s1846/Kconfig Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/tyan/s1846/Kconfig Wed Oct 6 21:32:39 2010 (r5917) @@ -25,7 +25,6 @@ select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 - select ROMCC select UDELAY_TSC select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/mainboard/tyan/s1846/romstage.c Wed Oct 6 21:32:39 2010 (r5917) @@ -26,16 +26,15 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87309/pc87309_early_serial.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) @@ -47,11 +46,8 @@ #include "northbridge/intel/i440bx/raminit.c" #include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,10 +57,8 @@ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); - /* ram_check(0, 640 * 1024); */ } - Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/northbridge/intel/i440bx/debug.c Wed Oct 6 21:32:39 2010 (r5917) @@ -1,6 +1,6 @@ - static void dump_spd_registers(void) { +#if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { @@ -32,6 +32,7 @@ print_debug("\n"); } } +#endif } #if 0 Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Tue Oct 5 21:39:35 2010 (r5916) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Wed Oct 6 21:32:39 2010 (r5917) @@ -63,95 +63,6 @@ return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } -static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) -{ - unsigned global_status_register; - unsigned byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(0, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHST_DAT) & 0xff; - - // Check for any result other than a command completion - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return byte; -} - -static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned value) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHST_CMD); - /* set up for a send byte */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x1), smbus_io_base + SMBHST_CTL); - - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* set the data word...*/ - outw(value, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { - return SMBUS_ERROR; - } - return 0; -} - - static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { unsigned status_register; @@ -199,41 +110,3 @@ return byte; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) -{ - unsigned global_status_register; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - } - - /* setup transaction */ - /* disable interrupts */ - outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); - /* set the device I'm talking too */ - outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHST_ADDR); - outb(address & 0xFF, smbus_io_base + SMBHST_CMD); - /* set up for a byte data write */ /* FIXME */ - outw((inw(smbus_io_base + SMBHST_CTL) & ~7) | (0x2), smbus_io_base + SMBHST_CTL); - /* clear any lingering errors, so the transaction will run */ - /* Do I need to write the bits to a 1 to clear an error? */ - outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); - - /* write the data word...*/ - outw(val, smbus_io_base + SMBHST_DAT); - - /* start the command */ - outw((inw(smbus_io_base + SMBHST_CTL) | (1 << 3)), smbus_io_base + SMBHST_CTL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - global_status_register = inw(smbus_io_base + SMBHST_STATUS); - - if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 1)) { - return SMBUS_ERROR; - } - return 0; -} -

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coreboot October 2010