coreboot October 2010

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[PATCH]De-define CK804 flags
by Patrick Georgi 05 Oct '10

05 Oct '10

Hi, attached patch moves a couple more config flags out of romstage: CK804_USE_NIC, CK804_USE_ACI. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

3 4

[commit] r5912 - in trunk/src: mainboard/asus/a8n_e mainboard/gigabyte/m57sli mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv main...
by repository service 05 Oct '10

05 Oct '10

Author: myles Date: Tue Oct 5 19:59:12 2010 New Revision: 5912 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5912 Log: attached patch moves a couple more config flags out of romstage: CK804_USE_NIC, CK804_USE_ACI, CK804_NUM. MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Pter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/msi/ms7135/Kconfig trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/Kconfig trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -42,10 +42,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -/* Used by ck894_early_setup(). */ -#define CK804_NUM 1 - #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -8,6 +8,8 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_ITE_IT8716F select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL select HAVE_BUS_CONFIG Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -90,10 +90,6 @@ return smbus_read_byte(device, address); } -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 0 #define MCP55_MB_SETUP \ Modified: trunk/src/mainboard/msi/ms7135/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7135/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms7135/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -15,6 +15,8 @@ select HAVE_MP_TABLE select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -43,10 +43,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -/* Used by ck804_early_setup(). */ -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms7260/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -8,6 +8,8 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -92,9 +92,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 #define MCP55_PCI_E_X_0 0 #define MCP55_MB_SETUP \ Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms9282/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -105,7 +105,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" //set GPIO to input mode #define MCP55_MB_SETUP \ Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -8,6 +8,8 @@ select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -89,10 +89,6 @@ #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -9,6 +9,8 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG @@ -44,6 +46,10 @@ int default 1 +config MCP55_NUM + int + default 2 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -100,10 +100,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 2 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 2 #define MCP55_PCI_E_X_1 4 Modified: trunk/src/mainboard/sunw/ultra40/Kconfig ============================================================================== --- trunk/src/mainboard/sunw/ultra40/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/sunw/ultra40/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -14,6 +14,8 @@ select HAVE_MP_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -78,9 +78,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -9,6 +9,8 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -155,10 +155,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -9,6 +9,8 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -100,10 +100,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -8,6 +8,8 @@ select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -89,10 +89,6 @@ #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -92,10 +92,6 @@ #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 0 -#define MCP55_USE_AZA 0 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -62,12 +62,9 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -72,9 +72,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2912/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -9,6 +9,7 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -100,9 +100,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -8,6 +8,7 @@ select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 19:59:12 2010 (r5912) @@ -89,9 +89,6 @@ #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -16,3 +16,14 @@ hex default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 +config CK804_USE_NIC + bool + default n if SOUTHBRIDGE_NVIDIA_CK804 + +config CK804_USE_ACI + bool + default n if SOUTHBRIDGE_NVIDIA_CK804 + +config CK804_NUM + int + default 1 if SOUTHBRIDGE_NVIDIA_CK804 Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Tue Oct 5 19:59:12 2010 (r5912) @@ -52,7 +52,7 @@ #define CK804_PCI_E_X 4 #endif -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE + 0x8000) #ifndef CK804B_BUSN @@ -63,14 +63,6 @@ #endif #endif -#ifndef CK804_USE_NIC -#define CK804_USE_NIC 0 -#endif - -#ifndef CK804_USE_ACI -#define CK804_USE_ACI 0 -#endif - #define CK804_CHIP_REV 3 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE @@ -89,12 +81,12 @@ { static const unsigned int ctrl_devport_conf[] = { PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, #endif PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, #endif }; @@ -106,11 +98,11 @@ { static const unsigned int ctrl_devport_conf_clear[] = { PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #endif PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, #endif }; @@ -126,7 +118,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, @@ -141,7 +133,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, @@ -155,7 +147,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, #endif @@ -164,7 +156,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, @@ -173,7 +165,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, @@ -190,7 +182,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff) | (0xff << 16)), (0x41 << 16) | (0x32), RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff << 16), (0xa0 << 16), -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, @@ -200,7 +192,7 @@ #endif RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #endif @@ -226,7 +218,7 @@ RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, @@ -240,25 +232,25 @@ #endif RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), #endif RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, #endif RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), #endif RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -266,17 +258,17 @@ RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CK804_USE_ACI == 1 +#if CONFIG_CK804_USE_ACI RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0, ~(3 << 2), (0 << 2), #endif -#if CK804_NUM > 1 -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_NUM > 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -296,7 +288,7 @@ setup_ss_table(ANACTRL_IO_BASE + 0xb0, ANACTRL_IO_BASE + 0xb4, ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); setup_ss_table(ANACTRL_IO_BASE + 0xc0, ANACTRL_IO_BASE + 0xc4, ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); -#if CK804_NUM > 1 +#if CONFIG_CK804_NUM > 1 setup_ss_table(CK804B_ANACTRL_IO_BASE + 0x40, CK804B_ANACTRL_IO_BASE + 0x44, CK804B_ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xb0, CK804B_ANACTRL_IO_BASE + 0xb4, CK804B_ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Oct 5 19:59:12 2010 (r5912) @@ -55,14 +55,6 @@ #define CK804B_PCI_E_X 4 #endif -#ifndef CK804_USE_NIC -#define CK804_USE_NIC 0 -#endif - -#ifndef CK804_USE_ACI -#define CK804_USE_ACI 0 -#endif - #define CK804_CHIP_REV 3 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE @@ -198,7 +190,7 @@ //SYSCTRL RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -206,7 +198,7 @@ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CK804_USE_ACI == 1 +#if CONFIG_CK804_USE_ACI RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif @@ -271,7 +263,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 19:59:12 2010 (r5912) @@ -1,7 +1,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool - select IOAPIC select HAVE_USBDEBUG + select IOAPIC config ID_SECTION_OFFSET hex @@ -15,3 +15,14 @@ hex default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 +config MCP55_USE_NIC + bool + default n if SOUTHBRIDGE_NVIDIA_MCP55 + +config MCP55_USE_AZA + bool + default n if SOUTHBRIDGE_NVIDIA_MCP55 + +config MCP55_NUM + int + default 1 if SOUTHBRIDGE_NVIDIA_MCP55 Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Oct 5 15:40:31 2010 (r5911) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Oct 5 19:59:12 2010 (r5912) @@ -89,14 +89,6 @@ #define MCP55_PCI_E_X_3 4 #endif -#ifndef MCP55_USE_NIC - #define MCP55_USE_NIC 0 -#endif - -#ifndef MCP55_USE_AZA - #define MCP55_USE_AZA 0 -#endif - #define MCP55_CHIP_REV 3 static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) @@ -269,7 +261,7 @@ RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, -#if MCP55_USE_AZA == 1 +#if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14, @@ -279,7 +271,7 @@ MCP55_MB_SETUP #endif -#if MCP55_USE_AZA == 1 +#if CONFIG_MCP55_USE_AZA RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2), @@ -308,7 +300,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, -#if MCP55_USE_NIC == 1 +#if CONFIG_MCP55_USE_NIC RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), @@ -399,7 +391,7 @@ devn[mcp55_num] = devnx; io_base[mcp55_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than MCP55 mcp55_num++; - if(mcp55_num == MCP55_NUM) goto out; + if(mcp55_num == CONFIG_MCP55_NUM) goto out; break; // only one MCP55 on one chain } }

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[PATCH]Move USB debug port includes out of romstage
by Patrick Georgi 05 Oct '10

05 Oct '10

Hi, attached patch does: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead - Disable USBDEBUG in abuild, I forgot this by accident before the previous commit It's abuild tested. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

4 4

build service results for r5911
by repository service 05 Oct '10

05 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5911 to the coreboot repository. This caused the following changes: Change Log: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:dbm690t has been fixed Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:pistachio has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:m4a785-m has been fixed Compilation of getac:p470 has been fixed Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of gigabyte:m57sli has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of ibase:mb899 has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of intel:d945gclf has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of kontron:kt690 has been fixed Compilation of msi:ms7135 has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9282 has been fixed Compilation of msi:ms9652_fam10 has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of roda:rk886ex has been fixed Compilation of sunw:ultra40 has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s2912 has been fixed Compilation of tyan:s2912_fam10 has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5911 - in trunk/src: include mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh main...
by repository service 05 Oct '10

05 Oct '10

Author: oxygene Date: Tue Oct 5 15:40:31 2010 New Revision: 5911 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5911 Log: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/include/ehci.h trunk/src/include/usbdebug.h trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/pc80/usbdebug_serial.c trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb600/Makefile.inc trunk/src/southbridge/amd/sb600/sb600.h trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c trunk/src/southbridge/amd/sb700/Kconfig trunk/src/southbridge/amd/sb700/Makefile.inc trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c trunk/src/southbridge/intel/i82801gx/Kconfig trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/Makefile.inc trunk/src/southbridge/nvidia/ck804/ck804.h trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/nvidia/mcp55/Makefile.inc trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c trunk/src/southbridge/sis/sis966/Kconfig trunk/src/southbridge/sis/sis966/Makefile.inc trunk/src/southbridge/sis/sis966/sis966.h trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Modified: trunk/src/include/ehci.h ============================================================================== --- trunk/src/include/ehci.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/include/ehci.h Tue Oct 5 15:40:31 2010 (r5911) @@ -23,6 +23,8 @@ #ifndef EHCI_H #define EHCI_H +#define EHCI_BAR_INDEX 0x10 + /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ Modified: trunk/src/include/usbdebug.h ============================================================================== --- trunk/src/include/usbdebug.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/include/usbdebug.h Tue Oct 5 15:40:31 2010 (r5911) @@ -41,6 +41,7 @@ void set_ehci_debug(unsigned ehci_deug); unsigned get_ehci_debug(void); void set_debug_port(unsigned port); +void early_usbdebug_init(void); void usbdebug_ram_tx_byte(unsigned char data); void usbdebug_tx_byte(unsigned char data); Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,10 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/mahogany/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -50,11 +50,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/pistachio/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -45,11 +45,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -27,6 +27,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <usbdebug.h> #include <pc80/mc146818rtc.h> Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,13 +51,11 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/sis/sis966/sis966_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> +#include "southbridge/sis/sis966/sis966.h" #include "southbridge/sis/sis966/sis966_early_smbus.c" #include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,10 +49,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -55,11 +55,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -59,11 +59,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h> #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -62,11 +62,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "superio/fintek/f71859/f71859_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c" Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -66,10 +66,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb700/sb700_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -27,6 +27,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <usbdebug.h> #include "superio/winbond/w83627thg/w83627thg.h" Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/kontron/kt690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -53,10 +53,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -52,10 +52,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -42,10 +42,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,10 +49,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -33,6 +33,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <usbdebug.h> #include <cpu/x86/bist.h> #include "northbridge/intel/i945/i945.h" Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -51,11 +51,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -#if CONFIG_USBDEBUG -#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -49,11 +49,8 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif #include <lib.h> +#include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 15:40:31 2010 (r5911) @@ -42,10 +42,7 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#if CONFIG_USBDEBUG -#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" -#include "pc80/usbdebug_serial.c" -#endif +#include <usbdebug.h> #include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/pc80/usbdebug_serial.c ============================================================================== --- trunk/src/pc80/usbdebug_serial.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/pc80/usbdebug_serial.c Tue Oct 5 15:40:31 2010 (r5911) @@ -19,13 +19,15 @@ */ #include "../lib/usbdebug.c" +#include <arch/io.h> +#include <ehci.h> -static void early_usbdebug_init(void) +void early_usbdebug_init(void) { struct ehci_debug_info *dbg_info = (struct ehci_debug_info *) (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); - usbdebug_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); + usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } void usbdebug_tx_byte(unsigned char data) Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -22,3 +22,11 @@ select IOAPIC select HAVE_USBDEBUG +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB600 + Modified: trunk/src/southbridge/amd/sb600/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb600/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -8,3 +8,4 @@ driver-y += sb600_ac97.c driver-y += sb600_pci.c ramstage-y += sb600_reset.c +romstage-y += sb600_enable_usbdebug.c Modified: trunk/src/southbridge/amd/sb600/sb600.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/sb600.h Tue Oct 5 15:40:31 2010 (r5911) @@ -40,4 +40,5 @@ void sb600_lpc_port80(void); void sb600_pci_port80(void); +void sb600_enable_usbdebug(unsigned int port); #endif /* SB600_H */ Modified: trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb600/sb600_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -18,12 +18,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ +#include "sb600.h" /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,7 +30,7 @@ /* TODO: Allow changing the physical USB port used as Debug Port. */ } -static void sb600_enable_usbdebug(unsigned int port) +void sb600_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ @@ -39,7 +38,7 @@ set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); Modified: trunk/src/southbridge/amd/sb700/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb700/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -27,3 +27,11 @@ default n depends on SOUTHBRIDGE_AMD_SB700 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_AMD_SB700 + +config EHCI_DEBUG_OFFSET + hex + default 0xe0 if SOUTHBRIDGE_AMD_SB700 + Modified: trunk/src/southbridge/amd/sb700/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb700/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -7,3 +7,4 @@ driver-y += sb700_hda.c driver-y += sb700_pci.c ramstage-y += sb700_reset.c +romstage-y += sb700_enable_usbdebug.c Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/sb700.h Tue Oct 5 15:40:31 2010 (r5911) @@ -59,4 +59,5 @@ #endif +void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */ Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -19,14 +19,13 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sb700.h" -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ -#define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ - -#define EHCI_EOR (EHCI_BAR + 0x20) +#define EHCI_EOR (CONFIG_EHCI_BAR + 0x20) #define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) void set_debug_port(unsigned int port) @@ -46,12 +45,12 @@ * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ -static void sb700_enable_usbdebug(unsigned int port) +void sb700_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -24,3 +24,11 @@ select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX + Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 5 15:40:31 2010 (r5911) @@ -39,10 +39,13 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 +#if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); #endif +void i82801gx_enable_usbdebug(unsigned int port); +#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -18,12 +18,12 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> - -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */ -#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */ +#include "i82801gx.h" /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) @@ -31,20 +31,20 @@ /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } -static void i82801gx_enable_usbdebug(unsigned int port) +void i82801gx_enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); - dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); + dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); - write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -8,3 +8,11 @@ hex default 0x80 if SOUTHBRIDGE_NVIDIA_CK804 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 + Modified: trunk/src/southbridge/nvidia/ck804/Makefile.inc ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -15,5 +15,8 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c +romstage-y += ck804_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds + Modified: trunk/src/southbridge/nvidia/ck804/ck804.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/ck804.h Tue Oct 5 15:40:31 2010 (r5911) @@ -4,5 +4,6 @@ #include "chip.h" void ck804_enable(device_t dev); +void ck804_enable_usbdebug(unsigned int port); #endif Modified: trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -22,8 +22,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "ck804.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); } -static void ck804_enable_usbdebug(unsigned int port) +void ck804_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -6,3 +6,12 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 + Modified: trunk/src/southbridge/nvidia/mcp55/Makefile.inc ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -15,5 +15,7 @@ ramstage-y += mcp55_reset.c +romstage-y += mcp55_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Tue Oct 5 15:40:31 2010 (r5911) @@ -29,4 +29,5 @@ #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif +void mcp55_enable_usbdebug(unsigned int port); #endif /* MCP55_H */ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -22,8 +22,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "mcp55.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned int port) +void mcp55_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); Modified: trunk/src/southbridge/sis/sis966/Kconfig ============================================================================== --- trunk/src/southbridge/sis/sis966/Kconfig Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/Kconfig Tue Oct 5 15:40:31 2010 (r5911) @@ -6,3 +6,11 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_SIS_SIS966 Modified: trunk/src/southbridge/sis/sis966/Makefile.inc ============================================================================== --- trunk/src/southbridge/sis/sis966/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/Makefile.inc Tue Oct 5 15:40:31 2010 (r5911) @@ -9,6 +9,7 @@ driver-y += sis966_pcie.c driver-y += sis966_aza.c ramstage-y += sis966_reset.c +romstage-y += sis966_enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds Modified: trunk/src/southbridge/sis/sis966/sis966.h ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966.h Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/sis966.h Tue Oct 5 15:40:31 2010 (r5911) @@ -32,5 +32,6 @@ #include "chip.h" void sis966_enable(device_t dev); +void sis966_enable_usbdebug(unsigned int port); #endif /* SIS966_H */ Modified: trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Tue Oct 5 11:07:10 2010 (r5910) +++ trunk/src/southbridge/sis/sis966/sis966_enable_usbdebug.c Tue Oct 5 15:40:31 2010 (r5911) @@ -24,8 +24,11 @@ /* TODO: Check whether this actually works (might be copy-paste leftover). */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "sis966.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -33,10 +36,6 @@ #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -49,7 +48,7 @@ pci_write_config32(dev, 0x74, dword); } -static void sis966_enable_usbdebug(unsigned int port) +void sis966_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -57,7 +56,7 @@ set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);

1 0

[PATCH] Factor out common CAR asm snippets
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. abuilt-tested. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

9 21

build service results for r5910
by repository service 05 Oct '10

05 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5910 to the coreboot repository. This caused the following changes: Change Log: Remove lib/ramtest.c-include from all CAR boards. Remove many more .c-includes from i945 based boards. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=dbm690t&vendor… Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mahogany&vendo… Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mahogany_fam10… Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=pistachio&vend… Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tilapia_fam10&… Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=939a785gmh&ven… Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=a8n_e&vendor=a… Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=m4a785-m&vendo… Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=p470&vendor=ge… Compilation of gigabyte:ga_2761gxdk has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ga_2761gxdk&ve… Compilation of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=m57sli&vendor=… Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ma785gmt&vendo… Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ma78gm&vendor=… Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=mb899&vendor=i… Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=kino-780am2-fa… Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=d945gclf&vendo… Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=pa78vm5&vendor… Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=986lcd-m&vendo… Compilation of kontron:kt690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=kt690&vendor=k… Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms7135&vendor=… Compilation of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms7260&vendor=… Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms9282&vendor=… Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ms9652_fam10&v… Compilation of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=l1_2pvv&vendor… Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=rk886ex&vendor… Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=ultra40&vendor… Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dme&vendor=s… Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dmr&vendor=s… Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=h8qme_fam10&ve… Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tim5690&vendor… Compilation of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=tim8690&vendor… Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2891&vendor=t… Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2892&vendor=t… Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2895&vendor=t… Compilation of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2912&vendor=t… Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5910&device=s2912_fam10&ve… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5910 - in trunk: src/lib src/mainboard/amd/db800 src/mainboard/amd/mahogany_fam10 src/mainboard/amd/norwich src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard...
by repository service 05 Oct '10

05 Oct '10

Author: oxygene Date: Tue Oct 5 11:07:10 2010 New Revision: 5910 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5910 Log: Remove lib/ramtest.c-include from all CAR boards. Remove many more .c-includes from i945 based boards. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/lib/Makefile.inc trunk/src/lib/ramtest.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/d810e2cb/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/intel/i945/Makefile.inc trunk/src/northbridge/intel/i945/debug.c trunk/src/northbridge/intel/i945/early_init.c trunk/src/northbridge/intel/i945/errata.c trunk/src/northbridge/intel/i945/i945.h trunk/src/northbridge/intel/i945/raminit.c trunk/src/northbridge/intel/i945/raminit.h trunk/src/northbridge/intel/i945/udelay.c trunk/src/pc80/Makefile.inc trunk/src/southbridge/intel/i82801gx/Makefile.inc trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h trunk/util/abuild/abuild Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/lib/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -21,6 +21,7 @@ romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c Modified: trunk/src/lib/ramtest.c ============================================================================== --- trunk/src/lib/ramtest.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/lib/ramtest.c Tue Oct 5 11:07:10 2010 (r5910) @@ -1,4 +1,6 @@ +#include <stdint.h> #include <lib.h> /* Prototypes */ +#include <console/console.h> static void write_phys(unsigned long addr, u32 value) { Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/db800/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/norwich/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/rumba/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,11 +45,11 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/arima/hdama/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -7,7 +7,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -48,7 +48,6 @@ #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,11 +27,11 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" +#include <lib.h> #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/broadcom/blast/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,6 @@ #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -6,7 +6,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,24 +26,20 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { u32 gpios; @@ -87,18 +83,6 @@ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -55,7 +55,6 @@ #include "southbridge/sis/sis966/sis966_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,6 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -41,10 +41,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -55,7 +55,6 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,11 +49,11 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h> #include "superio/winbond/w83627ehg/w83627ehg.h" @@ -34,21 +35,17 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -64,18 +61,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibm/e325/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibm/e326/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -48,10 +48,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/d810e2cb/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801bx/i82801bx.h" #include "southbridge/intel/i82801bx/i82801bx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" @@ -36,6 +35,7 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include <lib.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h> #include "superio/smsc/lpc47m15x/lpc47m15x.h" @@ -34,21 +35,17 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c" -#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ printk(BIOS_DEBUG, " GPIOS..."); @@ -65,18 +62,6 @@ outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -34,7 +34,6 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "reset.c" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit.h" Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "resourcemap.c" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c" /* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c" Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,13 +27,13 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" +#include <lib.h> #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,10 +46,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -21,6 +21,7 @@ #include <stdint.h> #include <string.h> +#include <lib.h> #include <arch/io.h> #include <arch/romcc_io.h> #include <device/pci_def.h> @@ -35,21 +36,17 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c" -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -65,18 +62,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lanner/em8510/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -30,7 +30,6 @@ #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -29,7 +29,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -29,7 +29,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,7 +49,6 @@ #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -56,12 +56,12 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <lib.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/newisys/khepri/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/rca/rm4100/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,24 +28,20 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h" -#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void); -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -61,18 +57,6 @@ outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ } -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -16,7 +16,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,7 +49,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -43,7 +43,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -43,7 +43,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,7 @@ #include <arch/llshell.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c" Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/traverse/geos/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2735/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2850/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2875/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2880/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2881/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2882/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2885/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -15,7 +15,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_10xxx_rev.h> Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s4880/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s4882/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/epia-cn/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/epia-m700/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -33,7 +33,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/pc2500e/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/vt8454c/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/winent/pl6064/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/wyse/s50/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> Modified: trunk/src/northbridge/intel/i945/Makefile.inc ============================================================================== --- trunk/src/northbridge/intel/i945/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -20,3 +20,9 @@ driver-y += northbridge.c driver-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +romstage-y += udelay.c +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += errata.c +romstage-y += debug.c Modified: trunk/src/northbridge/intel/i945/debug.c ============================================================================== --- trunk/src/northbridge/intel/i945/debug.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/debug.c Tue Oct 5 11:07:10 2010 (r5910) @@ -19,11 +19,18 @@ * MA 02110-1301 USA */ +#include <lib.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "i945.h" + #define SMBUS_MEM_DEVICE_START 0x50 #define SMBUS_MEM_DEVICE_END 0x53 #define SMBUS_MEM_DEVICE_INC 1 -static inline void print_pci_devices(void) +void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -42,7 +49,7 @@ } } -static inline void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned dev) { int i; @@ -61,7 +68,7 @@ } } -static inline void dump_pci_devices(void) +void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -78,7 +85,7 @@ } } -static inline void dump_spd_registers(void) +void dump_spd_registers(void) { unsigned device; device = SMBUS_MEM_DEVICE_START; @@ -103,7 +110,7 @@ } } -static inline void dump_mem(unsigned start, unsigned end) +void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:"); Modified: trunk/src/northbridge/intel/i945/early_init.c ============================================================================== --- trunk/src/northbridge/intel/i945/early_init.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/early_init.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,10 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> #include "i945.h" #include "pcie_config.c" -static int i945_silicon_revision(void) +int i945_silicon_revision(void) { return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); } @@ -856,7 +862,7 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); } -static void i945_early_initialization(void) +void i945_early_initialization(void) { /* Print some chipset specific information */ switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { @@ -879,7 +885,7 @@ RCBA32(0x2010) |= (1 << 10); } -static void i945_late_initialization(void) +void i945_late_initialization(void) { i945_setup_egress_port(); Modified: trunk/src/northbridge/intel/i945/errata.c ============================================================================== --- trunk/src/northbridge/intel/i945/errata.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/errata.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include "i945.h" #include "raminit.h" int fixup_i945_errata(void) Modified: trunk/src/northbridge/intel/i945/i945.h ============================================================================== --- trunk/src/northbridge/intel/i945/i945.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/i945.h Tue Oct 5 11:07:10 2010 (r5910) @@ -333,5 +333,22 @@ static inline void barrier(void) { asm("" ::: "memory"); } +int i945_silicon_revision(void); +void i945_early_initialization(void); +void i945_late_initialization(void); + +/* provided by southbridge code */ +int smbus_read_byte(unsigned device, unsigned address); + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); + #endif #endif Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/raminit.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,10 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <pc80/mc146818rtc.h> #include <spd.h> +#include <string.h> +#include <arch/romcc_io.h> #include "raminit.h" #include "i945.h" @@ -45,6 +48,11 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + static __attribute__((noinline)) void do_ram_command(u32 command) { u32 reg32; Modified: trunk/src/northbridge/intel/i945/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/raminit.h Tue Oct 5 11:07:10 2010 (r5910) @@ -71,4 +71,6 @@ void sdram_initialize(int boot_path); unsigned long get_top_of_ram(void); int fixup_i945_errata(void); +void udelay(u32 us); + #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/intel/i945/udelay.c ============================================================================== --- trunk/src/northbridge/intel/i945/udelay.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/udelay.c Tue Oct 5 11:07:10 2010 (r5910) @@ -18,6 +18,7 @@ */ #include <delay.h> +#include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/pc80/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -6,6 +6,7 @@ romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c romstage-$(CONFIG_CACHE_AS_RAM) += serial.c +romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c subdirs-y += vga $(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H) Modified: trunk/src/southbridge/intel/i82801gx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -35,3 +35,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c + +romstage-y += i82801gx_early_smbus.c +romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c + Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Tue Oct 5 11:07:10 2010 (r5910) @@ -18,11 +18,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801gx.h" #include "i82801gx_smbus.h" -static void enable_smbus(void) +int smbus_read_byte(unsigned device, unsigned address); + +void enable_smbus(void) { device_t dev; @@ -52,7 +58,7 @@ print_debug("SMBus controller enabled.\n"); } -static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h Tue Oct 5 11:07:10 2010 (r5910) @@ -20,6 +20,8 @@ #include <device/smbus_def.h> +void enable_smbus(void); + static void smbus_delay(void) { inb(0x80); Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/util/abuild/abuild Tue Oct 5 11:07:10 2010 (r5910) @@ -203,6 +203,7 @@ echo "CONFIG_SCANBUILD_ENABLE=y" >> .config echo "CONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" >> .config fi + echo "CONFIG_USBDEBUG=y" >> .config fi #yes "" | $MAKE oldconfig -j $cpus obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log

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[PATCH] Streamline CPU_ADDR_BITS usage
by Uwe Hermann 05 Oct '10

05 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

8 14

[commit] r5909 - in trunk/src/cpu/intel: model_68x model_6bx model_6xx
by repository service 04 Oct '10

04 Oct '10

Author: uwe Date: Mon Oct 4 22:43:55 2010 New Revision: 5909 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5909 Log: Add missing Intel Pentium II/III era CPU IDs. Add links to the respective Intel specification updates or manuals where the IDs are listed. Mention the possible core steppings of each CPU ID. There are duplicate IDs in model_6xx and model_68x for now, not sure if those should be eliminated, but there were already duplicates before this patch, so that's probably an extra issue to look into. Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/intel/model_68x/model_68x_init.c trunk/src/cpu/intel/model_6bx/model_6bx_init.c trunk/src/cpu/intel/model_6xx/model_6xx_init.c Modified: trunk/src/cpu/intel/model_68x/model_68x_init.c ============================================================================== --- trunk/src/cpu/intel/model_68x/model_68x_init.c Sat Oct 2 22:51:29 2010 (r5908) +++ trunk/src/cpu/intel/model_68x/model_68x_init.c Mon Oct 4 22:43:55 2010 (r5909) @@ -100,8 +100,26 @@ .init = model_68x_init, }; +/* + * Intel Celeron Processor Identification Information + * http://www.intel.com/design/celeron/qit/update.pdf + * + * Intel Pentium III Processor Identification and Package Information + * http://www.intel.com/design/pentiumiii/qit/update.pdf + * + * Intel Pentium III Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24445358.pdf + * + * Mobile Intel Pentium III/III-M Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24530663.pdf + */ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0680 }, + { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */ + { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/ + { X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */ + { X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */ + { 0, 0 }, }; Modified: trunk/src/cpu/intel/model_6bx/model_6bx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6bx/model_6bx_init.c Sat Oct 2 22:51:29 2010 (r5908) +++ trunk/src/cpu/intel/model_6bx/model_6bx_init.c Mon Oct 4 22:43:55 2010 (r5909) @@ -86,9 +86,16 @@ .init = model_6bx_init, }; +/* + * Pentium III Processor Identification and Package Information. + * http://www.intel.com/design/pentiumiii/qit/update.pdf + * + * Intel Pentium III Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24445358.pdf + */ static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x06B1 }, - { X86_VENDOR_INTEL, 0x06B4 }, /* Low Voltage PIII Micro-FCBGA Socket 479 */ + { X86_VENDOR_INTEL, 0x06b1 }, /* Pentium III/Celeron, tA1/A1/FPA1 */ + { X86_VENDOR_INTEL, 0x06b4 }, /* Pentium III, tB1/FPB1 */ { 0, 0 }, }; Modified: trunk/src/cpu/intel/model_6xx/model_6xx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6xx/model_6xx_init.c Sat Oct 2 22:51:29 2010 (r5908) +++ trunk/src/cpu/intel/model_6xx/model_6xx_init.c Mon Oct 4 22:43:55 2010 (r5909) @@ -51,20 +51,63 @@ static struct device_operations cpu_dev_ops = { .init = model_6xx_init, }; + +/* + * Intel Pentium Pro Processor Specification Update + * http://download.intel.com/design/archives/processors/pro/docs/24268935.pdf + * + * Intel Pentium II Processor Specification Update + * http://download.intel.com/design/PentiumII/specupdt/24333749.pdf + * + * Mobile Intel Pentium II Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24388757.pdf + * + * Intel Celeron Processor Identification Information + * http://www.intel.com/design/celeron/qit/update.pdf + * + * Intel Pentium II Xeon Processor Specification Update + * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf + * + * Intel Pentium III Processor Identification and Package Information + * http://www.intel.com/design/pentiumiii/qit/update.pdf + * + * Intel Pentium III Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24445358.pdf + * + * Mobile Intel Pentium III/III-M Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24530663.pdf + */ static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x0650 }, - { X86_VENDOR_INTEL, 0x0652 }, - { X86_VENDOR_INTEL, 0x0660 }, /* Celeron (Mendocino) */ - { X86_VENDOR_INTEL, 0x0665 }, - { X86_VENDOR_INTEL, 0x0672 }, - { X86_VENDOR_INTEL, 0x0673 }, + { X86_VENDOR_INTEL, 0x0611 }, /* Pentium Pro, B0 */ + { X86_VENDOR_INTEL, 0x0612 }, /* Pentium Pro, C0 */ + { X86_VENDOR_INTEL, 0x0616 }, /* Pentium Pro, sA0 */ + { X86_VENDOR_INTEL, 0x0617 }, /* Pentium Pro, sA1 */ + { X86_VENDOR_INTEL, 0x0619 }, /* Pentium Pro, sB1 */ + + { X86_VENDOR_INTEL, 0x0633 }, /* PII, C0 */ + { X86_VENDOR_INTEL, 0x0634 }, /* PII, C1 */ + + { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ + { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ + { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ + { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ + + { X86_VENDOR_INTEL, 0x0660 }, /* Celeron, A0 */ + { X86_VENDOR_INTEL, 0x0665 }, /* Celeron, B0 */ + { X86_VENDOR_INTEL, 0x066a }, /* PII, mdxA0/dmmA0 + others */ + + { X86_VENDOR_INTEL, 0x0672 }, /* PIII, kB0 */ + { X86_VENDOR_INTEL, 0x0673 }, /* PIII, kC0 */ + { X86_VENDOR_INTEL, 0x0680 }, - { X86_VENDOR_INTEL, 0x0681 }, - { X86_VENDOR_INTEL, 0x0683 }, - { X86_VENDOR_INTEL, 0x0686 }, - { X86_VENDOR_INTEL, 0x06A0 }, - { X86_VENDOR_INTEL, 0x06A1 }, - { X86_VENDOR_INTEL, 0x06A4 }, + { X86_VENDOR_INTEL, 0x0681 }, /* PIII, cA2/cA2c/A2/BA2/PA2/MA2 */ + { X86_VENDOR_INTEL, 0x0683 }, /* PIII/Celeron, cB0/cB0c/B0/BB0/PB0/MB0*/ + { X86_VENDOR_INTEL, 0x0686 }, /* PIII/Celeron, cC0/C0/BC0/PC0/MC0 */ + { X86_VENDOR_INTEL, 0x068a }, /* PIII/Celeron, cD0/D0/BD0/PD0 */ + + { X86_VENDOR_INTEL, 0x06a0 }, /* PIII, A0 */ + { X86_VENDOR_INTEL, 0x06a1 }, /* PIII, A1 */ + { X86_VENDOR_INTEL, 0x06a4 }, /* PIII, B0 */ { 0, 0 }, };

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coreboot October 2010