coreboot October 2010

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Fwd: Dogbert's Blog: BIOS Password Backdoors in Laptops
by ron minnich 08 Oct '10

08 Oct '10

Kinda fun. ---------- Forwarded message ---------- Date: Thu, Oct 7, 2010 at 11:25 AM Subject: Dogbert's Blog: BIOS Password Backdoors in Laptops To: ron minnich <rminnich(a)gmail.com> Amusing, and potentially useful, too. http://dogber1.blogspot.com/2009/05/table-of-reverse-engineered-bios.html

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[commit] r5920 - in trunk/src: . cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/socket_754 cpu/amd/socket_939 cpu/amd/socket_940 lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahoga...
by repository service 08 Oct '10

08 Oct '10

Author: myles Date: Fri Oct 8 01:02:06 2010 New Revision: 5920 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5920 Log: Remove duplicate line from pci_ids.h. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/src/Kconfig trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/model_fxx/powernow_acpi.c trunk/src/cpu/amd/socket_754/Kconfig trunk/src/cpu/amd/socket_939/Kconfig trunk/src/cpu/amd/socket_940/Kconfig trunk/src/lib/generic_sdram.c trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/Kconfig trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/Kconfig trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/Kconfig trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/Kconfig trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m4a785-m/Kconfig trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/Kconfig trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g3/Kconfig trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iwill/dk8_htx/Kconfig trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/Kconfig trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/Kconfig trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/pa78vm5/Kconfig trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/kt690/Kconfig trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/Kconfig trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/Kconfig trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/Kconfig trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/Kconfig trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/via/epia-m700/Kconfig trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdk8/Kconfig trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit.h trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -720,6 +720,10 @@ bool default n +config RAMINIT_SYSINFO + bool + default n + config ENABLE_APIC_EXT_ID bool default n Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Fri Oct 8 01:02:06 2010 (r5920) @@ -257,7 +257,7 @@ stop_this_cpu(); } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else static u32 init_cpus(u32 cpu_init_detectedx) @@ -918,7 +918,7 @@ u8 nodes = get_nodes(); u32 reg; -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */ reg = pci_read_config32(NODE_HT(0), 0x64); sysinfo->sblk = (reg >> 8) & 7; Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Fri Oct 8 01:02:06 2010 (r5920) @@ -209,7 +209,7 @@ stop_this_cpu(); } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else static u32 init_cpus(u32 cpu_init_detectedx) Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/powernow_acpi.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c Fri Oct 8 01:02:06 2010 (r5920) @@ -30,6 +30,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include <arch/cpu.h> +#if CONFIG_K8_REV_F_SUPPORT static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid, u8 *pstate_fid, u32 *pstate_power, int coreID, u32 pcontrol_blk, u8 plen, u8 onlyBSP) @@ -386,3 +387,12 @@ acpigen_patch_len(lens - 1); return lens; } + +#else + +int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) +{ + return 0; +} + +#endif Modified: trunk/src/cpu/amd/socket_754/Kconfig ============================================================================== --- trunk/src/cpu/amd/socket_754/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/socket_754/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -1,13 +1,3 @@ config CPU_AMD_SOCKET_754 bool select CPU_AMD_MODEL_FXX - -config CPU_SOCKET_TYPE - hex - default 0x10 - depends on CPU_AMD_SOCKET_754 - -config DIMM_SUPPORT - hex - default 0x108 - depends on CPU_AMD_SOCKET_754 Modified: trunk/src/cpu/amd/socket_939/Kconfig ============================================================================== --- trunk/src/cpu/amd/socket_939/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/socket_939/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -2,12 +2,3 @@ bool select CPU_AMD_MODEL_FXX -config CPU_SOCKET_TYPE - hex - default 0x0 - depends on CPU_AMD_SOCKET_939 - -config DIMM_SUPPORT - hex - default 0x108 - depends on CPU_AMD_SOCKET_939 Modified: trunk/src/cpu/amd/socket_940/Kconfig ============================================================================== --- trunk/src/cpu/amd/socket_940/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/cpu/amd/socket_940/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -9,14 +9,6 @@ select CPU_AMD_MODEL_FXX select CACHE_AS_RAM -config CPU_SOCKET_TYPE - hex - default 0x0 - -config DIMM_SUPPORT - hex - default 0x108 - config CPU_ADDR_BITS int default 40 Modified: trunk/src/lib/generic_sdram.c ============================================================================== --- trunk/src/lib/generic_sdram.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/lib/generic_sdram.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,9 +1,5 @@ #include <lib.h> /* Prototypes */ -#ifndef RAMINIT_SYSINFO - #define RAMINIT_SYSINFO 0 -#endif - static inline void print_debug_sdram_8(const char *strval, uint32_t val) { #if CONFIG_CACHE_AS_RAM @@ -14,7 +10,7 @@ } /* Setup SDRAM */ -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) #else void sdram_initialize(int controllers, const struct mem_controller *ctrl) @@ -25,7 +21,7 @@ for(i = 0; i < controllers; i++) { print_debug_sdram_8("Ram1.", i); - #if RAMINIT_SYSINFO == 1 + #if CONFIG_RAMINIT_SYSINFO sdram_set_registers(ctrl + i, sysinfo); #else sdram_set_registers(ctrl + i); @@ -36,7 +32,7 @@ for(i = 0; i < controllers; i++) { print_debug_sdram_8("Ram2.", i); - #if RAMINIT_SYSINFO == 1 + #if CONFIG_RAMINIT_SYSINFO sdram_set_spd_registers(ctrl + i, sysinfo); #else sdram_set_spd_registers(ctrl + i); @@ -50,7 +46,7 @@ */ print_debug("Ram3\n"); - #if RAMINIT_SYSINFO == 1 + #if CONFIG_RAMINIT_SYSINFO sdram_enable(controllers, ctrl, sysinfo); #else sdram_enable(controllers, ctrl); Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/amd/mahogany/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/mahogany/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -22,6 +22,7 @@ select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select GFXUMA config MAINBOARD_DIR Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/mahogany/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,6 +24,7 @@ select AMDMCT select GENERATE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/amd/pistachio/Kconfig ============================================================================== --- trunk/src/mainboard/amd/pistachio/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/pistachio/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/pistachio/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,6 +24,7 @@ select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,8 +1,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,5 +1,3 @@ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -22,6 +22,7 @@ select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select LIFT_BSP_APIC_ID select TINY_BOOTBLOCK Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ //#define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,6 +24,7 @@ select AMDMCT select GENERATE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -23,6 +23,7 @@ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select GFXUMA + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -15,6 +15,7 @@ select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -32,6 +32,7 @@ select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO select VGA select TINY_BOOTBLOCK select HAVE_MAINBOARD_RESOURCES Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/m4a785-m/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -23,6 +23,7 @@ select AMDMCT select GENERATE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -17,6 +17,7 @@ select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -24,8 +24,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -27,6 +27,7 @@ select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -27,6 +27,7 @@ select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/hp/dl145_g3/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -19,6 +19,7 @@ select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -25,8 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/hp/dl165_g6_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -19,6 +19,7 @@ select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT select TINY_BOOTBLOCK Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -25,8 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,6 +24,7 @@ select AMDMCT select GENERATE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8_htx/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,5 +1,3 @@ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8s2/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -17,6 +17,7 @@ select WAIT_BEFORE_CPUS_INIT select ATI_RAGE_XL select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,5 +1,3 @@ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/iwill/dk8x/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8x/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8x/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -16,6 +16,7 @@ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1,5 +1,3 @@ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/jetway/pa78vm5/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,6 +24,7 @@ select AMDMCT select GENERATE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select TINY_BOOTBLOCK select GFXUMA Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/kontron/kt690/Kconfig ============================================================================== --- trunk/src/mainboard/kontron/kt690/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/kontron/kt690/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/kontron/kt690/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms7260/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -23,7 +23,6 @@ #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 #define SET_NB_CFG_54 1 /* Used by RAM init. */ #define QRANK_DIMM_SUPPORT 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms7260/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -24,7 +24,6 @@ // #define DQS_TRAIN_DEBUG 1 // #define RES_DEBUG 1 -#define RAMINIT_SYSINFO 1 #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS == 1 Modified: trunk/src/mainboard/msi/ms9185/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9185/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9185/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -19,6 +19,7 @@ select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9185/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -23,8 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/msi/ms9282/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9282/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9282/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -18,6 +18,7 @@ select HAVE_HARD_RESET select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9282/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -18,6 +18,7 @@ select HAVE_OPTION_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT select TINY_BOOTBLOCK Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -21,6 +21,7 @@ select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -21,6 +21,7 @@ #select AP_CODE_IN_CAR select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -16,8 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select TINY_BOOTBLOCK select ENABLE_APIC_EXT_ID Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -19,6 +19,7 @@ select LIFT_BSP_APIC_ID select AMDMCT select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select TINY_BOOTBLOCK select ENABLE_APIC_EXT_ID Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/technexion/tim5690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim5690/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/technexion/tim5690/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -21,6 +21,7 @@ select GFXUMA select HAVE_MAINBOARD_RESOURCES select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/technexion/tim8690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim8690/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/technexion/tim8690/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 #define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/tyan/s2912/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -20,6 +20,7 @@ select LIFT_BSP_APIC_ID select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 - #define SET_NB_CFG_54 1 //used by raminit Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/tyan/s2912/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define K8_ALLOCATE_IO_RANGE 1 #define QRANK_DIMM_SUPPORT 1 Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -18,6 +18,7 @@ select HAVE_HARD_RESET select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT select TINY_BOOTBLOCK Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define RAMINIT_SYSINFO 1 - #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 Modified: trunk/src/mainboard/via/epia-m700/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m700/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/via/epia-m700/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -9,6 +9,7 @@ select BOARD_HAS_FADT select HAVE_OPTION_TABLE select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO config MAINBOARD_DIR string Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/mainboard/via/epia-m700/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -22,7 +22,6 @@ * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch. */ -#define RAMINIT_SYSINFO 1 #define PAYLOAD_IS_SEABIOS 0 #include <stdint.h> Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -26,75 +26,62 @@ select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select MMCONF_SUPPORT +if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE hex default 0x4000000 - depends on NORTHBRIDGE_AMD_AMDFAM10 config HT3_SUPPORT bool default y - depends on NORTHBRIDGE_AMD_AMDFAM10 config AMDMCT bool default y - depends on NORTHBRIDGE_AMD_AMDFAM10 config MEM_TRAIN_SEQ int default 0 - depends on NORTHBRIDGE_AMD_AMDFAM10 config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on NORTHBRIDGE_AMD_AMDFAM10 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config MMCONF_BASE_ADDRESS hex default 0xe0000000 - depends on NORTHBRIDGE_AMD_AMDFAM10 config MMCONF_BUS_NUMBER int default 256 - depends on NORTHBRIDGE_AMD_AMDFAM10 config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdfam10/bootblock.c" - depends on NORTHBRIDGE_AMD_AMDFAM10 config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config DIMM_FBDIMM bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config DIMM_DDR2 bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config DIMM_DDR3 bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config DIMM_REGISTERED bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 if DIMM_FBDIMM config DIMM_SUPPORT @@ -123,5 +110,6 @@ default 0x0005 endif endif +endif source src/northbridge/amd/amdfam10/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdk8/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdk8/Kconfig Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdk8/Kconfig Fri Oct 8 01:02:06 2010 (r5920) @@ -24,45 +24,40 @@ select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT +if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE hex default 0x4000000 - depends on NORTHBRIDGE_AMD_AMDK8 config K8_HT_FREQ_1G_SUPPORT bool default n - depends on NORTHBRIDGE_AMD_AMDK8 config MEM_TRAIN_SEQ int default 0 - depends on NORTHBRIDGE_AMD_AMDK8 config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on NORTHBRIDGE_AMD_AMDK8 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on NORTHBRIDGE_AMD_AMDK8 config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n - depends on NORTHBRIDGE_AMD_AMDK8 + +if K8_REV_F_SUPPORT config DIMM_DDR2 bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 config DIMM_REGISTERED bool default n - depends on NORTHBRIDGE_AMD_AMDFAM10 if DIMM_DDR2 if DIMM_REGISTERED @@ -76,6 +71,10 @@ hex default 0x0004 endif -endif +endif #DIMM_DDR2 + +endif #K8_REV_F_SUPPORT + +endif #NORTHBRIDGE_AMD_K8 source src/northbridge/amd/amdk8/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Fri Oct 8 01:02:06 2010 (r5920) @@ -1813,7 +1813,7 @@ return needs_reset; } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void setup_coherent_ht_domain(void) #else static int setup_coherent_ht_domain(void) @@ -1835,7 +1835,7 @@ } coherent_ht_finalize(nodes); -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO return optimize_link_coherent_ht(); #endif } Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Fri Oct 8 01:02:06 2010 (r5920) @@ -11,10 +11,6 @@ #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif -#ifndef RAMINIT_SYSINFO - #define RAMINIT_SYSINFO 0 -#endif - #ifndef K8_ALLOCATE_IO_RANGE #define K8_ALLOCATE_IO_RANGE 0 #endif @@ -297,7 +293,7 @@ return needs_reset; } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) #else static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) @@ -308,7 +304,7 @@ uint8_t next_unitid, last_unitid; unsigned uoffs; -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO int reset_needed = 0; #endif @@ -415,7 +411,7 @@ flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; - #if RAMINIT_SYSINFO == 1 + #if CONFIG_RAMINIT_SYSINFO /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ { struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num]; @@ -451,7 +447,7 @@ flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); - #if RAMINIT_SYSINFO == 1 + #if CONFIG_RAMINIT_SYSINFO // Here need to change the dev in the array int i; for(i=0;i<sysinfo->link_pair_num;i++) @@ -470,14 +466,14 @@ } #endif -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO return reset_needed; #endif } #if 0 -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) #else static int ht_setup_chain(device_t udev, unsigned upos) @@ -501,7 +497,7 @@ offset_unitid = 1; #endif -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo); #else return ht_setup_chainx(udev, upos, 0, offset_unitid); @@ -636,7 +632,7 @@ } #endif -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo) #else static int ht_setup_chains(uint8_t ht_c_num) @@ -651,7 +647,7 @@ device_t udev; uint8_t i; -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO int reset_needed = 0; #else sysinfo->link_pair_num = 0; @@ -692,7 +688,7 @@ upos = ((reg & 0xf00)>>8) * 0x20 + 0x80; udev = PCI_DEV(0, devpos, 0); -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not #else reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not @@ -700,7 +696,7 @@ } -#if RAMINIT_SYSINFO == 0 +#if !CONFIG_RAMINIT_SYSINFO reset_needed |= optimize_link_read_pointers_chain(ht_c_num); return reset_needed; @@ -712,7 +708,7 @@ static inline unsigned get_nodes(void); #endif -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void ht_setup_chains_x(struct sys_info *sysinfo) #else static int ht_setup_chains_x(void) @@ -734,7 +730,7 @@ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3) ); -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; @@ -840,7 +836,7 @@ } } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO sysinfo->ht_c_num = i; ht_setup_chains(i, sysinfo); sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); @@ -850,7 +846,7 @@ } -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static int optimize_link_incoherent_ht(struct sys_info *sysinfo) { // We need to use recorded link pair info to optimize the link Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdk8/raminit.c Fri Oct 8 01:02:06 2010 (r5920) @@ -45,7 +45,7 @@ return pci_read_config32(ctrl->f0, 0) == 0x11001022; } -#if RAMINIT_SYSINFO==1 +#if CONFIG_RAMINIT_SYSINFO static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else static void sdram_set_registers(const struct mem_controller *ctrl) @@ -2062,7 +2062,7 @@ return dimm_mask; } -#if RAMINIT_SYSINFO==1 +#if CONFIG_RAMINIT_SYSINFO static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) #else static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -2223,7 +2223,7 @@ #endif #define TIMEOUT_LOOPS 300000 -#if RAMINIT_SYSINFO == 1 +#if CONFIG_RAMINIT_SYSINFO static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) #else static void sdram_enable(int controllers, const struct mem_controller *ctrl) Modified: trunk/src/northbridge/amd/amdk8/raminit.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.h Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/amd/amdk8/raminit.h Fri Oct 8 01:02:06 2010 (r5920) @@ -15,7 +15,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); void setup_resource_map(const unsigned int *register_values, int max); -#if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1 +#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); #else void sdram_initialize(int controllers, const struct mem_controller *ctrl); Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Thu Oct 7 20:25:04 2010 (r5919) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Fri Oct 8 01:02:06 2010 (r5920) @@ -20,7 +20,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define RAMINIT_SYSINFO 1 #include <stdint.h> #include <device/pci_def.h>

3 2

[PATCH] rs780/690 handle non-zero sblink
by Liu Tao 08 Oct '10

08 Oct '10

Hi, this patch handles sblink in ProgK8TempMmioBase(), so enable_pcie_bar3() can work correctly when rs780 is not on CPU's HT0 port. tested on a K8 board with rs780 on HT Link1. -- Regards, Liu Tao

1 0

[commit] r5923 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 08 Oct '10

08 Oct '10

Author: zbao Date: Fri Oct 8 07:08:47 2010 New Revision: 5923 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5923 Log: Trivial. Spell checking. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -30,7 +30,7 @@ * ordinarily in 64-bit mode. * * Trc precision does not use extra Jedec defined fractional component. - * InsteadTrc (course) is rounded up to nearest 1 ns. + * Instead Trc (course) is rounded up to nearest 1 ns. * * Mini and Micro DIMM not supported. Only RDIMM, UDIMM, SO-DIMM defined types * supported. @@ -183,7 +183,7 @@ * on setup options). It is the responsibility of PCI subsystem to * create an uncacheable IO region below 4GB and to adjust TOP_MEM * downward prior to any IO mapping or accesses. It is the same - * responsibility of the CPU sub-system prior toaccessing LAPIC. + * responsibility of the CPU sub-system prior to accessing LAPIC. * * Slot Number is an external convention, and is determined by OEM with * accompanying silk screening. OEM may choose to use Slot number @@ -655,7 +655,7 @@ { /* Initiates a memory clear operation for all node. The mem clr - * is done in paralel. After the memclr is complete, all processors + * is done in parallel. After the memclr is complete, all processors * status are checked to ensure that memclr has completed. */ u8 Node; @@ -856,7 +856,7 @@ * HW memory clear process that the chip is capable of. The sooner * that dram init is set for all nodes, the faster the memory system * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processeses for non BSP nodes sooner. + * two loops so as to start the processes for non BSP nodes sooner. * This procedure will not wait for the process to finish. * Synchronization is handled elsewhere. */ @@ -878,7 +878,7 @@ reg = 0x78 + reg_off; val = Get_NB32(dev, reg); /* Setting this bit forces a 1T window with hard left - * pass/fail edge and a probabalistic right pass/fail + * pass/fail edge and a probabilistic right pass/fail * edge. LEFT edge is referenced for final * receiver enable position.*/ val |= 1 << DqsRcvEnTrain; @@ -1038,7 +1038,7 @@ } else { byte = mctRead_SPD(smbaddr, SPD_TRCRFC); if (byte & 0xF0) { - val++; /* round up in case fractional extention is non-zero.*/ + val++; /* round up in case fractional extension is non-zero.*/ } } if (Trc < val) @@ -1496,7 +1496,7 @@ DramConfigMisc = 0; DramConfigMisc2 = 0; - /* set bank addessing and Masks, plus CS pops */ + /* set bank addressing and Masks, plus CS pops */ SPDSetBanks_D(pMCTstat, pDCTstat, dct); if (pDCTstat->ErrCode == SC_StopError) goto AutoConfig_exit; @@ -1582,7 +1582,7 @@ } if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ + DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */ if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) @@ -3405,7 +3405,7 @@ if (pDCTstat->CSPresent & (1 << cs)) { odt &= ~(1 << (cs / 2)); - /* if quad-rank capable platform clear adtitional pins */ + /* if quad-rank capable platform clear additional pins */ if (max_dimms != MAX_CS_SUPPORTED) { if (pDCTstat->CSPresent & (1 << (cs + 1))) odt &= ~(4 << (cs / 2)); @@ -3768,7 +3768,7 @@ * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */ for (Node = 0; Node < 8; Node++) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -479,7 +479,7 @@ continue; } - BanksPresent = 1; /* flag for atleast one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4); Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -656,7 +656,7 @@ { /* Initiates a memory clear operation for all node. The mem clr - * is done in paralel. After the memclr is complete, all processors + * is done in parallel. After the memclr is complete, all processors * status are checked to ensure that memclr has completed. */ u8 Node; @@ -868,7 +868,7 @@ * HW memory clear process that the chip is capable of. The sooner * that dram init is set for all nodes, the faster the memory system * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processeses for non BSP nodes sooner. + * two loops so as to start the processes for non BSP nodes sooner. * This procedure will not wait for the process to finish. * Synchronization is handled elsewhere. */ @@ -1520,7 +1520,7 @@ DramConfigMisc = 0; DramConfigMisc2 = 0; - /* set bank addessing and Masks, plus CS pops */ + /* set bank addressing and Masks, plus CS pops */ SPDSetBanks_D(pMCTstat, pDCTstat, dct); if (pDCTstat->ErrCode == SC_StopError) goto AutoConfig_exit; @@ -1547,7 +1547,7 @@ else val = 6; DramControl &= ~0xFF; - DramControl |= val; /* RdPrtInit = 6 for Cx CPU */ + DramControl |= val; /* RdPtrInit = 6 for Cx CPU */ if (mctGet_NVbits(NV_CLKHZAltVidC3)) DramControl |= 1<<16; /* check */ @@ -1570,7 +1570,7 @@ } if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ + DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */ if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) @@ -3511,7 +3511,7 @@ * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR3 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR3 training. */ for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Fri Oct 8 05:35:12 2010 (r5922) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Fri Oct 8 07:08:47 2010 (r5923) @@ -481,7 +481,7 @@ continue; } - BanksPresent = 1; /* flag for atleast one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);

1 0

[PATCH try 4] Reduce duplicate definition in CAR code.
by Warren Turkal 08 Oct '10

08 Oct '10

I added names for the AMD registers and separated each .long onto it's own line to avoid any bugs of the type the caldani mentioned. Comments? Acks? :) Thanks, wt 8<--------------------------- Macros for the register addresses for the MTRR MSRs are already defined in include/cpu/x86/car.h. This patch uses those macros instead of creating a second instance of that same data. I also combined common MTRR definitions into a macro. I also added a few macros to the amd mtrr.h to make the MSR naming more consistent. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/car/cache_as_ram.inc | 24 ++++----------------- src/cpu/intel/car/cache_as_ram.inc | 17 +++------------ src/cpu/via/car/cache_as_ram.inc | 17 +++------------ src/include/cpu/amd/mtrr.h | 27 +++++++++++++++++++----- src/include/cpu/x86/mtrr.h | 39 ++++++++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 51 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5318272..4f692b2 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -396,23 +396,9 @@ CAR_FAM10_ap_out: post_code(0xaf) /* Should never see this POST code. */ -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - -var_iorr_msr: - .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 - -mem_top: - .long 0xC001001A, 0xC001001D - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES +AMD_MTRR_MSRS_TABLE_ENTRIES +END_MTRR_MSRS_TABLE_ENTRY cache_as_ram_setup_out: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index d8465f4..29a9c95 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -115,7 +115,7 @@ NotHtProcessor: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -128,18 +128,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES +END_MTRR_MSRS_TABLE_ENTRY clear_fixed_var_mtrr_out: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index d6df4a9..6394110 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -47,7 +47,7 @@ CacheAsRam: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -60,18 +60,9 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ +all_mtrr_msrs: +X86_MTRR_MSRS_TABLE_ENTRIES +END_MTRR_MSRS_TABLE_ENTRY clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(0), %ecx diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index c7b3fca..ec56c06 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -21,16 +21,31 @@ #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define IORR1_BASE 0xC0010018 -#define IORR1_MASK 0xC0010019 -#define TOP_MEM 0xC001001A -#define TOP_MEM2 0xC001001D +#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) +#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) + +#define TOP_MEM_MSR 0xC001001A +#define TOP_MEM2_MSR 0xC001001D +#define TOP_MEM TOP_MEM_MSR +#define TOP_MEM2 TOP_MEM2_MSR #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) +#if defined(ASSEMBLY) +.macro AMD_MTRR_MSRS_TABLE_ENTRIES + /* Variable IORR MTRR MSRs */ + .long IORRBase_MSR(0) + .long IORRMask_MSR(0) + .long IORRBase_MSR(1) + .long IORRMask_MSR(1) + + /* Top of memory MTRR MSRs */ + .long TOP_MEM_MSR + .long TOP_MEM2_MSR +.endm /* AMD_MTRR_MSRS_TABLE_ENTRIES */ +#endif /* defined(ASSEMBLY) */ + #if !defined(__PRE_RAM__) && !defined(ASSEMBLY) void amd_setup_mtrrs(void); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index e79c90e..826a46d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -34,6 +34,45 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f +#if defined (ASSEMBLY) +.macro X86_MTRR_MSRS_TABLE_ENTRIES + /* fixed mtrr MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var mtrr MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) +.endm /* X86_MTRR_MSRS_TABLE_ENTRIES */ + +.macro END_MTRR_MSRS_TABLE_ENTRY + .long 0x000 /* NULL, end of table */ +.endm /* END_MTRR_MSRS_TABLE_ENTRY */ +#endif /* defined (ASSEMBLY) */ + #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); -- 1.7.1

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[commit] r5922 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 08 Oct '10

08 Oct '10

Author: zbao Date: Fri Oct 8 05:35:12 2010 New Revision: 5922 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5922 Log: Trivial. Fix the typo. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922) @@ -848,7 +848,7 @@ struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -863,7 +863,7 @@ struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 01:42:17 2010 (r5921) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Fri Oct 8 05:35:12 2010 (r5922) @@ -800,7 +800,7 @@ struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -814,7 +814,7 @@ struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */

1 0

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)
by Uwe Hermann 08 Oct '10

08 Oct '10

See patch. Next steps will be: - Remove .c file includes from 440BX board's romstage.c files. - Add L2 cache support from Keith Hui, and split CPU models before that, as needed by that patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

5 5

[commit] r5921 - in trunk/src/cpu: amd/model_10xxx amd/model_fxx amd/model_gx2 intel/model_1067x intel/model_106cx intel/model_69x intel/model_6dx intel/model_6ex intel/model_6fx intel/model_6xx in...
by repository service 08 Oct '10

08 Oct '10

Author: uwe Date: Fri Oct 8 01:42:17 2010 New Revision: 5921 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5921 Log: Remove some duplicate #include files (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/cpu/amd/model_fxx/model_fxx_update_microcode.c trunk/src/cpu/amd/model_gx2/model_gx2_init.c trunk/src/cpu/intel/model_1067x/model_1067x_init.c trunk/src/cpu/intel/model_106cx/model_106cx_init.c trunk/src/cpu/intel/model_69x/model_69x_init.c trunk/src/cpu/intel/model_6dx/model_6dx_init.c trunk/src/cpu/intel/model_6ex/model_6ex_init.c trunk/src/cpu/intel/model_6fx/model_6fx_init.c trunk/src/cpu/intel/model_6xx/model_6xx_init.c trunk/src/cpu/intel/model_f0x/model_f0x_init.c trunk/src/cpu/intel/model_f1x/model_f1x_init.c trunk/src/cpu/intel/model_f2x/model_f2x_init.c trunk/src/cpu/intel/model_f3x/model_f3x_init.c trunk/src/cpu/intel/model_f4x/model_f4x_init.c trunk/src/cpu/via/model_c3/model_c3_init.c trunk/src/cpu/via/model_c7/model_c7_init.c Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -27,9 +27,7 @@ #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> - #include "northbridge/amd/amdfam10/amdfam10.h" - #include <cpu/amd/model_10xxx_rev.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -7,6 +7,7 @@ * Copyright 2005 AMD * 2005.08 yhlu add microcode support */ + #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -17,17 +18,13 @@ #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> - #include "northbridge/amd/amdk8/amdk8.h" - #include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> - #include <cpu/amd/multicore.h> - #include <cpu/amd/model_fxx_msr.h> #if CONFIG_WAIT_BEFORE_CPUS_INIT @@ -110,6 +107,7 @@ msr_t base; msr_t mask; }; + struct mtrr_state { struct mtrr mtrrs[MTRR_COUNT]; msr_t top_mem, top_mem2; Modified: trunk/src/cpu/amd/model_fxx/model_fxx_update_microcode.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_update_microcode.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/amd/model_fxx/model_fxx_update_microcode.c Fri Oct 8 01:42:17 2010 (r5921) @@ -19,16 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Description: Microcode patch support for k8 by yhlu - */ - - #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <string.h> - #include <cpu/amd/microcode.h> static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { @@ -80,7 +74,6 @@ }; - unsigned new_id; int i; @@ -94,7 +87,6 @@ } return new_id; - } void model_fxx_update_microcode(unsigned cpu_deviceid) @@ -105,6 +97,4 @@ equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); if(equivalent_processor_rev_id != 0) amd_update_microcode(microcode_updates, equivalent_processor_rev_id); - } - Modified: trunk/src/cpu/amd/model_gx2/model_gx2_init.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/model_gx2_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/amd/model_gx2/model_gx2_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> - static void vsm_end_post_smi(void) { __asm__ volatile ( Modified: trunk/src/cpu/intel/model_1067x/model_1067x_init.c ============================================================================== --- trunk/src/cpu/intel/model_1067x/model_1067x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_1067x/model_1067x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -30,7 +30,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> static const uint32_t microcode_updates[] = { Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/model_106cx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -28,7 +28,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> #include <usbdebug.h> Modified: trunk/src/cpu/intel/model_69x/model_69x_init.c ============================================================================== --- trunk/src/cpu/intel/model_69x/model_69x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_69x/model_69x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -9,7 +8,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static uint32_t microcode_updates[] = { /* Dummy terminator */ @@ -19,7 +17,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_69x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -37,6 +34,7 @@ static struct device_operations cpu_dev_ops = { .init = model_69x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0690 }, /* Pentium M */ { X86_VENDOR_INTEL, 0x0695 }, Modified: trunk/src/cpu/intel/model_6dx/model_6dx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6dx/model_6dx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_6dx/model_6dx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -9,7 +8,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static uint32_t microcode_updates[] = { /* Dummy terminator */ @@ -19,7 +17,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_6dx_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -37,6 +34,7 @@ static struct device_operations cpu_dev_ops = { .init = model_6dx_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x06D0 }, /* Pentium M on 90nm with 2MiB of L2 cache */ { X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */ Modified: trunk/src/cpu/intel/model_6ex/model_6ex_init.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/model_6ex_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_6ex/model_6ex_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -30,7 +30,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> #include <usbdebug.h> Modified: trunk/src/cpu/intel/model_6fx/model_6fx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/model_6fx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_6fx/model_6fx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -30,7 +30,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/name.h> #include <usbdebug.h> Modified: trunk/src/cpu/intel/model_6xx/model_6xx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6xx/model_6xx_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_6xx/model_6xx_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -9,7 +8,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static uint32_t microcode_updates[] = { /* WARNING - Intel has a new data structure that has variable length @@ -33,7 +31,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_6xx_init(device_t dev) { /* Turn on caching if we haven't already */ Modified: trunk/src/cpu/intel/model_f0x/model_f0x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f0x/model_f0x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_f0x/model_f0x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -9,7 +8,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> /* 256KB cache */ static uint32_t microcode_updates[] = { @@ -25,7 +23,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_f0x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -43,6 +40,7 @@ static struct device_operations cpu_dev_ops = { .init = model_f0x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f0A }, { 0, 0 }, Modified: trunk/src/cpu/intel/model_f1x/model_f1x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f1x/model_f1x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_f1x/model_f1x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -9,7 +8,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> /* 256KB cache */ static uint32_t microcode_updates[] = { @@ -25,7 +23,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_f1x_init(device_t dev) { /* Turn on caching if we haven't already */ @@ -43,6 +40,7 @@ static struct device_operations cpu_dev_ops = { .init = model_f1x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f12 }, { 0, 0 }, Modified: trunk/src/cpu/intel/model_f2x/model_f2x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f2x/model_f2x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_f2x/model_f2x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -9,7 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> /* 512KB cache */ static uint32_t microcode_updates[] = { @@ -49,6 +48,7 @@ static struct device_operations cpu_dev_ops = { .init = model_f2x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f22 }, { X86_VENDOR_INTEL, 0x0f24 }, Modified: trunk/src/cpu/intel/model_f3x/model_f3x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f3x/model_f3x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_f3x/model_f3x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -10,7 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static uint32_t microcode_updates[] = { /* WARNING - Intel has a new data structure that has variable length @@ -29,7 +27,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_f3x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -50,6 +47,7 @@ static struct device_operations cpu_dev_ops = { .init = model_f3x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f34 }, /* Xeon */ { 0, 0 }, Modified: trunk/src/cpu/intel/model_f4x/model_f4x_init.c ============================================================================== --- trunk/src/cpu/intel/model_f4x/model_f4x_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/intel/model_f4x/model_f4x_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -1,6 +1,5 @@ #include <console/console.h> #include <device/device.h> -#include <device/device.h> #include <device/pci.h> #include <string.h> #include <cpu/cpu.h> @@ -10,7 +9,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static uint32_t microcode_updates[] = { /* WARNING - Intel has a new data structure that has variable length @@ -26,7 +24,6 @@ 0x0, 0x0, 0x0, 0x0, }; - static void model_f4x_init(device_t cpu) { /* Turn on caching if we haven't already */ @@ -47,6 +44,7 @@ static struct device_operations cpu_dev_ops = { .init = model_f4x_init, }; + static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f41 }, /* Xeon */ { 0, 0 }, Modified: trunk/src/cpu/via/model_c3/model_c3_init.c ============================================================================== --- trunk/src/cpu/via/model_c3/model_c3_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/via/model_c3/model_c3_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -25,7 +25,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> static void model_c3_init(device_t dev) { Modified: trunk/src/cpu/via/model_c7/model_c7_init.c ============================================================================== --- trunk/src/cpu/via/model_c7/model_c7_init.c Fri Oct 8 01:02:06 2010 (r5920) +++ trunk/src/cpu/via/model_c7/model_c7_init.c Fri Oct 8 01:42:17 2010 (r5921) @@ -23,13 +23,11 @@ #include <console/console.h> #include <delay.h> #include <stdlib.h> - #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199

1 0

[PATCH] Kconfig fixes & RAMINIT_SYSINFO
by Myles Watson 08 Oct '10

08 Oct '10

Kconfig_if.diff : use if instead of depends on to avoid typos socket_type.diff : don't define socket_type and dimm_type when they aren't used raminit_sysinfo.diff : get rid of another define Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[PATCH] Stop putting useless or sensitive information in coreboot images
by Uwe Hermann 07 Oct '10

07 Oct '10

See patch. This is only build-tested, please carefully review if it might have impact on software that depends on the coreboot tables. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

3 2

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coreboot October 2010