coreboot October 2010

coreboot@coreboot.org

55 participants
316 discussions

[commit] r5941 - trunk/src/arch/i386
by repository service 12 Oct '10

12 Oct '10

Author: wt Date: Tue Oct 12 08:12:00 2010 New Revision: 5941 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5941 Log: Build bootblock.S instead of bootblock.c. The file is actually just including a bunch of assembly. The build rule for bootblock.c even states that the file will be "assembler-with-cpp." Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/Makefile.bootblock.inc Modified: trunk/src/arch/i386/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bootblock.inc Tue Oct 12 01:22:24 2010 (r5940) +++ trunk/src/arch/i386/Makefile.bootblock.inc Tue Oct 12 08:12:00 2010 (r5941) @@ -52,7 +52,7 @@ mkdir -p $(obj)/bootblock printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ -$(obj)/bootblock/bootblock.c: $$(bootblock_inc) +$(obj)/bootblock/bootblock.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/bootblock printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ @@ -61,9 +61,9 @@ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc @printf " ROMCC $(subst $(obj)/,,$(@))\n"

1 0

[PATCH try 5] Reduce duplicate definition in CAR code.
by Warren Turkal 12 Oct '10

12 Oct '10

I implemented the consensus method of only replacing the magic numbers with constants instead of pulling the lists into assembler macros in mtrr.h. How does this one look to everyone? Comments? Acks? Thanks, wt 8<--------------------------------- Macros for the register addresses for the MTRR MSRs are already defined in include/cpu/x86/car.h. This patch uses those macros instead of creating a second instance of that same data. I also added a few macros to the amd mtrr.h to make the MSR naming more consistent. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/cpu/amd/car/cache_as_ram.inc | 59 +++++++++++++++++++++++++---------- src/cpu/intel/car/cache_as_ram.inc | 45 ++++++++++++++++++++------- src/cpu/via/car/cache_as_ram.inc | 43 +++++++++++++++++++------- src/include/cpu/amd/mtrr.h | 13 ++++---- 4 files changed, 114 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5318272..5a19a0c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -155,7 +155,7 @@ enable_fixed_mtrr_dram_modify: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -396,23 +396,48 @@ CAR_FAM10_ap_out: post_code(0xaf) /* Should never see this POST code. */ -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + + /* Variable IORR MTRR MSRs */ + .long IORRBase_MSR(0) + .long IORRMask_MSR(0) + .long IORRBase_MSR(1) + .long IORRMask_MSR(1) + + /* Top of memory MTRR MSRs */ + .long TOP_MEM_MSR + .long TOP_MEM2_MSR -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - -var_iorr_msr: - .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 - -mem_top: - .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */ cache_as_ram_setup_out: diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index d8465f4..e228f4c 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -115,7 +115,7 @@ NotHtProcessor: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -128,17 +128,38 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index d6df4a9..1f0bed2 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -47,7 +47,7 @@ CacheAsRam: /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -60,17 +60,38 @@ clear_fixed_var_mtrr: jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index c7b3fca..e866fb9 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -21,12 +21,13 @@ #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define IORR1_BASE 0xC0010018 -#define IORR1_MASK 0xC0010019 -#define TOP_MEM 0xC001001A -#define TOP_MEM2 0xC001001D +#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) +#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) + +#define TOP_MEM_MSR 0xC001001A +#define TOP_MEM2_MSR 0xC001001D +#define TOP_MEM TOP_MEM_MSR +#define TOP_MEM2 TOP_MEM2_MSR #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -- 1.7.1

2 2

[PATCH] Build bootblock.S instead of bootblock.c.
by Warren Turkal 12 Oct '10

12 Oct '10

I did some test builds on a few intel boards using the tiny bootblock. I think that this should be pretty low risk. Looking for an ack, wt 8<------------- The file is actually just including a bunch of assembly. The build rule for bootblock.c even states that the file will be "assembler-with-cpp." Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/arch/i386/Makefile.bootblock.inc | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/i386/Makefile.bootblock.inc b/src/arch/i386/Makefile.bootblock.inc index face04c..6d975ac 100644 --- a/src/arch/i386/Makefile.bootblock.inc +++ b/src/arch/i386/Makefile.bootblock.inc @@ -52,7 +52,7 @@ $(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions mkdir -p $(obj)/bootblock printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ -$(obj)/bootblock/bootblock.c: $$(bootblock_inc) +$(obj)/bootblock/bootblock.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/bootblock printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@ @@ -61,9 +61,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/b @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc @printf " ROMCC $(subst $(obj)/,,$(@))\n" -- 1.7.1

2 2

Re: [coreboot] [PATCH] coreboot: fix typo after r5925
by Uwe Hermann 12 Oct '10

12 Oct '10

Hi Sylvain, please always reply to the mailing list, not individual developers. The "reply all" button in your mail client should do the right thing. On Sun, Oct 10, 2010 at 07:08:39PM +0200, Sylvain 'ythier' Hitier wrote: > Hello, > > Here is an untested patch, but I feel enough confident with C. > > Regards, > Sylvain "ythier" Hitier > > ======== > > Fix typo after r5925. > BTW, embed the always-the-same string instead of referencing it through "%s". > > Signed-off-by: Sylvain Hitier <sylvain.hitier(a)gmail.com> Thanks, committed in r5940 with a small change, I only moved "IDE interface" into the string, which should save a little bit of space in the ROM (as the strings for primary and secondary are now identical, except for the contents of %s). I also did the same micro-optimization in i82371EB. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 0

[commit] r5940 - in trunk/src/southbridge/intel: i82371eb i82801ax
by repository service 12 Oct '10

12 Oct '10

Author: uwe Date: Tue Oct 12 01:22:24 2010 New Revision: 5940 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5940 Log: Fix typo after r5925. BTW, embed the always-the-same string instead of referencing it through "%s". Do the same for i82371EB while we're at it. Signed-off-by: Sylvain Hitier <sylvain.hitier(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c Tue Oct 12 00:49:39 2010 (r5939) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_ide.c Tue Oct 12 01:22:24 2010 (r5940) @@ -48,14 +48,14 @@ reg16 = pci_read_config16(dev, IDETIM_PRI); reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_PRI, reg16); - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", conf->ide0_enable ? "on" : "off"); /* Enable/disable the secondary IDE interface. */ reg16 = pci_read_config16(dev, IDETIM_SEC); reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_SEC, reg16); - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Secondary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", conf->ide1_enable ? "on" : "off"); /* Enable access to the legacy IDE ports (both primary and secondary), Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Tue Oct 12 00:49:39 2010 (r5939) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Tue Oct 12 01:22:24 2010 (r5940) @@ -38,7 +38,7 @@ reg16 &= ~IDE_DECODE_ENABLE; if (!conf || conf->ide0_enable) reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_PRI, reg16); @@ -46,7 +46,7 @@ reg16 &= ~IDE_DECODE_ENABLE; if (!conf || conf->ide1_enable) reg16 |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_SEC, reg16); }

1 0

build service results for r5939
by repository service 12 Oct '10

12 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 5939 to the coreboot repository. This caused the following changes: Change Log: Build fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of intel:d810e2cb has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5939 - trunk/src/southbridge/intel/i82801bx
by repository service 12 Oct '10

12 Oct '10

Author: uwe Date: Tue Oct 12 00:49:39 2010 New Revision: 5939 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5939 Log: Build fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Mon Oct 11 23:38:49 2010 (r5938) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Tue Oct 12 00:49:39 2010 (r5939) @@ -27,7 +27,6 @@ static void enable_smbus(void) { device_t dev; - uint16_t device_id; /* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3); Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Mon Oct 11 23:38:49 2010 (r5938) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Tue Oct 12 00:49:39 2010 (r5939) @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "i82801bx.h" static void pci_init(struct device *dev) {

1 0

build service results for r5938
by repository service 11 Oct '10

11 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 5938 to the coreboot repository. This caused the following changes: Change Log: First round of ICH2/ICH2-M cleanups after split from i82801xx. - Drop all non-ICH2 "struct pci_driver" entries from all files. - Kconfig: Add missing USE_WATCHDOG_ON_BOOT. - Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI. - Simplify lots of code, getting rid of i82801xx remainders. - Use u8 et al (instead of uint8_t) in a few more places. - Use #defines from header files where possible. - Various other fixes and updates. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of intel:d810e2cb has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5938&device=d810e2cb&vendo… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5938 - trunk/src/southbridge/intel/i82801bx
by repository service 11 Oct '10

11 Oct '10

Author: uwe Date: Mon Oct 11 23:38:49 2010 New Revision: 5938 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5938 Log: First round of ICH2/ICH2-M cleanups after split from i82801xx. - Drop all non-ICH2 "struct pci_driver" entries from all files. - Kconfig: Add missing USE_WATCHDOG_ON_BOOT. - Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI. - Simplify lots of code, getting rid of i82801xx remainders. - Use u8 et al (instead of uint8_t) in a few more places. - Use #defines from header files where possible. - Various other fixes and updates. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/southbridge/intel/i82801bx/i82801bx_sata.c trunk/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c Modified: trunk/src/southbridge/intel/i82801bx/Kconfig trunk/src/southbridge/intel/i82801bx/Makefile.inc trunk/src/southbridge/intel/i82801bx/chip.h trunk/src/southbridge/intel/i82801bx/i82801bx.c trunk/src/southbridge/intel/i82801bx/i82801bx.h trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c Modified: trunk/src/southbridge/intel/i82801bx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Kconfig Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/Kconfig Mon Oct 11 23:38:49 2010 (r5938) @@ -20,4 +20,5 @@ config SOUTHBRIDGE_INTEL_I82801BX bool select HAVE_HARD_RESET + select USE_WATCHDOG_ON_BOOT Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Makefile.inc Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/Makefile.inc Mon Oct 11 23:38:49 2010 (r5938) @@ -24,10 +24,8 @@ driver-y += i82801bx_lpc.c driver-y += i82801bx_nic.c driver-y += i82801bx_pci.c -driver-y += i82801bx_sata.c driver-y += i82801bx_smbus.c driver-y += i82801bx_usb.c -driver-y += i82801bx_usb_ehci.c ramstage-y += i82801bx_reset.c ramstage-y += i82801bx_watchdog.c Modified: trunk/src/southbridge/intel/i82801bx/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/chip.h Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/chip.h Mon Oct 11 23:38:49 2010 (r5938) @@ -19,38 +19,26 @@ */ /* - * The i82801bx code currently supports: - * - 82801AA - * - 82801AB - * - 82801BA - * - 82801CA - * - 82801DB - * - 82801DBM - * - 82801EB - * - 82801ER - * - * This code should NOT be used for ICH6 and later versions. + * The i82801bx code supports: 82801BA/82801BAM (ICH2/ICH2-M) */ #ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801bx_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; + u8 pirqa_routing; + u8 pirqb_routing; + u8 pirqc_routing; + u8 pirqd_routing; + u8 pirqe_routing; + u8 pirqf_routing; + u8 pirqg_routing; + u8 pirqh_routing; - uint8_t ide0_enable; - uint8_t ide1_enable; + u8 ide0_enable; + u8 ide1_enable; }; extern struct chip_operations southbridge_intel_i82801bx_ops; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.c Mon Oct 11 23:38:49 2010 (r5938) @@ -27,38 +27,21 @@ void i82801bx_enable(device_t dev) { - unsigned int index = 0; - uint16_t cur_disable_mask, new_disable_mask; + u16 reg16, index; + device_t lpc_dev; - /* All 82801xx devices should be on bus 0. */ - unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC - device_t lpc_dev = dev_find_slot(0, devfn); // 0 + /* Search for the 82801BA/BAM LPC device (D31:F0) on PCI bus 0. */ + lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc_dev) return; - /* We're going to assume, perhaps incorrectly, that if a function - * exists it can be disabled. Workarounds for ICH variants that don't - * follow this should be done by checking the device ID. - */ - if (PCI_SLOT(dev->path.pci.devfn) == 31) { - index = PCI_FUNC(dev->path.pci.devfn); - } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { - index = 8 + PCI_FUNC(dev->path.pci.devfn); - } + index = PCI_FUNC(dev->path.pci.devfn); - /* Function 0 is a bit of an exception. */ - if (index == 0) { - index = 14; - } - - cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); - new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */ - if (!dev->enabled) { - new_disable_mask |= (1 << index); /* Disable it, if desired. */ - } - if (new_disable_mask != cur_disable_mask) { - pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); - } + reg16 = pci_read_config16(lpc_dev, FUNC_DIS); + reg16 &= ~(1 << index); /* Enable device. */ + if (!dev->enabled) + reg16 |= (1 << index); /* Disable device, if desired. */ + pci_write_config16(lpc_dev, FUNC_DIS, reg16); } struct chip_operations southbridge_intel_i82801bx_ops = { Modified: trunk/src/southbridge/intel/i82801bx/i82801bx.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx.h Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx.h Mon Oct 11 23:38:49 2010 (r5938) @@ -26,6 +26,13 @@ extern void i82801bx_enable(device_t dev); #endif +#define SMBUS_IO_BASE 0x0f00 +#define PMBASE_ADDR 0x0400 +#define GPIO_BASE_ADDR 0x0500 +#define HPET_ADDR 0xfed00000 + +#define SECSTS 0x1e + #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 #define GEN_CNTL 0xd0 @@ -34,11 +41,12 @@ #define GEN_PMCON_3 0xa4 #define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */ -#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */ +#define GPIO_BASE 0x58 /* GPIO Base Address Register */ +#define GPIO_CNTL 0x5C /* GPIO Control Register */ +#define GPIO_EN (1 << 4) #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 @@ -51,10 +59,10 @@ #define FUNC_DIS 0xF2 -#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ -#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ -#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ +#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */ +#define LPC_EN 0xE6 /* LPC IF Enables Register */ + +// TODO: FDC_DEC etc #define SBUS_NUM 0x19 #define SUB_BUS_NUM 0x1A @@ -67,8 +75,6 @@ #define MTT 0x70 #define PCI_MAST_STS 0x82 -#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ - #define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ @@ -77,14 +83,14 @@ #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -/* PCI Configuration Space (D31:F1) */ +/* IDE Timing registers (IDE_TIM) */ #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ /* IDE_TIM bits */ #define IDE_DECODE_ENABLE (1 << 15) -/* PCI Configuration Space (D31:F3) */ +/* SMbus */ #define SMB_BASE 0x20 #define HOSTC 0x40 @@ -93,13 +99,7 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* SMBus I/O bits. - * TODO: Does it matter where we put the SMBus IO base, as long as we keep - * consistent and don't interfere with anything else? - */ -/* #define SMBUS_IO_BASE 0x1000 */ -#define SMBUS_IO_BASE 0x0f00 - +/* SMBus I/O registers. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -114,8 +114,5 @@ #define SMBUS_TIMEOUT (10 * 1000 * 100) -/* HPET, if present */ -#define HPET_ADDR 0xfed00000 - #endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */ Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_ac97.c Mon Oct 11 23:38:49 2010 (r5938) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code should work for all ICH* southbridges with AC97 audio/modem. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -36,32 +34,6 @@ .enable = i82801bx_enable, }; -/* 82801AA (ICH) */ -static const struct pci_driver i82801aa_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO, -}; - -static const struct pci_driver i82801aa_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM, -}; - -/* 82801AB (ICH0) */ -static const struct pci_driver i82801ab_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO, -}; - -static const struct pci_driver i82801ab_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM, -}; - /* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_ac97_audio __pci_driver = { .ops = &ac97_ops, @@ -74,55 +46,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM, }; - -/* 82801CA/CAM (ICH3-S/ICH3-M) */ -static const struct pci_driver i82801ca_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO, -}; - -static const struct pci_driver i82801ca_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM, -}; - -/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ -static const struct pci_driver i82801db_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO, -}; - -static const struct pci_driver i82801db_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM, -}; - -/* 82801EB/ER (ICH5/ICH5R) */ -static const struct pci_driver i82801eb_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO, -}; - -static const struct pci_driver i82801eb_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM, -}; - -/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ -static const struct pci_driver i82801fb_ac97_audio __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO, -}; - -static const struct pci_driver i82801fb_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM, -}; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Mon Oct 11 23:38:49 2010 (r5938) @@ -29,19 +29,9 @@ device_t dev; uint16_t device_id; - /* Set the SMBus device statically. */ + /* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3); - /* Check to make sure we've got the right device. */ - device_id = pci_read_config16(dev, 0x2); - - /* Clear bits 7-4 (the only bits that vary between models). */ - device_id &= 0xff0f; - - if (device_id != 0x2403) { - die("Device not found, Corey probably screwed up!"); - } - /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_ide.c Mon Oct 11 23:38:49 2010 (r5938) @@ -31,34 +31,24 @@ static void ide_init(struct device *dev) { - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u16 reg16; + config_t *conf = dev->chip_info; - /* TODO: Needs to be tested for compatibility with ICH5(R). */ - /* Enable IDE devices so the Linux IDE driver will work. */ - uint16_t ideTimingConfig; - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide0_enable) { - /* Enable primary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide1_enable) { - /* Enable secondary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); + reg16 = pci_read_config16(dev, IDE_TIM_PRI); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide0_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_PRI, reg16); + + reg16 = pci_read_config16(dev, IDE_TIM_SEC); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide1_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_SEC, reg16); } static struct device_operations ide_ops = { @@ -70,51 +60,9 @@ .enable = i82801bx_enable, }; -/* 82801AA */ -static const struct pci_driver i82801aa_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2411, -}; - -/* 82801AB */ -static const struct pci_driver i82801ab_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2421, -}; - -/* 82801BA */ +/* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x244b, }; - -/* 82801CA */ -static const struct pci_driver i82801ca_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x248b, -}; - -/* 82801DB */ -static const struct pci_driver i82801db_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24cb, -}; - -/* 82801DBM */ -static const struct pci_driver i82801dbm_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24ca, -}; - -/* 82801EB & 82801ER */ -static const struct pci_driver i82801ex_ide __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24db, -}; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Mon Oct 11 23:38:49 2010 (r5938) @@ -21,8 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* From 82801DBM, needs to be fixed to support everything the 82801ER does. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -53,8 +51,10 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. + * + * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN) + * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above. + * 1 - The PIRQ is not routed to the 8259. */ #define PIRQA 0x03 @@ -71,7 +71,6 @@ * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. */ - static void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; @@ -81,14 +80,14 @@ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); @@ -118,60 +117,33 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) { - /* Get the chip configuration */ + u8 reg8; config_t *config = dev->chip_info; - if (config->pirqa_routing) { - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - } else { - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - } + reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA; + pci_write_config8(dev, PIRQA_ROUT, reg8); - if (config->pirqb_routing) { - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - } else { - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - } + reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB; + pci_write_config8(dev, PIRQB_ROUT, reg8); - if (config->pirqc_routing) { - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - } else { - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - } + reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC; + pci_write_config8(dev, PIRQC_ROUT, reg8); - if (config->pirqd_routing) { - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); - } else { - pci_write_config8(dev, PIRQD_ROUT, PIRQD); - } + reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD; + pci_write_config8(dev, PIRQD_ROUT, reg8); - /* Route PIRQE - PIRQH (for ICH2-ICH9). */ - if (ich_model >= 0x2440) { - if (config->pirqe_routing) { - pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); - } else { - pci_write_config8(dev, PIRQE_ROUT, PIRQE); - } - - if (config->pirqf_routing) { - pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); - } else { - pci_write_config8(dev, PIRQF_ROUT, PIRQF); - } - - if (config->pirqg_routing) { - pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); - } else { - pci_write_config8(dev, PIRQG_ROUT, PIRQG); - } - - if (config->pirqh_routing) { - pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); - } else { - pci_write_config8(dev, PIRQH_ROUT, PIRQH); - } - } + reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE; + pci_write_config8(dev, PIRQE_ROUT, reg8); + + reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF; + pci_write_config8(dev, PIRQF_ROUT, reg8); + + reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG; + pci_write_config8(dev, PIRQG_ROUT, reg8); + + reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH; + pci_write_config8(dev, PIRQH_ROUT, reg8); } static void i82801bx_power_options(device_t dev) @@ -208,7 +180,7 @@ { /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); + pci_write_config8(dev, GPIO_CNTL, GPIO_EN); } static void i82801bx_rtc_init(struct device *dev) @@ -252,15 +224,9 @@ * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. * We also need to set the value for LPC I/F Enables Register. - * Note: ICH-ICH5 registers differ from ICH6-ICH9. */ - if (ich_model <= 0x24D0) { - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F); - } else if (ich_model >= 0x2640) { - pci_write_config8(dev, LPC_IO_DEC, 0x10); - pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F); - } + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); } static void lpc_init(struct device *dev) @@ -332,45 +298,9 @@ .enable = i82801bx_enable, }; -static const struct pci_driver i82801aa_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2410, -}; - -static const struct pci_driver i82801ab_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2420, -}; - +/* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_lpc __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2440, }; - -static const struct pci_driver i82801ca_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2480, -}; - -static const struct pci_driver i82801db_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24c0, -}; - -static const struct pci_driver i82801dbm_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24cc, -}; - -/* 82801EB and 82801ER */ -static const struct pci_driver i82801ex_lpc __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x24d0, -}; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_nic.c Mon Oct 11 23:38:49 2010 (r5938) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code should work for all ICH* southbridges with a NIC. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -33,46 +31,9 @@ .scan_bus = 0, }; -/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */ - -/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */ +/* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_nic __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801BA_LAN, }; - -/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ -static const struct pci_driver i82801db_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_LAN, -}; - -/* 82801EB/ER (ICH5/ICH5R) */ -static const struct pci_driver i82801eb_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_LAN, -}; - -/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ -static const struct pci_driver i82801fb_nic __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_LAN, -}; - -/* 82801E (C-ICH) */ -static const struct pci_driver i82801e_nic1 __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801E_LAN1, -}; - -static const struct pci_driver i82801e_nic2 __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801E_LAN2, -}; - Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_pci.c Mon Oct 11 23:38:49 2010 (r5938) @@ -26,16 +26,16 @@ static void pci_init(struct device *dev) { - uint16_t reg16; + u16 reg16; /* Clear system errors */ - reg16 = pci_read_config16(dev, 0x06); + reg16 = pci_read_config16(dev, PCI_STATUS); reg16 |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, reg16); + pci_write_config16(dev, PCI_STATUS, reg16); - reg16 = pci_read_config16(dev, 0x1e); + reg16 = pci_read_config16(dev, SECSTS); reg16 |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, reg16); + pci_write_config16(dev, SECSTS, reg16); } static struct device_operations pci_ops = { @@ -46,27 +46,9 @@ .scan_bus = pci_scan_bridge, }; -static const struct pci_driver i82801aa_pci __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2418, -}; - -static const struct pci_driver i82801ab_pci __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2428, -}; - -/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */ +/* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801misc_pci __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x244e, }; - -static const struct pci_driver i82801dbm_pci __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2448, -}; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c Mon Oct 11 23:38:49 2010 (r5938) @@ -53,58 +53,9 @@ .ops_smbus_bus = &lops_smbus_bus, }; -/* 82801AA (ICH) */ -static const struct pci_driver i82801aa_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AA_SMB, -}; - -/* 82801AB (ICH0) */ -static const struct pci_driver i82801ab_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AB_SMB, -}; - /* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_smb __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801BA_SMB, }; - -/* 82801CA/CAM (ICH3-S/ICH3-M) */ -static const struct pci_driver i82801ca_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_SMB, -}; - -/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ -static const struct pci_driver i82801db_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_SMB, -}; - -/* 82801EB/ER (ICH5/ICH5R) */ -static const struct pci_driver i82801eb_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_SMB, -}; - -/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ -static const struct pci_driver i82801fb_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_SMB, -}; - -/* 82801E (C-ICH) */ -static const struct pci_driver i82801e_smb __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801E_SMB, -}; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c Mon Oct 11 21:36:13 2010 (r5937) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_usb.c Mon Oct 11 23:38:49 2010 (r5938) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code should work for all ICH* southbridges with USB. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -40,20 +38,6 @@ .enable = i82801bx_enable, }; -/* 82801AA (ICH) */ -static const struct pci_driver i82801aa_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AA_USB, -}; - -/* 82801AB (ICH0) */ -static const struct pci_driver i82801ab_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801AB_USB, -}; - /* 82801BA/BAM (ICH2/ICH2-M) */ static const struct pci_driver i82801ba_usb1 __pci_driver = { .ops = &usb_ops, @@ -66,98 +50,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801BA_USB2, }; - -/* 82801CA/CAM (ICH3-S/ICH3-M) */ -static const struct pci_driver i82801ca_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB1, -}; - -static const struct pci_driver i82801ca_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, -}; - -static const struct pci_driver i82801ca_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, -}; - -/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ -static const struct pci_driver i82801db_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_USB1, -}; - -static const struct pci_driver i82801db_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_USB2, -}; - -static const struct pci_driver i82801db_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_USB3, -}; - -/* 82801EB/ER (ICH5/ICH5R) */ -static const struct pci_driver i82801eb_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_USB1, -}; - -static const struct pci_driver i82801eb_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_USB2, -}; - -static const struct pci_driver i82801eb_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_USB3, -}; - -static const struct pci_driver i82801eb_usb4 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801EB_USB4, -}; - -/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */ -static const struct pci_driver i82801fb_usb1 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_USB1, -}; - -static const struct pci_driver i82801fb_usb2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_USB2, -}; - -static const struct pci_driver i82801fb_usb3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_USB3, -}; - -static const struct pci_driver i82801fb_usb4 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801FB_USB4, -}; - -/* 82801E (C-ICH) */ -static const struct pci_driver i82801e_usb __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801E_USB, -};

1 0

[commit] r5937 - in trunk/src: cpu/amd/sc520 devices include/device mainboard/emulation/qemu-x86 northbridge/amd/amdfam10 northbridge/amd/amdk8 northbridge/amd/gx1 northbridge/amd/gx2 northbridge/a...
by repository service 11 Oct '10

11 Oct '10

Author: uwe Date: Mon Oct 11 21:36:13 2010 New Revision: 5937 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5937 Log: Factor out a few commonly duplicated functions from northbridge.c. The following functions are moved to devices/device_util.c: - ram_resource() - tolm_test() - find_pci_tolm() There are only two tolm_test() / find_pci_tolm() which differ from the defaults, one of them can easily be eliminated in a follow-up patch, maybe even both, but for now keep it simple and only eliminate the majority. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/sc520/sc520.c trunk/src/devices/device_util.c trunk/src/include/device/device.h trunk/src/mainboard/emulation/qemu-x86/northbridge.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/gx1/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/intel/e7501/northbridge.c trunk/src/northbridge/intel/e7520/northbridge.c trunk/src/northbridge/intel/e7525/northbridge.c trunk/src/northbridge/intel/i3100/northbridge.c trunk/src/northbridge/intel/i440bx/northbridge.c trunk/src/northbridge/intel/i440lx/northbridge.c trunk/src/northbridge/intel/i82810/northbridge.c trunk/src/northbridge/intel/i82830/northbridge.c trunk/src/northbridge/intel/i855/northbridge.c trunk/src/northbridge/intel/i945/northbridge.c trunk/src/northbridge/via/cn400/northbridge.c trunk/src/northbridge/via/cn700/northbridge.c trunk/src/northbridge/via/cx700/northbridge.c trunk/src/northbridge/via/vt8601/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/northbridge.c Modified: trunk/src/cpu/amd/sc520/sc520.c ============================================================================== --- trunk/src/cpu/amd/sc520/sc520.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/cpu/amd/sc520/sc520.c Mon Oct 11 21:36:13 2010 (r5937) @@ -84,47 +84,6 @@ .device = 0x3000 }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - printk(BIOS_SPEW, "%s sizek 0x%lx\n", __func__, sizek); - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - printk(BIOS_SPEW, "%s\n", __func__); - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - printk(BIOS_SPEW, "%s returns 0x%x\n", __func__, tolm); - return tolm; -} - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; Modified: trunk/src/devices/device_util.c ============================================================================== --- trunk/src/devices/device_util.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/devices/device_util.c Mon Oct 11 21:36:13 2010 (r5937) @@ -730,3 +730,47 @@ show_one_resource(debug_level, dev, res, ""); } } + +void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) + return; + + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + + best = *best_p; + + if (!best || (best->base > new->base)) + best = new; + + *best_p = best; +} + +u32 find_pci_tolm(struct bus *bus) +{ + struct resource *min = NULL; + u32 tolm; + + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, + tolm_test, &min); + + tolm = 0xffffffffUL; + + if (min && tolm > min->base) + tolm = min->base; + + return tolm; +} Modified: trunk/src/include/device/device.h ============================================================================== --- trunk/src/include/device/device.h Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/include/device/device.h Mon Oct 11 21:36:13 2010 (r5937) @@ -146,4 +146,10 @@ void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); unsigned int scan_static_bus(device_t bus, unsigned int max); + +void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek); +void tolm_test(void *gp, struct device *dev, struct resource *new); +u32 find_pci_tolm(struct bus *bus); + #endif /* DEVICE_H */ Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -9,45 +9,6 @@ #include "chip.h" #include <delay.h> -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -689,33 +689,7 @@ #endif } -static void ram_resource(device_t dev, unsigned long index, - resource_t basek, resource_t sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = basek << 10; - resource->size = sizek << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus, u32 tolm) +static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) { struct resource *min; min = 0; @@ -951,7 +925,7 @@ pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link, pci_tolm); + pci_tolm = my_find_pci_tolm(link, pci_tolm); } // FIXME handle interleaved nodes. If you fix this here, please fix Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -646,22 +646,7 @@ #endif } -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) +static void my_tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; struct resource *best; @@ -673,12 +658,12 @@ *best_p = best; } -static u32 find_pci_tolm(struct bus *bus) +static u32 my_find_pci_tolm(struct bus *bus) { struct resource *min; u32 tolm; min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, my_tolm_test, &min); tolm = 0xffffffffUL; if (min && tolm > min->base) { tolm = min->base; @@ -915,7 +900,7 @@ } #endif - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = my_find_pci_tolm(dev->link_list); // FIXME handle interleaved nodes. If you fix this here, please fix // amdfam10, too. Modified: trunk/src/northbridge/amd/gx1/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx1/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/amd/gx1/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -66,45 +66,6 @@ .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/amd/gx2/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -350,47 +350,6 @@ .device = PCI_DEVICE_ID_NS_GX2, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -#if 0 -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min; - u32 tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} -#endif - // FIXME handle UMA correctly. #define FRAMEBUFFERK 4096 Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/amd/lx/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -372,21 +372,6 @@ .device = PCI_DEVICE_ID_AMD_LXBRIDGE, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/e7501/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7501/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/e7501/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -9,45 +9,6 @@ #include <bitops.h> #include "chip.h" -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/e7520/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7520/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/e7520/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -16,42 +16,6 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/e7525/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7525/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/e7525/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -16,42 +16,6 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/i3100/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i3100/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i3100/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -37,42 +37,6 @@ static u32 max_bus; -static void ram_resource(device_t dev, u32 index, - u32 basek, u32 sizek) -{ - struct resource *resource; - - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min; - u32 tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/i440bx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i440bx/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -33,45 +33,6 @@ .device = 0x7190, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/i440lx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i440lx/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -18,6 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -61,45 +62,6 @@ .device = 0x7180, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/i82810/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i82810/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -62,46 +62,6 @@ .device = 0x7124, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, - &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - /* IGD UMA memory */ uint64_t uma_memory_base=0, uma_memory_size=0; Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i82830/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -52,43 +52,6 @@ .device = 0x3575, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) - best = new; - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, - &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) - tolm = min->base; - return tolm; -} - /* IGD memory */ uint64_t uma_memory_base=0, uma_memory_size=0; Modified: trunk/src/northbridge/intel/i855/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i855/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i855/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -53,45 +53,6 @@ .device = 0x3580, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/intel/i945/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i945/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/intel/i945/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -92,43 +92,6 @@ } } -static void ram_resource(device_t dev, unsigned long index, unsigned long basek, - unsigned long sizek) -{ - struct resource *resource; - - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, - &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; Modified: trunk/src/northbridge/via/cn400/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn400/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/cn400/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -161,20 +161,6 @@ printk(BIOS_SPEW, "Leaving %s.\n", __func__); } -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - resource = new_resource(dev, index); - resource->base = (resource_t) (basek << 10); - resource->size = (resource_t) (sizek << 10); - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - #ifdef UNUSED_CODE static void ram_reservation(device_t dev, unsigned long index, unsigned long base, unsigned long size) @@ -191,35 +177,6 @@ } #endif -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - - best = *best_p; - if (!best || (best->base > new->base)) - best = new; - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min = NULL; - u32 tolm; - - printk(BIOS_SPEW, "Entering CN400 find_pci_tolm\n"); - - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) - tolm = min->base; - - printk(BIOS_SPEW, "Leaving CN400 find_pci_tolm\n"); - - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 Modified: trunk/src/northbridge/via/cn700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn700/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/cn700/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -97,51 +97,6 @@ .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - - best = *best_p; - if (!best || (best->base > new->base)) - best = new; - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min; - u32 tolm; - - print_debug("Entering find_pci_tolm\n"); - - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) - tolm = min->base; - - print_debug("Leaving find_pci_tolm\n"); - - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 Modified: trunk/src/northbridge/via/cx700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/cx700/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -32,46 +32,6 @@ #include "chip.h" #include "northbridge.h" -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min = NULL; - u32 tolm; - - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 Modified: trunk/src/northbridge/via/vt8601/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8601/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/vt8601/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -45,45 +45,6 @@ .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/vt8623/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -105,45 +105,6 @@ .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - #if CONFIG_WRITE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 Modified: trunk/src/northbridge/via/vx800/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.c Mon Oct 11 00:05:02 2010 (r5936) +++ trunk/src/northbridge/via/vx800/northbridge.c Mon Oct 11 21:36:13 2010 (r5937) @@ -74,48 +74,6 @@ .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, }; -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - print_debug("Entering find_pci_tolm\n"); - struct resource *min; - u32 tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - print_debug("Leaving find_pci_tolm\n"); - return tolm; -} - static void pci_domain_set_resources(device_t dev) { /*

1 0

← Newer
1
...
17
18
19
20
21
22
23
...
32
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2010