coreboot October 2010

coreboot@coreboot.org

55 participants
316 discussions

Where does printk() message go in coreboot source code
by fengwei zhang 14 Oct '10

14 Oct '10

Hi, I am new to coreboot. Do you guys know where printk() statement go in coreboot source code? e.g. printk(BIOS_DEBUG, "%s\n", msg); Thank you very much! Best, Fengwei

3 2

Re: [coreboot] CarPC project, with MB899 MB
by Peter Stuge 14 Oct '10

14 Oct '10

Nasa wrote: > > Did you pick a particular CPU for the board, or did the CPU come > > already installed when you bought the board? .. > I choose the CPU (a number of years ago) which is an Intel Core 2 > Duo Mobile 1.66GHz. Ok. I don't know if this CPU has been tested with coreboot, but even so it is possible that it will just work<tm>. You should give it a go. > I have read a little about payloads and noted that SeaBIOS would be > the easiest way to go... However (this being important for the > flash chip), I didn't see anything about the benefits of putting a > linux kernel as a payload. Benefits are that fewer steps are required to boot the system, so with the kernel in boot flash you can immediately access the root filesystem regardless of where it is stored. > I did read from the FAQ that most chips aren't large enough to have > the kernel added as a payload. The FAQ needs some updates. I guess "most" chips still aren't large enough for a kernel, but those 16Mbit chips should be able to hold a monolithic kernel optimized for a single board. > If my goal is the fastest boot time possible, while still > supporting the basic system, would going to a Linux payload be the > way to go? Maybe, but maybe not. If you are using flash media which does not have a spin-up delay then it might actually be faster for another payload to load the kernel off the drive using DMA. > If so, what size flash chip should I get? The larger the better IMO. There can be a chipset limit for the flash chip size, but I don't know what it is for i945 chipsets. In any case a larger flash chip will still be usable, just at e.g. half capacity. > BTW: once I get this working, it's going up on the carpc forum -- I > know a lot of people would be interested in reducing their systems > boot time. Yes. It's also the first thing I used coreboot for myself. Please mention that it is very important for people to check if their mainboard and/or CPU+chipset is already supported, otherwise they are looking at rather large projects of studying PC architecture and developing lots of low-level code to implement that support. An unsupported mainboard with a supported CPU+chipset is much less effort though, and could best case be just a few days-few weeks project for a C programmer. For new installs of course hardware known to be coreboot confirmed would be best. :) //Peter

2 2

coreboot support for AMD HT3
by Scott Duplichan 14 Oct '10

14 Oct '10

Hello, I am having trouble getting high resolution UMA graphics modes to work on my RS780/SB700 system. I am using coreboot project mahogany_fam10. EDID is working. Both VGA and DVI connections have the problem. At 1600x1200, 16-bit color is almost perfect. But the same resolution with 32-bit color results in a display that jumps so much it cannot be read. Why would 32-bit color make a difference? I am thinking that refreshing 1600x1200 pixels 60 times per second takes a lot data, and that data has to cross the HT link. True color takes more data than high color, and true color may be exceeding the capacity of the cpu-RS780 link. The link is running at the slowest possible setting, 200 MHz, 8-bit. Question: I see all the code in place for HT3. What is the status of coreboot support for AMD HT3? Thanks, Scott

2 1

LANL in the news (sort of)
by Gregg Levine 14 Oct '10

14 Oct '10

Hello! I had first heard about the Utah facility when I had started exploring the logic behind how to network boot a computer. Yes this includes http://etherboot.org/ as well as the netboot project as well. (Which is at http://netboot.sourceforge.net/ ) The home page for the whole business is at http://www.cs.utah.edu/flux/index.html . They had created a blob called OS-Kit to enable the idea of building a something-or-other to do something else. It was about the same time Ron, that I came across the work you were doing with the original site for this business, and its name LinuxBIOS. On the whole I prefer CoreBoot as it means we're past those early days. The site in question is here https://www.emulab.net/news.php3?single=243 EmuLab is as it name implies an emulation of everything the Internet suggests, a big congested delivery method. And they enable people to study why that happens. I have an account with them, but as of several months previously its not an active one. I suspect they find my ideas as strange was Linux when Linus was first developing his great idea. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

1 0

[commit] r5951 - in trunk/src: mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/ecs/p6iwp-fe mainboard/hp/e_vectra_p2706t mainboard/intel/d810e2cb mainboard/mitac/6513wu mainboard/msi/ms6178 m...
by repository service 14 Oct '10

14 Oct '10

Author: uwe Date: Thu Oct 14 01:00:41 2010 New Revision: 5951 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5951 Log: Remove various .c #includes from Intel i810/i82801ax/i82801bx boards. This is pretty much the same mechanism as in r5929. - Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for northbridge/intel/i82810/raminit.c, and northbridge/intel/i82810/debug.c. - Add various header files which are now needed, drop unused includes. - Make functions that need to be visible non-static. Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/mew-am/romstage.c trunk/src/mainboard/asus/mew-vm/romstage.c trunk/src/mainboard/ecs/p6iwp-fe/romstage.c trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c trunk/src/mainboard/intel/d810e2cb/romstage.c trunk/src/mainboard/mitac/6513wu/romstage.c trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/nec/powermate2000/romstage.c trunk/src/northbridge/intel/i82810/Makefile.inc trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/i82810.h trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h trunk/src/southbridge/intel/i82801ax/Makefile.inc trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h trunk/src/southbridge/intel/i82801bx/Makefile.inc trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Modified: trunk/src/mainboard/asus/mew-am/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-am/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/asus/mew-am/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,22 +23,20 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -46,7 +44,7 @@ console_init(); report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/mainboard/asus/mew-vm/romstage.c ============================================================================== --- trunk/src/mainboard/asus/mew-vm/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/asus/mew-vm/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,23 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" -#include "lib/debug.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "northbridge/intel/i82810/raminit.c" -#include "northbridge/intel/i82810/debug.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/ecs/p6iwp-fe/romstage.c ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/ecs/p6iwp-fe/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -24,20 +24,18 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -#include "northbridge/intel/i82810/debug.c" #include <lib.h> +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { it8712f_24mhz_clkin(); Modified: trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c ============================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/hp/e_vectra_p2706t/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -31,15 +31,16 @@ /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/debug.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h> /* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* TODO: It's a PC87364 actually! */ @@ -48,7 +49,7 @@ console_init(); enable_smbus(); report_bist_failure(bist); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/intel/d810e2cb/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,24 +23,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "southbridge/intel/i82801bx/i82801bx.h" -#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" -#include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ @@ -52,7 +49,7 @@ report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/mainboard/mitac/6513wu/romstage.c ============================================================================== --- trunk/src/mainboard/mitac/6513wu/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/mitac/6513wu/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -23,22 +23,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "northbridge/intel/i82810/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" -#include "northbridge/intel/i82810/raminit.c" -/* #include "northbridge/intel/i82810/debug.c" */ #include <lib.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -47,7 +46,7 @@ report_bist_failure(bist); enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/msi/ms6178/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,21 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "lib/debug.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { /* FIXME */ @@ -48,12 +48,9 @@ uart_init(); console_init(); - enable_smbus(); - report_bist_failure(bist); - - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/mainboard/nec/powermate2000/romstage.c ============================================================================== --- trunk/src/mainboard/nec/powermate2000/romstage.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/mainboard/nec/powermate2000/romstage.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,20 +22,21 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" +#include "southbridge/intel/i82801ax/i82801ax.h" #include "pc80/udelay_io.c" -#include "northbridge/intel/i82810/raminit.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -43,7 +44,7 @@ console_init(); enable_smbus(); report_bist_failure(bist); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); Modified: trunk/src/northbridge/intel/i82810/Makefile.inc ============================================================================== --- trunk/src/northbridge/intel/i82810/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -20,3 +20,6 @@ driver-y += northbridge.c +romstage-y += raminit.c +romstage-y += debug.c + Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/debug.c Thu Oct 14 01:00:41 2010 (r5951) @@ -1,4 +1,6 @@ -static void dump_spd_registers(void) +#include "raminit.h" + +void dump_spd_registers(void) { #if CONFIG_DEBUG_RAM_SETUP int i; Modified: trunk/src/northbridge/intel/i82810/i82810.h ============================================================================== --- trunk/src/northbridge/intel/i82810/i82810.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/i82810.h Thu Oct 14 01:00:41 2010 (r5951) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef NORTHBRIDGE_INTEL_I82810_I82810_H +#define NORTHBRIDGE_INTEL_I82810_I82810_H + /* * Datasheet: * - Name: Intel 810 Chipset: @@ -43,3 +46,7 @@ #define MISSC 0x72 /* Miscellaneous Control */ #define MISSC2 0x80 /* Miscellaneous Control 2 */ #define BUFF_SC 0x92 /* System Memory Buffer Strength Control */ + +int smbus_read_byte(u8 device, u8 address); + +#endif Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/raminit.c Thu Oct 14 01:00:41 2010 (r5951) @@ -22,7 +22,13 @@ #include <spd.h> #include <delay.h> +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> #include "i82810.h" +#include "raminit.h" /*----------------------------------------------------------------------------- Macros and definitions. @@ -421,7 +427,7 @@ Public interface. -----------------------------------------------------------------------------*/ -static void sdram_set_registers(void) +void sdram_set_registers(void) { u8 reg8; u16 did; @@ -454,7 +460,7 @@ pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8); } -static void sdram_set_spd_registers(void) +void sdram_set_spd_registers(void) { spd_set_dram_size(); set_dram_buffer_strength(); @@ -464,7 +470,7 @@ /** * Enable SDRAM. */ -static void sdram_enable(void) +void sdram_enable(void) { int i; Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/northbridge/intel/i82810/raminit.h Thu Oct 14 01:00:41 2010 (r5951) @@ -27,4 +27,10 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50 -#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */ +/* Function prototypes. */ +void sdram_set_registers(void); +void sdram_set_spd_registers(void); +void sdram_enable(void); +void dump_spd_registers(void); + +#endif Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801ax/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -29,3 +29,5 @@ ramstage-y += i82801ax_reset.c ramstage-y += i82801ax_watchdog.c +romstage-y += i82801ax_early_smbus.c + Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Thu Oct 14 01:00:41 2010 (r5951) @@ -20,11 +20,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801ax.h" #include "i82801ax_smbus.h" -static void enable_smbus(void) +int smbus_read_byte(u8 device, u8 address); + +void enable_smbus(void) { device_t dev; @@ -50,7 +56,7 @@ print_debug("SMBus controller enabled\n"); } -static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Thu Oct 14 01:00:41 2010 (r5951) @@ -20,6 +20,9 @@ #include <device/smbus_def.h> +void enable_smbus(void); +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address); + static void smbus_delay(void) { inb(0x80); @@ -51,8 +54,7 @@ return loops ? 0 : -1; } -static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, - unsigned address) +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) { unsigned char global_status_register; unsigned char byte; Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Makefile.inc Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/Makefile.inc Thu Oct 14 01:00:41 2010 (r5951) @@ -30,3 +30,5 @@ ramstage-y += i82801bx_reset.c ramstage-y += i82801bx_watchdog.c +romstage-y += i82801bx_early_smbus.c + Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Thu Oct 14 01:00:41 2010 (r5951) @@ -20,11 +20,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801bx.h" #include "i82801bx_smbus.h" -static void enable_smbus(void) +int smbus_read_byte(u8 device, u8 address); + +void enable_smbus(void) { device_t dev; @@ -50,7 +56,7 @@ print_debug("SMBus controller enabled\n"); } -static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Wed Oct 13 19:00:42 2010 (r5950) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Thu Oct 14 01:00:41 2010 (r5951) @@ -20,6 +20,8 @@ #include <device/smbus_def.h> +void enable_smbus(void); + static void smbus_delay(void) { inb(0x80); @@ -51,8 +53,7 @@ return loops ? 0 : -1; } -static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, - unsigned address) +static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) { unsigned char global_status_register; unsigned char byte;

1 0

Re: [coreboot] CarPC project, with MB899 MB
by Nasa 14 Oct '10

14 Oct '10

----- "Peter Stuge" <peter(a)stuge.se> wrote: > Nasa wrote: > > All that said, I was hoping to get pointed in the right direction > > to being able to install this in my motherboard. The specifics of > > the board (in case I misread the post) are(from manual): > > > > IBASE MB899 > > Intel 945GM Chipset > > GMCH: 82945GM 1466-pin Micro-FCBGA > > ICH7M:82801GBM 652-pin MBGA. > > Did you pick a particular CPU for the board, or did the CPU come > already installed when you bought the board? > > In general you're in luck because as was noted the board is supported > by coreboot. > > You will need a few things: > > * Cross-over serial cable (AKA null modem) > * Spare boot flash chips > * Patience > > You have to choose a payload for your coreboot build. coreboot does > hardware init but does not include any code to boot your operating > system. That second part is handled by a completely separate program, > which is stored together with coreboot in the boot flash. > > An easy first step might be to use SeaBIOS as payload. SeaBIOS is an > open source legacy BIOS implementation, so your system should start > just like before. Once everything is running well with > coreboot+SeaBIOS you could move on and try to optimize the boot even > further, using other payloads. > > > > While I am very capable of building software out of SVN (been doing > > that for mythtv, openmobile, etc) and linux kernel, > > Good. Note that coreboot and SeaBIOS both run before an operating > system environment is available, and the toolchains shipped with many > distributions have been patched so that they fail to correctly build > such software. You can try using your regular toolchain, but if you > have any trouble then it is recommended to build a reference > toolchain and use that to build coreboot. After svn checkout of the > coreboot tree, do: > > cd util/crossgcc > ./buildgcc > cd ../.. > rm -f .xcompile > > The next time you run make in the coreboot directory it should pick > up the toolchain built by buildgcc automatically. Check the contents > of .xcompile to make sure. > > > > I have not played with pulling individual chips, like a BIOS. So I > > don't know anything about acquiring and/or replacing one. > > Note that BIOS is the software, not so much the flash chip it is > stored in. > > You will need replacement flash chips. They shouldn't cost more than > a few USD and I recommend getting a few of them, so that you always > have at least one backup of the factory BIOS that you can use if > coreboot doesn't work straight away. (Sometimes it will, but better > safe than sorry, if there's a problem you can't start the system > anymore without a backup flash chip.) > > > Warren Turkal wrote: > > the bios chip might be the SST thing near the white connector in > > the bottom left quadrant of the board. > > Yes, that's correct. This package is called PLCC32, but only > describes the physical format of the chip. > > > > I think it's an LPC style chip. > > Well, almost. It is connected to a bus which is electrically and > protocol-wise compatible with LPC, but all Intel chipsets use their > own memory read and write commands which are different from the LPC > standard commands. The flash chip type is usually called FWH, > Firmware Hub, since that is the name of Intel's own boot flash chips. > > Look for a couple of compatible flash chips. Some current part > numbers are: > > 8Mbit = 1Mbyte > SST49LF008A-33-4C-NHE > http://parts.digikey.com/1/parts/1904170-ic-flash-fwh-8mbit-33mhz-32plcc-ss… > > 16Mbit = 2Mbyte > SST49LF016C-33-4C-NHE > SST49LF016C-66-4C-NHE > http://parts.digikey.com/1/parts/1904173-ic-flash-ser-lpc-16mbit-32plcc-sst… > > > You can most likely use flashrom (flashrom.org, coreboot sibling > project) to read the factory BIOS from the chip in a running system. > You can then hotswap flash chips (prepare them with pushpin knobs > first) in the running system, put a blank chip in, and write your > first factory BIOS backup onto that. Then get the third flash chip, > repeat the hotswap, and write a coreboot image with SeaBIOS onto > that chip. Reboot and watch the seral port output on another > computer, via the null modem cable. > > > //Peter Wow, Thanks a lot Peter -- that was VERY informative. I choose the CPU (a number of years ago) which is an Intel Core 2 Duo Mobile 1.66GHz. I have read a little about payloads and noted that SeaBIOS would be the easiest way to go... However (this being important for the flash chip), I didn't see anything about the benefits of putting a linux kernel as a payload. I did read from the FAQ that most chips aren't large enough to have the kernel added as a payload. If my goal is the fastest boot time possible, while still supporting the basic system, would going to a Linux payload be the way to go? If so, what size flash chip should I get? Thanks Again for the SWEET email. Nasa BTW: once I get this working, it's going up on the carpc forum -- I know a lot of people would be interested in reducing their systems boot time.

1 0

Re: [coreboot] CarPC project, with MB899 MB
by Warren Turkal 13 Oct '10

13 Oct '10

On Wednesday, October 13, 2010 06:10:45 am Nasa wrote: *snip* > IBASE MB899 > Intel 945GM Chipset > GMCH: 82945GM 1466-pin Micro-FCBGA > ICH7M:82801GBM 652-pin MBGA. I just looked in our tree and I see src/mainboard/mb899. Anyone know how well it's supported? > While I am very capable of building software out of SVN (been doing that > for mythtv, openmobile, etc) and linux kernel, I have not played with > pulling individual chips, like a BIOS. So I don't know anything about > acquiring and/or replacing one. But I can be somewhat adventureous... Is the following your board? http://www.ibase.com.tw/MB899_500.jpg If so, the bios chip might be the SST thing near the white connector in the bottom left quadrant of the board. I think it's an LPC style chip. Having another chip to flash instead of that one would mean that you could keep your oringinal untouched. I think that usually those types of chips just pull right out. Also, having an external flasher would be really useful in case you flash a bad image onto your chip and need to fix it. wt

3 2

[PATCH] Split model_67x CPU support from model_6xx, with microcode / L2 cache code question
by Keith Hui 13 Oct '10

13 Oct '10

On Tue, Oct 12, 2010 at 7:23 PM, Uwe Hermann <uwe(a)hermann-uwe.de> wrote: > Can you post an extra patch for splitting off CPUs to make it easier to > review? The last one was merged into the already huge L2 patch which > made it really hard to read. > And you shall receive, in small delicious pieces. :D Attached patch adds support for Katmai Slot 1 CPUs (model_67x). abuild-tested. Boot tested on P2B-LS. Signed-off-by: Keith Hui <buurin(a)gmail.com> Similar patch for Deschutes(65x) and Klamath (63x) to come, but I need someone else to boot test them. > After the split, your L2 patch should be relatively small and clean, > please repost that too then. As we already know the L2 patch is a huge chunk of code, so let's figure out where best to place that code. It is specific to 63x,65x and 67x CPUs. There are some small code path differences between these CPU families. I'm trying to minimize duplication; if these code can be put in one .c file and be linked from a few other places, that's how I'd prefer it. Thanks Keith

3 3

Re: [coreboot] CarPC project, with MB899 MB
by Myles Watson 13 Oct '10

13 Oct '10

>> If so, the bios chip might be the SST thing near the white connector >> in the >> bottom left quadrant of the board. I think it's an LPC style chip. >> Having >> another chip to flash instead of that one would mean that you could >> keep your >> oringinal untouched. I think that usually those types of chips just >> pull right >> out. > > If that one does just pull out; could I make a copy of the running bios, > pull the chip (from a running machine...), and copy the old bios on to > the new chip? http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools Push pin flash is my favorite method. Thanks, Myles

1 0

Re: [coreboot] CarPC project, with MB899 MB
by Myles Watson 13 Oct '10

13 Oct '10

1 0

← Newer
1
...
14
15
16
17
18
19
20
...
32
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2010