coreboot October 2010

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[commit] r5946 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 13 Oct '10

13 Oct '10

Author: zbao Date: Wed Oct 13 04:46:59 2010 New Revision: 5946 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5946 Log: Trivial. Clean up code and add some comments. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Wed Oct 13 01:22:08 2010 (r5945) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Wed Oct 13 04:46:59 2010 (r5946) @@ -415,7 +415,7 @@ u16 i; buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - if (pDCTstat->Status & (1<<SB_128bitmode)) { + if (pDCTstat->Status & (1 << SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ for (i=0; i<16*18; i++) buf[i] = TestPatternJD1b_D[i]; @@ -489,9 +489,9 @@ print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ - if (pDCTstat->Direction==DQS_READDIR) { + if (pDCTstat->Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); + WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); } for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { @@ -504,12 +504,12 @@ if (pDCTstat->Direction == DQS_WRITEDIR) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); + WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); } print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); - ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); -// print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); + ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); + /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */ if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) { @@ -520,14 +520,13 @@ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 \tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO_D(TestAddr); - FlushDQSTestPattern_D(pDCTstat, TestAddr<<8); + FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); ResetTargetWTIO_D(); } } if (BanksPresent) { - u8 mask_pass = 0; for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); pDCTstat->ByteLane = ByteLane; @@ -556,7 +555,7 @@ } print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); if (RnkDlySeqPassMax == 0) { - Errors |= 1<<SB_NODQSPOS; /* no passing window */ + Errors |= 1 << SB_NODQSPOS; /* no passing window */ } else { print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4); if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)){ @@ -572,7 +571,6 @@ } } } - print_debug_dqs("\t\t\t\tTrainDQSPos: 41 mask_pass ",mask_pass, 3); } skipLocMiddle: pDCTstat->TrainErrors = Errors; @@ -779,19 +777,19 @@ if (pattern && channel) { addr_lo += 8; //second channel - test_buf+= 2; + test_buf += 2; } - bytelane = 0; - bitmap = 0xFF; - for (i=0; i < (9 * 64 / 4); i++) { /* /4 due to next loop */ + bytelane = 0; /* bytelane counter */ + bitmap = 0xFF; /* bytelane test bitmap, 1=pass */ + for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); value_test = *test_buf; print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", value_test, 7); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", value, 7); - for (j = 0; j < (4 * 8); j += 8) { + for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */ if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) { bitmap &= ~(1 << bytelane); } @@ -889,7 +887,7 @@ hi = addr_hi>>24; addr = FS_Base; _WRMSR(addr, lo, hi); - return addr_hi<<8; + return addr_hi << 8; } @@ -1021,7 +1019,7 @@ } /* get the proper register index */ - shift = ByteLane%4; + shift = ByteLane % 4; shift <<= 3; /* get bit position of bytelane, 8 bit */ if (pDCTstat->Status & (1 << SB_Over400MHz)) { @@ -1222,5 +1220,5 @@ SetUpperFSbase(addr); /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr<<8); + value = read32_fs(addr << 8); } Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Wed Oct 13 01:22:08 2010 (r5945) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Wed Oct 13 04:46:59 2010 (r5946) @@ -491,9 +491,9 @@ print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4); SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */ - if (pDCTstat->Direction==DQS_READDIR) { + if (pDCTstat->Direction == DQS_READDIR) { print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); + WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); } for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { @@ -517,12 +517,12 @@ if (pDCTstat->Direction == DQS_WRITEDIR) { print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5); - WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); + WriteDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); } print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5); - ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr<<8); -/* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ + ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); + /* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */ word = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 compare 1 ", word, 3); @@ -541,7 +541,7 @@ print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 \tMutualCSPassW ", MutualCSPassW[DQSDelay], 5); SetTargetWTIO_D(TestAddr); - FlushDQSTestPattern_D(pDCTstat, TestAddr<<8); + FlushDQSTestPattern_D(pDCTstat, TestAddr << 8); ResetTargetWTIO_D(); } @@ -552,7 +552,6 @@ } if (BanksPresent) { - u8 mask_pass = 0; for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); if (!(pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane))) { @@ -602,7 +601,7 @@ } print_debug_dqs("\t\t\t\tTrainDQSPos: 33 RnkDlySeqPassMax ", RnkDlySeqPassMax, 4); if (RnkDlySeqPassMax == 0) { - Errors |= 1<<SB_NODQSPOS; /* no passing window */ + Errors |= 1 << SB_NODQSPOS; /* no passing window */ } else { print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4); if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)){ @@ -624,9 +623,8 @@ pDCTstat->DqsRdWrPos_Saved |= 1 << ByteLane; } } - } /* if (pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane)) */ - } - print_debug_dqs("\t\t\t\tTrainDQSPos: 41 mask_pass ",mask_pass, 3); + } + } /* if (pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane)) */ } /* skipLocMiddle: */ pDCTstat->TrainErrors = Errors; @@ -850,14 +848,14 @@ if (pattern && channel) { addr_lo += 8; /* second channel */ - test_buf+= 2; + test_buf += 2; } - bytelane = 0; - bitmap = 0xFFFF; + bytelane = 0; /* bytelane counter */ + bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */ MEn1Results = 0xFFFF; BeatCnt = 0; - for (i=0; i < (9 * 64 / 4); i++) { /* /4 due to next loop */ + for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */ value = read32_fs(addr_lo); value_test = *test_buf; @@ -867,7 +865,7 @@ if (pDCTstat->Direction == DQS_READDIR) { if (BeatCnt != 0) { value_r = *test_buf; - if (pattern) + if (pattern) /* if multi-channel */ value_r_test = read32_fs(addr_lo - 16); else value_r_test = read32_fs(addr_lo - 8); @@ -876,7 +874,7 @@ print_debug_dqs_pair("\t\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value_r = ", value_r_test, 7); } - for (j = 0; j < (4 * 8); j += 8) { + for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */ if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) { bitmap &= ~(1 << bytelane); } @@ -900,7 +898,7 @@ if (bytelane == 0){ BeatCnt += 4; - if (!(pDCTstat->Status & (1 <<SB_128bitmode))) { + if (!(pDCTstat->Status & (1 << SB_128bitmode))) { if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */ } else { if (BeatCnt == 4) BeatCnt = 0; /* 4 beat burst */ @@ -990,7 +988,7 @@ hi = addr_hi>>24; addr = FS_Base; _WRMSR(addr, lo, hi); - return addr_hi<<8; + return addr_hi << 8; } void ResetDCTWrPtr_D(u32 dev, u32 index_reg, u32 index) @@ -1079,6 +1077,9 @@ } } +/* + * Set DQS delay value to related register + */ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel) { @@ -1107,7 +1108,7 @@ } /* get the proper register index */ - shift = ByteLane%4; + shift = ByteLane % 4; shift <<= 3; /* get bit position of bytelane, 8 bit */ index += (ChipSel>>1) << 8; @@ -1126,6 +1127,10 @@ } } +/* + * mct_SetDQSDelayAllCSR_D: + * Write the Delay value to all eight byte lanes. + */ static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 cs_start) @@ -1307,5 +1312,5 @@ SetUpperFSbase(addr); /* 1st move causes read fill (to exclusive or shared)*/ - value = read32_fs(addr<<8); + value = read32_fs(addr << 8); }

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Slot 1 regression! Asus P2B/P3B boards no longer boots with model_6bx CPUs
by Keith Hui 13 Oct '10

13 Oct '10

Guys, I could no longer boot my P3B-F with my Tualeron and r5938. Dies with "unknown CPU". I believe it will happen with any Slot 1 440BX boards that supports model_6bx CPUs. I need to make the change below to make it work. abuild tested. Boot tested on P2B-LS and P3B-F. After we split the rest of the P6 family from model_6xx, a similar change will need to be made here. Signed-off-by: Keith Hui <buurin(a)gmail.com> 8<------------------------- Index: Makefile.inc =================================================================== --- Makefile.inc (revision 5938) +++ Makefile.inc (working copy) @@ -20,6 +20,7 @@ ramstage-y += slot_1.c subdirs-y += ../model_6xx +subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic

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[commit] r5945 - trunk/src/cpu/intel/slot_1
by repository service 13 Oct '10

13 Oct '10

Author: uwe Date: Wed Oct 13 01:22:08 2010 New Revision: 5945 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5945 Log: Add missing include of model_6bx for slot_1. I could no longer boot my P3B-F with my Tualeron and r5938. Dies with "unknown CPU". I believe it will happen with any Slot 1 440BX boards that supports model_6bx CPUs. I need to make the change below to make it work. abuild tested. Boot tested on P2B-LS and P3B-F. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/intel/slot_1/Makefile.inc Modified: trunk/src/cpu/intel/slot_1/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/slot_1/Makefile.inc Tue Oct 12 23:37:03 2010 (r5944) +++ trunk/src/cpu/intel/slot_1/Makefile.inc Wed Oct 13 01:22:08 2010 (r5945) @@ -20,6 +20,7 @@ ramstage-y += slot_1.c subdirs-y += ../model_6xx +subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic

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[PATCH] Drop nrv2b support from coreboot
by Uwe Hermann 13 Oct '10

13 Oct '10

Please correct me if I'm wrong, but it looks like noone uses or cares about nrv2b, we use LZMA since quite a while now, so let's drop nrv2b. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r5944 - trunk/src/northbridge/intel/i82810
by repository service 12 Oct '10

12 Oct '10

Author: uwe Date: Tue Oct 12 23:37:03 2010 New Revision: 5944 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5944 Log: Move translate_spd_to_i82810[] from .h to .c file (trivial). This is in preparation of further i810 fixes and switching it to CAR. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Tue Oct 12 19:34:08 2010 (r5943) +++ trunk/src/northbridge/intel/i82810/raminit.c Tue Oct 12 23:37:03 2010 (r5944) @@ -58,6 +58,60 @@ #define RAM_COMMAND_CBR 0x7 /* CBR */ /* + * This table is used to translate the value read from SPD Byte 31 to a value + * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most + * northbridges have some sort of simple calculation that can be done for this, + * I haven't yet figured out one for this northbridge. Until someone does, + * this table is necessary. + */ +static const u8 translate_spd_to_i82810[] = { + /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB + * side can't be either, at least for now. + */ + /* TODO: For above case, only use the other side if > 4MB, and get some + * of these DIMMs to test it with. Same for unsupported 128/x sizes. + */ + + /* SPD Byte 31 Memory Size [Side 1/2] */ + 0xff, /* 0x01 No memory */ + 0xff, /* 0x01 4/0 */ + 0x01, /* 0x02 8/0 */ + 0xff, /* 0x03 8/4 */ + 0x04, /* 0x04 16/0 or 16 */ + 0xff, /* 0x05 16/4 */ + 0x05, /* 0x06 16/8 */ + 0xff, /* 0x07 Invalid */ + 0x07, /* 0x08 32/0 or 32 */ + 0xff, /* 0x09 32/4 */ + 0xff, /* 0x0A 32/8 */ + 0xff, /* 0x0B Invalid */ + 0x08, /* 0x0C 32/16 */ + 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */ + 0x0a, /* 0x10 64/0 or 64 */ + 0xff, /* 0x11 64/4 */ + 0xff, /* 0x12 64/8 */ + 0xff, /* 0x13 Invalid */ + 0xff, /* 0x14 64/16 */ + 0xff, 0xff, 0xff, /* 0x15-17 Invalid */ + 0x0b, /* 0x18 64/32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */ + 0x0d, /* 0x20 128/0 or 128 */ + /* These configurations are not supported by the i810 */ + 0xff, /* 0x21 128/4 */ + 0xff, /* 0x22 128/8 */ + 0xff, /* 0x23 Invalid */ + 0xff, /* 0x24 128/16 */ + 0xff, 0xff, 0xff, /* 0x25-27 Invalid */ + 0xff, /* 0x28 128/32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */ + 0x0e, /* 0x30 128/64 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, /* 0x31-3f Invalid */ + 0x0f, /* 0x40 256/0 or 256 */ + /* Anything larger is not supported by the 82810. */ +}; + +/* * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. * Note that 2 is a value which the DRP should never be programmed to. * Some size values appear twice, due to single-sided vs dual-sided banks. Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Tue Oct 12 19:34:08 2010 (r5943) +++ trunk/src/northbridge/intel/i82810/raminit.h Tue Oct 12 23:37:03 2010 (r5944) @@ -27,61 +27,4 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50 -/* The following table has been bumped over to this header to avoid clutter in - * raminit.c. It's used to translate the value read from SPD Byte 31 to a value - * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most - * northbridges have some sort of simple calculation that can be done for this, - * I haven't yet figured out one for this northbridge. Until someone does, - * this table is necessary. - */ - -/* TODO: Find a better way of doing this. */ - -static const uint8_t translate_spd_to_i82810[] = { - /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB - * side can't be either, at least for now. - */ - /* TODO: For above case, only use the other side if > 4MB, and get some - * of these DIMMs to test it with. Same for unsupported 128/x sizes. - */ - - /* SPD Byte 31 Memory Size [Side 1/2] */ - 0xff, /* 0x01 No memory */ - 0xff, /* 0x01 4/0 */ - 0x01, /* 0x02 8/0 */ - 0xff, /* 0x03 8/4 */ - 0x04, /* 0x04 16/0 or 16 */ - 0xff, /* 0x05 16/4 */ - 0x05, /* 0x06 16/8 */ - 0xff, /* 0x07 Invalid */ - 0x07, /* 0x08 32/0 or 32 */ - 0xff, /* 0x09 32/4 */ - 0xff, /* 0x0A 32/8 */ - 0xff, /* 0x0B Invalid */ - 0x08, /* 0x0C 32/16 */ - 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */ - 0x0a, /* 0x10 64/0 or 64 */ - 0xff, /* 0x11 64/4 */ - 0xff, /* 0x12 64/8 */ - 0xff, /* 0x13 Invalid */ - 0xff, /* 0x14 64/16 */ - 0xff, 0xff, 0xff, /* 0x15-17 Invalid */ - 0x0b, /* 0x18 64/32 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */ - 0x0d, /* 0x20 128/0 or 128 */ - /* These configurations are not supported by the i810 */ - 0xff, /* 0x21 128/4 */ - 0xff, /* 0x22 128/8 */ - 0xff, /* 0x23 Invalid */ - 0xff, /* 0x24 128/16 */ - 0xff, 0xff, 0xff, /* 0x25-27 Invalid */ - 0xff, /* 0x28 128/32 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */ - 0x0e, /* 0x30 128/64 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, /* 0x31-3f Invalid */ - 0x0f, /* 0x40 256/0 or 256 */ - /* Anything larger is not supported by the 82810. */ -}; - #endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */

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AMD AP core startup problem
by Scott Duplichan 12 Oct '10

12 Oct '10

Hello, I find with my RS780/SB700 board (ECS A780GM-M3), the initial family 10h AP launch is not reliable. I often see a hang when when all the cores are running in parallel. The parallel execution is apparent if serial logging is enabled, because the characters logged by each core are interleaved. I noticed the AP cores do a few cf8/cfc pci config writes. Could simultaneous access to this shared index/data pair be responsible for the hang? Concerns about such conflicts is why the AMD agesa code does not run cores on the same die in parallel. Thanks, Scott

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[commit] r5943 - in trunk: src/arch/i386/include/arch src/cpu/amd/sc520 src/mainboard/amd/dbm690t src/mainboard/amd/mahogany src/mainboard/amd/mahogany_fam10 src/mainboard/amd/pistachio src/mainboa...
by repository service 12 Oct '10

12 Oct '10

Author: uwe Date: Tue Oct 12 19:34:08 2010 New Revision: 5943 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5943 Log: We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it. As both ioapic.h and acpi.h define a macro named "NMI", rename one of them (NMI -> NMIType in acpi.h). Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/arch/i386/include/arch/acpi.h trunk/src/cpu/amd/sc520/sc520.c trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c trunk/src/mainboard/arima/hdama/mptable.c trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/asus/m4a785-m/acpi_tables.c trunk/src/mainboard/asus/p2b-d/mptable.c trunk/src/mainboard/asus/p2b-ds/mptable.c trunk/src/mainboard/dell/s1850/mptable.c trunk/src/mainboard/emulation/qemu-x86/northbridge.c trunk/src/mainboard/getac/p470/acpi_tables.c trunk/src/mainboard/getac/p470/mptable.c trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c trunk/src/mainboard/hp/dl145_g1/mptable.c trunk/src/mainboard/ibase/mb899/acpi_tables.c trunk/src/mainboard/ibase/mb899/mptable.c trunk/src/mainboard/ibm/e325/mptable.c trunk/src/mainboard/ibm/e326/mptable.c trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c trunk/src/mainboard/intel/d945gclf/acpi_tables.c trunk/src/mainboard/intel/d945gclf/mptable.c trunk/src/mainboard/intel/eagleheights/acpi_tables.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/intel/jarrell/mptable.c trunk/src/mainboard/intel/mtarvon/mptable.c trunk/src/mainboard/intel/truxton/mptable.c trunk/src/mainboard/intel/xe7501devkit/acpi_tables.c trunk/src/mainboard/intel/xe7501devkit/mptable.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/mptable.c trunk/src/mainboard/iwill/dk8s2/mptable.c trunk/src/mainboard/iwill/dk8x/mptable.c trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/src/mainboard/kontron/986lcd-m/mptable.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/newisys/khepri/mptable.c trunk/src/mainboard/roda/rk886ex/acpi_tables.c trunk/src/mainboard/roda/rk886ex/mptable.c trunk/src/mainboard/supermicro/x6dai_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/tyan/s2735/mptable.c trunk/src/mainboard/tyan/s2850/mptable.c trunk/src/mainboard/tyan/s2875/mptable.c trunk/src/mainboard/tyan/s2880/mptable.c trunk/src/mainboard/tyan/s2881/mptable.c trunk/src/mainboard/tyan/s2882/mptable.c trunk/src/mainboard/tyan/s2885/mptable.c trunk/src/mainboard/tyan/s4880/mptable.c trunk/src/mainboard/tyan/s4882/mptable.c trunk/src/mainboard/via/epia-n/acpi_tables.c trunk/src/mainboard/via/epia-n/mainboard.c trunk/src/mainboard/via/epia-n/mptable.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/mainboard/via/vt8454c/acpi_tables.c trunk/src/mainboard/via/vt8454c/mptable.c trunk/src/northbridge/via/cx700/cx700_lpc.c trunk/src/northbridge/via/vx800/vx800.h trunk/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/src/southbridge/amd/cs5530/cs5530_isa.c trunk/src/southbridge/amd/cs5535/cs5535.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/sb600/sb600_lpc.c trunk/src/southbridge/amd/sb600/sb600_sm.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sm.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/src/southbridge/intel/esb6300/esb6300_pic.c trunk/src/southbridge/intel/i3100/i3100_lpc.c trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c trunk/src/southbridge/intel/i82801dx/i82801dx.h trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/src/southbridge/sis/sis966/sis966_lpc.c trunk/src/southbridge/via/vt8231/vt8231_lpc.c trunk/src/southbridge/via/vt8235/vt8235_lpc.c trunk/src/southbridge/via/vt8237r/vt8237r.h trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c trunk/util/mptable/mptable.c Modified: trunk/src/arch/i386/include/arch/acpi.h ============================================================================== --- trunk/src/arch/i386/include/arch/acpi.h Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/arch/i386/include/arch/acpi.h Tue Oct 12 19:34:08 2010 (r5943) @@ -175,7 +175,7 @@ LocalApic = 0, IOApic = 1, IRQSourceOverride = 2, - NMI = 3, + NMIType = 3, LocalApicNMI = 4, LApicAddressOverride = 5, IOSApic = 6, Modified: trunk/src/cpu/amd/sc520/sc520.c ============================================================================== --- trunk/src/cpu/amd/sc520/sc520.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/cpu/amd/sc520/sc520.c Tue Oct 12 19:34:08 2010 (r5943) @@ -4,6 +4,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> @@ -63,7 +64,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -59,8 +60,6 @@ extern const unsigned char AmlCode[]; -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -66,8 +67,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -56,8 +57,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/pistachio/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -59,8 +60,6 @@ extern const unsigned char AmlCode[]; -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -11,13 +11,13 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/amdk8_acpi.h" - #include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 @@ -45,8 +45,6 @@ extern const unsigned char AmlCode_ssdt4[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/serengeti_cheetah/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -54,7 +55,7 @@ smp_write_bus(mc, m->bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111 + smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { device_t dev; struct resource *res; Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -56,8 +57,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -19,6 +19,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -74,7 +75,7 @@ smp_write_bus(mc, m->bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111 + smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { device_t dev; struct resource *res; Modified: trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -56,8 +57,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/arima/hdama/mptable.c ============================================================================== --- trunk/src/mainboard/arima/hdama/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/arima/hdama/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -201,7 +202,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -66,8 +67,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -26,6 +26,7 @@ #include <string.h> #include <arch/acpi.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" @@ -59,7 +60,7 @@ /* Write SB IOAPIC. */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - VT8237R_APIC_ID, VT8237R_APIC_BASE, 0); + VT8237R_APIC_ID, IO_APIC_ADDR, 0); /* Write NB IOAPIC. */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <string.h> #include <stdint.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" @@ -62,7 +63,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE); + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); Modified: trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -26,6 +26,7 @@ #include <string.h> #include <arch/acpi.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" @@ -61,7 +62,7 @@ /* Write SB IOAPIC. */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - VT8237R_APIC_ID, VT8237R_APIC_BASE, 0); + VT8237R_APIC_ID, IO_APIC_ADDR, 0); /* Write NB IOAPIC. */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, Modified: trunk/src/mainboard/asus/m4a785-m/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/m4a785-m/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,12 +20,12 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> - #include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 @@ -56,8 +56,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/asus/p2b-d/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/p2b-d/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -56,7 +57,7 @@ smp_write_bus(mc, 2, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/asus/p2b-ds/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/asus/p2b-ds/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -55,7 +56,7 @@ smp_write_bus(mc, 1, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/dell/s1850/mptable.c ============================================================================== --- trunk/src/mainboard/dell/s1850/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/dell/s1850/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -109,7 +110,7 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <stdint.h> #include <device/device.h> #include <device/pci.h> @@ -64,7 +65,7 @@ /* Reserve space for the IOAPIC. This should be in the Southbridge, * but I couldn't tell which device to put it in. */ res = new_resource(dev, 2); - res->base = 0xfec00000UL; + res->base = IO_APIC_ADDR; res->size = 0x100000UL; res->limit = 0xffffffffUL; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | Modified: trunk/src/mainboard/getac/p470/acpi_tables.c ============================================================================== --- trunk/src/mainboard/getac/p470/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/getac/p470/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -23,6 +23,7 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <device/device.h> @@ -131,8 +132,6 @@ return header->length; } -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ Modified: trunk/src/mainboard/getac/p470/mptable.c ============================================================================== --- trunk/src/mainboard/getac/p470/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/getac/p470/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <string.h> #include <stdint.h> @@ -67,7 +67,7 @@ smp_write_bus(mc, isa_bus, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); Modified: trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/gigabyte/ma785gmt/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -54,8 +55,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,13 +20,13 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> - #define DUMP_ACPI_TABLES 0 #if DUMP_ACPI_TABLES == 1 @@ -55,8 +55,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/hp/dl145_g1/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/hp/dl145_g1/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -60,7 +61,7 @@ /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/ibase/mb899/acpi_tables.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/ibase/mb899/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -21,6 +21,7 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <device/device.h> @@ -86,8 +87,6 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ Modified: trunk/src/mainboard/ibase/mb899/mptable.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/ibase/mb899/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <string.h> #include <stdint.h> @@ -86,7 +86,7 @@ /* I/O APICs: APIC ID Version State Address */ ioapic_id = 2; - smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000); + smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ Modified: trunk/src/mainboard/ibm/e325/mptable.c ============================================================================== --- trunk/src/mainboard/ibm/e325/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/ibm/e325/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -81,7 +82,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* Legacy IOAPIC #2 */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/ibm/e326/mptable.c ============================================================================== --- trunk/src/mainboard/ibm/e326/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/ibm/e326/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -80,7 +81,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* Legacy IOAPIC #2 */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/iei/kino-780am2-fam10/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -56,8 +57,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/intel/d945gclf/acpi_tables.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/d945gclf/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -27,6 +27,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> +#include <arch/ioapic.h> #include "dmi.h" #define OLD_ACPI 0 @@ -146,8 +147,6 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ Modified: trunk/src/mainboard/intel/d945gclf/mptable.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/d945gclf/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <string.h> #include <stdint.h> @@ -65,7 +65,7 @@ smp_write_bus(mc, isa_bus, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ Modified: trunk/src/mainboard/intel/eagleheights/acpi_tables.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/eagleheights/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -23,6 +23,7 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -84,8 +85,6 @@ #define IO_APIC0 2 #define IO_APIC1 3 -#define IO_APIC0_ADDR 0xfec00000UL -#define IO_APIC1_ADDR 0xfec10000UL unsigned long acpi_fill_madt(unsigned long current) { @@ -99,9 +98,9 @@ current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC0_ADDR, irq_start); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC1_ADDR, irq_start); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC_ADDR + 0x10000, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -23,6 +23,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> @@ -144,7 +145,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* { device_t dev; Modified: trunk/src/mainboard/intel/jarrell/mptable.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/jarrell/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -111,7 +112,7 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 8, 0x20, 0xfec00000); + smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/intel/mtarvon/mptable.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/mtarvon/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -22,6 +22,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -62,7 +63,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, 0x01, 0x20, 0xfec00000); + smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0); Modified: trunk/src/mainboard/intel/truxton/mptable.c ============================================================================== --- trunk/src/mainboard/intel/truxton/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/truxton/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -95,7 +96,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000); + smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); Modified: trunk/src/mainboard/intel/xe7501devkit/acpi_tables.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/xe7501devkit/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -8,6 +8,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <assert.h> @@ -48,7 +49,7 @@ // Southbridge IOAPIC - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, IO_APIC_ADDR, irq_start); irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; // P64H2#2 Bus A IOAPIC Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/intel/xe7501devkit/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -37,7 +38,7 @@ // TODO: Gack. This is REALLY ugly. // Southbridge IOAPIC - smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address + smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, IO_APIC_ADDR); // APIC ID, Version, Address // P64H2#2 Bus A IOAPIC dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -11,13 +11,13 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/amdk8_acpi.h" - #include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 @@ -47,8 +47,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/iwill/dk8_htx/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -54,7 +55,7 @@ smp_write_bus(mc, m->bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111 + smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { device_t dev; struct resource *res; Modified: trunk/src/mainboard/iwill/dk8s2/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/iwill/dk8s2/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -82,7 +83,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/iwill/dk8x/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/iwill/dk8x/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -82,7 +83,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/jetway/pa78vm5/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -21,6 +21,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -55,8 +56,6 @@ extern const unsigned char AmlCode_ssdt5[]; #endif -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/kontron/986lcd-m/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -21,6 +21,7 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <device/device.h> @@ -86,8 +87,6 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ Modified: trunk/src/mainboard/kontron/986lcd-m/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/kontron/986lcd-m/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -17,11 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <string.h> #include <stdint.h> @@ -72,7 +72,7 @@ /* I/O APICs: APIC ID Version State Address */ ioapic_id = 2; - smp_write_ioapic(mc, ioapic_id, 0x20, 0xfec00000); + smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/kontron/kt690/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -59,8 +60,6 @@ extern const unsigned char AmlCode[]; -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/newisys/khepri/mptable.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/newisys/khepri/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -83,7 +84,7 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/roda/rk886ex/acpi_tables.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/roda/rk886ex/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -22,6 +22,7 @@ #include <string.h> #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> @@ -142,10 +143,6 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } - - -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ Modified: trunk/src/mainboard/roda/rk886ex/mptable.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/roda/rk886ex/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -19,11 +19,11 @@ * MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <string.h> #include <stdint.h> @@ -67,7 +67,7 @@ smp_write_bus(mc, isa_bus, "ISA "); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); Modified: trunk/src/mainboard/supermicro/x6dai_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/supermicro/x6dai_g/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -58,8 +59,8 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); - smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0); Modified: trunk/src/mainboard/supermicro/x6dhe_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -84,8 +85,8 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); - smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -84,8 +85,8 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); - smp_write_ioapic(mc, 3, 0x20, 0xfec10000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -109,7 +110,7 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -109,7 +110,7 @@ /* IOAPIC handling */ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; device_t dev; Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -59,8 +60,6 @@ extern const unsigned char AmlCode[]; -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> @@ -59,8 +60,6 @@ extern const unsigned char AmlCode[]; -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_mcfg(unsigned long current) { /* Just a dummy */ Modified: trunk/src/mainboard/tyan/s2735/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2735/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -32,7 +33,7 @@ smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 8, 0x20, 0xfec00000); + smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/tyan/s2850/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2850/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -105,7 +106,7 @@ #endif apicid_8111 = apicid_base+0; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); Modified: trunk/src/mainboard/tyan/s2875/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2875/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -120,7 +121,7 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_8111 = apicid_base+0; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); Modified: trunk/src/mainboard/tyan/s2880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2880/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -135,7 +136,7 @@ apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; Modified: trunk/src/mainboard/tyan/s2881/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2881/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -62,7 +63,7 @@ /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/tyan/s2882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2882/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> #include <string.h> @@ -143,7 +144,7 @@ apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/tyan/s2885/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s2885/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -64,7 +65,7 @@ smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); //8111 + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 { device_t dev; struct resource *res; Modified: trunk/src/mainboard/tyan/s4880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s4880/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -135,7 +136,7 @@ apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/tyan/s4882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/tyan/s4882/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -135,7 +136,7 @@ apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; - smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000); + smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/via/epia-n/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-n/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/epia-n/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -30,6 +30,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -94,7 +95,7 @@ /* Write SB IOAPIC. */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - VT8237R_APIC_ID, VT8237R_APIC_BASE, gsi_base); + VT8237R_APIC_ID, IO_APIC_ADDR, gsi_base); /* IRQ0 -> APIC IRQ2. */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) Modified: trunk/src/mainboard/via/epia-n/mainboard.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mainboard.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/epia-n/mainboard.c Tue Oct 12 19:34:08 2010 (r5943) @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <boot/tables.h> +#include <arch/ioapic.h> #include <southbridge/via/vt8237r/vt8237r.h> #include "chip.h" @@ -30,7 +31,7 @@ { #if CONFIG_IOAPIC == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - VT8237R_APIC_BASE, 0x1000); + IO_APIC_ADDR, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, 0xFEE00000ULL, 0x1000); lb_add_memory_range(mem, LB_MEM_RESERVED, Modified: trunk/src/mainboard/via/epia-n/mptable.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/epia-n/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -2,6 +2,7 @@ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -35,7 +36,7 @@ mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/pc2500e/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -24,6 +24,7 @@ #include <console/console.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <device/pci.h> #include <string.h> #include <stdint.h> @@ -59,7 +60,7 @@ mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE); + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); /* Now, assemble the table. */ mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0); Modified: trunk/src/mainboard/via/vt8454c/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/acpi_tables.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/vt8454c/acpi_tables.c Tue Oct 12 19:34:08 2010 (r5943) @@ -22,6 +22,7 @@ #include <string.h> #include <console/console.h> #include <arch/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -85,10 +86,6 @@ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); } - - -#define IO_APIC_ADDR 0xfec00000UL - unsigned long acpi_fill_madt(unsigned long current) { /* Local Apic */ Modified: trunk/src/mainboard/via/vt8454c/mptable.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/mainboard/via/vt8454c/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <arch/smp/mpspec.h> +#include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <string.h> @@ -56,7 +57,7 @@ mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 17, 0xfec00000); + smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR); mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); Modified: trunk/src/northbridge/via/cx700/cx700_lpc.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/northbridge/via/cx700/cx700_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -19,17 +19,14 @@ #include <arch/io.h> #include <console/console.h> - #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - #include <pc80/mc146818rtc.h> #include <pc80/i8259.h> #include <pc80/keyboard.h> #include <pc80/isa-dma.h> - #include <cpu/x86/lapic.h> #include <arch/ioapic.h> #include <stdlib.h> @@ -253,7 +250,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/northbridge/via/vx800/vx800.h Tue Oct 12 19:34:08 2010 (r5943) @@ -120,7 +120,6 @@ #define SB_EHCI_REG 0,0x10, 4, #define VX800SB_APIC_ID 0x4 -#define VX800SB_APIC_BASE 0xfec00000ULL #define VX800SB_APIC_DATA_OFFSET 0x10 #define VX800SB_APIC_ENTRY_NUMBER 0x40 Modified: trunk/src/southbridge/amd/amd8111/amd8111_lpc.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/amd8111/amd8111_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -101,7 +101,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/amd/cs5530/cs5530_isa.c ============================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530_isa.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/cs5530/cs5530_isa.c Tue Oct 12 19:34:08 2010 (r5943) @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -38,7 +39,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/amd/cs5535/cs5535.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/cs5535/cs5535.c Tue Oct 12 19:34:08 2010 (r5943) @@ -1,5 +1,6 @@ #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -82,7 +83,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Tue Oct 12 19:34:08 2010 (r5943) @@ -18,6 +18,7 @@ */ #include <arch/io.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -656,7 +657,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/amd/sb600/sb600_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/sb600/sb600_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -27,6 +27,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -84,7 +85,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; Modified: trunk/src/southbridge/amd/sb600/sb600_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sm.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/sb600/sb600_sm.c Tue Oct 12 19:34:08 2010 (r5943) @@ -302,7 +302,7 @@ /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -27,6 +27,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "sb700.h" static void lpc_init(device_t dev) @@ -87,7 +88,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; Modified: trunk/src/southbridge/amd/sb700/sb700_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sm.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/amd/sb700/sb700_sm.c Tue Oct 12 19:34:08 2010 (r5943) @@ -308,7 +308,7 @@ /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -13,6 +13,7 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "bcm5785.h" static void lpc_init(device_t dev) @@ -47,7 +48,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/esb6300/esb6300_lpc.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/esb6300/esb6300_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -242,7 +242,7 @@ value |= (1 << 8)|(1<<7); value |= (6 << 0)|(1<<13)|(1<<11); pci_write_config32(dev, 0xd0, value); - setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID + setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID /* disable reset timer */ pci_write_config8(dev, 0xd4, 0x02); @@ -330,7 +330,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/esb6300/esb6300_pic.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_pic.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/esb6300/esb6300_pic.c Tue Oct 12 19:34:08 2010 (r5943) @@ -23,7 +23,7 @@ pci_write_config8(dev, 0x3c, 0xff); /* Setup the ioapic */ - clear_ioapic(0xfec10000); + clear_ioapic(IO_APIC_ADDR + 0x10000); } static void pic_read_resources(device_t dev) @@ -35,7 +35,7 @@ /* Report the pic1 mbar resource */ res = new_resource(dev, 0x44); - res->base = 0xfec10000; + res->base = IO_APIC_ADDR + 0x10000; res->size = 256; res->limit = res->base + res->size -1; res->align = 8; Modified: trunk/src/southbridge/intel/i3100/i3100_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i3100/i3100_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i3100/i3100_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -372,7 +372,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Tue Oct 12 19:34:08 2010 (r5943) @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> +#include <arch/ioapic.h> #include "i82371eb.h" static void isa_init(struct device *dev) @@ -64,7 +65,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801ax.h" #define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ @@ -72,8 +73,8 @@ static void i82801ax_enable_apic(struct device *dev) { u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); @@ -266,7 +267,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801bx.h" #define NMI_OFF 0 @@ -74,8 +75,8 @@ static void i82801bx_enable_apic(struct device *dev) { uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; - volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; + volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); @@ -284,7 +285,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -11,6 +11,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801cx.h" #define NMI_OFF 0 @@ -26,8 +27,8 @@ static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; - volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010; + volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; + volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); dword = pci_read_config32(dev, GEN_CNTL); dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ @@ -224,7 +225,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801dx/i82801dx.h ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx.h Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801dx/i82801dx.h Tue Oct 12 19:34:08 2010 (r5943) @@ -36,8 +36,6 @@ extern void i82801dx_enable(device_t dev); #endif -#define IO_APIC_ADDR 0xfec00000 - /* * HPET Memory Address Range. Possible values: * 0xfed00000 for FED0_0000h - FED0_03FFh Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -29,6 +29,7 @@ #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801dx.h" #define NMI_OFF 0 @@ -317,7 +318,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -314,7 +314,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Oct 12 19:34:08 2010 (r5943) @@ -32,7 +32,6 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 -#define IO_APIC_ADDR 0xfec00000 #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -26,6 +26,7 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "i82801gx.h" #define NMI_OFF 0 @@ -476,7 +477,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/nvidia/ck804/ck804_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -211,7 +211,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -185,7 +185,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/sis/sis966/sis966_lpc.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/sis/sis966/sis966_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -178,7 +178,7 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -3,9 +3,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - #include <pc80/mc146818rtc.h> - +#include <arch/ioapic.h> #include "chip.h" /* PIRQ init @@ -141,7 +140,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/via/vt8235/vt8235_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/via/vt8235/vt8235_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -4,9 +4,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> - #include <pc80/mc146818rtc.h> - +#include <arch/ioapic.h> #include "chip.h" /* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. @@ -228,7 +227,7 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.h Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/via/vt8237r/vt8237r.h Tue Oct 12 19:34:08 2010 (r5943) @@ -35,7 +35,6 @@ #define VT8237S_SPI_MEM_BASE 0xfed02000UL #endif #define VT8237R_HPET_ADDR 0xfed00000ULL -#define VT8237R_APIC_BASE 0xfec00000ULL /* IDE */ #define IDE_CS 0x40 Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Tue Oct 12 19:34:08 2010 (r5943) @@ -490,7 +490,7 @@ /* Fixed APIC resource */ res = new_resource(dev, 0x44); - res->base = VT8237R_APIC_BASE; + res->base = IO_APIC_ADDR; res->size = 256; res->limit = 0xffffffffUL; res->align = 8; @@ -516,7 +516,7 @@ { vt8237_common_init(dev); pci_routing_fixup(dev); - setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID); + setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); setup_i8259(); init_keyboard(dev); } Modified: trunk/util/mptable/mptable.c ============================================================================== --- trunk/util/mptable/mptable.c Tue Oct 12 08:13:40 2010 (r5942) +++ trunk/util/mptable/mptable.c Tue Oct 12 19:34:08 2010 (r5943) @@ -300,6 +300,7 @@ char *preamble[] = { "#include <console/console.h>", "#include <arch/smp/mpspec.h>", +"#include <arch/ioapic.h>", "#include <device/pci.h>", "#include <string.h>", "#include <stdint.h>", @@ -355,7 +356,7 @@ }; char *ioapic_code[] = { -" smp_write_ioapic(mc, 2, 0x20, 0xfec00000);", +" smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);", " {", " device_t dev;", " struct resource *res;",

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[PATCH] We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it
by Uwe Hermann 12 Oct '10

12 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[flashrom] Testers/reviewers for partial writes needed
by Carl-Daniel Hailfinger 12 Oct '10

12 Oct '10

Hi, I am almost done with partial write support in flashrom, but I need tests and reviews of the new code. Already merged in flashrom are a few cleanup patches for write functions. Two patches which do the actual conversion are pending: http://patchwork.coreboot.org/patch/2091/ http://patchwork.coreboot.org/patch/2095/ Please apply them in the order specified above and review and test. Note: Even with the above patches applied, flashrom will still erase-all then write-all, but those patches are the last ones touching individual chip drivers. Once those patches are in, I will change the generic code to a rolling erase/write model with region exclusion and all the other fun stuff people want. The current code does not have progress printing for writes anymore, but this will be fixed automatically once the rolling erase/write code is in (I will simply reuse the erase progress printing). Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r5942 - in trunk/src: cpu/amd/car cpu/intel/car cpu/via/car include/cpu/amd
by repository service 12 Oct '10

12 Oct '10

Author: wt Date: Tue Oct 12 08:13:40 2010 New Revision: 5942 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5942 Log: Reduce duplicate definition in CAR code. Macros for the register addresses for the MTRR MSRs are already defined in include/cpu/x86/car.h. This patch uses those macros instead of creating a second instance of that same data. I also added a few macros to the amd mtrr.h to make the MSR naming more consistent. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/include/cpu/amd/mtrr.h Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942) @@ -155,7 +155,7 @@ /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -396,23 +396,48 @@ post_code(0xaf) /* Should never see this POST code. */ -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + + /* Variable IORR MTRR MSRs */ + .long IORRBase_MSR(0) + .long IORRMask_MSR(0) + .long IORRBase_MSR(1) + .long IORRMask_MSR(1) + + /* Top of memory MTRR MSRs */ + .long TOP_MEM_MSR + .long TOP_MEM2_MSR -var_iorr_msr: - .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 - -mem_top: - .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */ cache_as_ram_setup_out: Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942) @@ -115,7 +115,7 @@ /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -128,17 +128,38 @@ jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Tue Oct 12 08:12:00 2010 (r5941) +++ trunk/src/cpu/via/car/cache_as_ram.inc Tue Oct 12 08:13:40 2010 (r5942) @@ -47,7 +47,7 @@ /* Clear all MTRRs. */ xorl %edx, %edx - movl $fixed_mtrr_msr, %esi + movl $all_mtrr_msrs, %esi clear_fixed_var_mtrr: lodsl (%esi), %eax @@ -60,17 +60,38 @@ jmp clear_fixed_var_mtrr -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F - -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F +all_mtrr_msrs: + /* fixed MTRR MSRs */ + .long MTRRfix64K_00000_MSR + .long MTRRfix16K_80000_MSR + .long MTRRfix16K_A0000_MSR + .long MTRRfix4K_C0000_MSR + .long MTRRfix4K_C8000_MSR + .long MTRRfix4K_D0000_MSR + .long MTRRfix4K_D8000_MSR + .long MTRRfix4K_E0000_MSR + .long MTRRfix4K_E8000_MSR + .long MTRRfix4K_F0000_MSR + .long MTRRfix4K_F8000_MSR + + /* var MTRR MSRs */ + .long MTRRphysBase_MSR(0) + .long MTRRphysMask_MSR(0) + .long MTRRphysBase_MSR(1) + .long MTRRphysMask_MSR(1) + .long MTRRphysBase_MSR(2) + .long MTRRphysMask_MSR(2) + .long MTRRphysBase_MSR(3) + .long MTRRphysMask_MSR(3) + .long MTRRphysBase_MSR(4) + .long MTRRphysMask_MSR(4) + .long MTRRphysBase_MSR(5) + .long MTRRphysMask_MSR(5) + .long MTRRphysBase_MSR(6) + .long MTRRphysMask_MSR(6) + .long MTRRphysBase_MSR(7) + .long MTRRphysMask_MSR(7) + .long 0x000 /* NULL, end of table */ clear_fixed_var_mtrr_out: Modified: trunk/src/include/cpu/amd/mtrr.h ============================================================================== --- trunk/src/include/cpu/amd/mtrr.h Tue Oct 12 08:12:00 2010 (r5941) +++ trunk/src/include/cpu/amd/mtrr.h Tue Oct 12 08:13:40 2010 (r5942) @@ -21,12 +21,13 @@ #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5)) #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0)) -#define IORR0_BASE 0xC0010016 -#define IORR0_MASK 0xC0010017 -#define IORR1_BASE 0xC0010018 -#define IORR1_MASK 0xC0010019 -#define TOP_MEM 0xC001001A -#define TOP_MEM2 0xC001001D +#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg)) +#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1) + +#define TOP_MEM_MSR 0xC001001A +#define TOP_MEM2_MSR 0xC001001D +#define TOP_MEM TOP_MEM_MSR +#define TOP_MEM2 TOP_MEM2_MSR #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)

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coreboot October 2010