coreboot October 2010

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316 discussions

Re: [coreboot] [PATCH] coreboot: remove more inclusions of lib/debug.c after r5929
by Idwer Vollering 10 Oct '10

10 Oct '10

2010/10/10 Sylvain 'ythier' Hitier <sylvain.hitier(a)gmail.com> > Hello, > > r5929 seems quite mechanical, especially when removing the inclusions of > the > lib/debug.c file. > > I noticed that: > Inclusion is kept for these mainboards: > p2b-d > p2b-ls > whereas removed from all these ones: > p2b > p2b-ds > p2b-f > p3b-f > and > Inclusion is kept for this mainboard: > ga-6bxe > whereas removed from this one: > ga-6bxc > > I feel the mainboards look like quite similar (but I diff'ed only SVN'ed > files > in these dirs). > > However I couldn't find any reason why #include is sometimes kept... > > Hence I suggest the following _untested_ patch. > > Regards, > Sylvain "ythier" Hitier > > ======== > > Remove more inclusions of lib/debug.c after r5929. > Does your patch survive abuild for each board ? > > Signed-off-by: Sylvain Hitier <sylvain.hitier(a)gmail.com> > If it does: Acked-by: Idwer Vollering <vidwer(a)gmail.com> > > Index: mainboard/gigabyte/ga-6bxe/romstage.c > =================================================================== > --- mainboard/gigabyte/ga-6bxe/romstage.c (revision 5929) > +++ mainboard/gigabyte/ga-6bxe/romstage.c (working copy) > @@ -28,7 +28,6 @@ > #include <console/console.h> > #include "southbridge/intel/i82371eb/i82371eb.h" > #include "northbridge/intel/i440bx/raminit.h" > -#include "lib/debug.c" > #include "pc80/udelay_io.c" > #include "lib/delay.c" > #include "cpu/x86/bist.h" > Index: mainboard/asus/p2b-ls/romstage.c > =================================================================== > --- mainboard/asus/p2b-ls/romstage.c (revision 5929) > +++ mainboard/asus/p2b-ls/romstage.c (working copy) > @@ -28,7 +28,6 @@ > #include <console/console.h> > #include "southbridge/intel/i82371eb/i82371eb.h" > #include "northbridge/intel/i440bx/raminit.h" > -#include "lib/debug.c" > #include "pc80/udelay_io.c" > #include "lib/delay.c" > #include "cpu/x86/bist.h" > Index: mainboard/asus/p2b-d/romstage.c > =================================================================== > --- mainboard/asus/p2b-d/romstage.c (revision 5929) > +++ mainboard/asus/p2b-d/romstage.c (working copy) > @@ -29,7 +29,6 @@ > #include <console/console.h> > #include "southbridge/intel/i82371eb/i82371eb.h" > #include "northbridge/intel/i440bx/raminit.h" > -#include "lib/debug.c" > #include "pc80/udelay_io.c" > #include "lib/delay.c" > #include "cpu/x86/bist.h" > > > > -- > Free hugs for Free Software Fellows! > Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse >

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[commit] r5930 - in trunk/src/southbridge/amd: sb600 sb700
by repository service 10 Oct '10

10 Oct '10

Author: zbao Date: Sun Oct 10 17:18:53 2010 New Revision: 5930 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5930 Log: Trivial. Spelling check. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c trunk/src/southbridge/amd/sb600/sb600_sata.c trunk/src/southbridge/amd/sb600/sb600_sm.c trunk/src/southbridge/amd/sb600/sb600_usb.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c trunk/src/southbridge/amd/sb700/sb700_hda.c trunk/src/southbridge/amd/sb700/sb700_lpc.c trunk/src/southbridge/amd/sb700/sb700_sata.c trunk/src/southbridge/amd/sb700/sb700_sm.c trunk/src/southbridge/amd/sb700/sb700_usb.c Modified: trunk/src/southbridge/amd/sb600/sb600_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_hda.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_hda.c Sun Oct 10 17:18:53 2010 (r5930) @@ -53,7 +53,7 @@ dword &= mask; } while ((dword != val) && --count); - /* Timeout occured */ + /* Timeout occurred */ if (!count) return -1; return 0; @@ -169,7 +169,7 @@ } /** - * Wait 50usec for for the codec to indicate it is ready + * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ static int wait_for_ready(u32 base) @@ -190,7 +190,7 @@ } /** - * Wait 50usec for for the codec to indicate that it accepted + * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative */ Modified: trunk/src/southbridge/amd/sb600/sb600_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sata.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_sata.c Sun Oct 10 17:18:53 2010 (r5930) @@ -39,7 +39,7 @@ if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the - * second SATA port is poulated. + * second SATA port is populated. */ printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); @@ -83,7 +83,7 @@ byte = 0x6 << 2; pci_write_config8(sm_dev, 0xaf, byte); - /* get base addresss */ + /* get base address */ sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; Modified: trunk/src/southbridge/amd/sb600/sb600_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_sm.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_sm.c Sun Oct 10 17:18:53 2010 (r5930) @@ -338,7 +338,7 @@ pci_dev_set_resources(dev); - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ + /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte); Modified: trunk/src/southbridge/amd/sb600/sb600_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_usb.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb600/sb600_usb.c Sun Oct 10 17:18:53 2010 (r5930) @@ -96,7 +96,7 @@ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); - /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ + /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword); Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Sun Oct 10 17:18:53 2010 (r5930) @@ -63,7 +63,7 @@ rev = 0x11; /* A11 */ else if (enable_14Mhz == 0x1) { /* This happens, if does, only once. So later if we need to get - * the rivision ID, we don't have to make such a big function. + * the revision ID, we don't have to make such a big function. * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */ rev = 0x12; byte = pci_read_config8(dev, 0x40); @@ -549,7 +549,7 @@ /* LPC Device, BDF:0-20-3 */ /* The code below is ported from old chipset. It is not - * metioned in RPR. But I keep them. The registers and the + * mentioned in RPR. But I keep them. The registers and the * comments are compatible. */ dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); /* Enabling LPC DMA function. */ Modified: trunk/src/southbridge/amd/sb700/sb700_hda.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_hda.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_hda.c Sun Oct 10 17:18:53 2010 (r5930) @@ -91,7 +91,7 @@ } /** - * Wait 50usec for for the codec to indicate it is ready + * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ static int wait_for_ready(u32 base) @@ -112,7 +112,7 @@ } /** - * Wait 50usec for for the codec to indicate that it accepted + * Wait 50usec for the codec to indicate that it accepted * the previous command. No response would imply that the code * is non-operative */ Modified: trunk/src/southbridge/amd/sb700/sb700_lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_lpc.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_lpc.c Sun Oct 10 17:18:53 2010 (r5930) @@ -108,7 +108,7 @@ /** * @brief Enable resources for children devices * - * @param dev the device whos children's resources are to be enabled + * @param dev the device whose children's resources are to be enabled * */ static void sb700_lpc_enable_childrens_resources(device_t dev) Modified: trunk/src/southbridge/amd/sb700/sb700_sata.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sata.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_sata.c Sun Oct 10 17:18:53 2010 (r5930) @@ -111,7 +111,7 @@ /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; - /* get base addresss */ + /* get base address */ sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; Modified: trunk/src/southbridge/amd/sb700/sb700_sm.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_sm.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_sm.c Sun Oct 10 17:18:53 2010 (r5930) @@ -206,7 +206,7 @@ /* 4.14:Enabling Requester ID for upstream traffic. */ abcfg_reg(0x98, 1 << 16, 1 << 16); - /* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */ + /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */ byte = pm2_ioread(0xE5); byte |= 1 << 2; pm2_iowrite(0xE5, byte); @@ -345,7 +345,7 @@ pci_dev_set_resources(dev); - /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ + /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */ byte = pm_ioread(0x52); byte |= 1 << 6; pm_iowrite(0x52, byte); Modified: trunk/src/southbridge/amd/sb700/sb700_usb.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_usb.c Sat Oct 9 19:00:18 2010 (r5929) +++ trunk/src/southbridge/amd/sb700/sb700_usb.c Sun Oct 10 17:18:53 2010 (r5930) @@ -83,7 +83,7 @@ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); - /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ + /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */ dword = 0x00020F00; write32(usb2_bar0 + 0xC0, dword); @@ -105,8 +105,8 @@ pci_write_config32(dev, 0x50, dword); #endif - /* RPR6.13 Enabling Fix for EHCI Controller Dirver Yellow Sign Issue */ - /* RPR says it is just for A12. CIMM sets it when it is above A11. */ + /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */ + /* RPR says it is just for A12. CIMx sets it when it is above A11. */ dword = pci_read_config32(dev, 0x50); dword |= (1 << 20); pci_write_config32(dev, 0x50, dword);

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[PATCH] Remove various .c #includes from Intel 440BX/82371EB boards
by Uwe Hermann 09 Oct '10

09 Oct '10

See patch. This works fine (tested in abuild) for all 440BX boards, but it seems to break the build of the QEMU target. I tried to fix it but I don't really know how it can be done. The problem is (I guess) that the QEMU target is still using ROMCC and all other 82371EB boards don't (?) Any ideas? CC southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o GEN romstage/ldscript.ld LINK coreboot.romstage build/southbridge/intel/i82371eb/i82371eb_early_pm.romstage.o: In function `enable_pm': /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_pm.c:42: undefined reference to `die' build/southbridge/intel/i82371eb/i82371eb_early_smbus.romstage.o: In function `enable_smbus': /home/uwe/v4_remove_c/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c:47: undefined reference to `die' collect2: ld returned 1 exit status make: *** [build/coreboot.romstage] Error 1 Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r5929 - in trunk/src: mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-ds mainboard/asus/p2b-f ma...
by repository service 09 Oct '10

09 Oct '10

Author: uwe Date: Sat Oct 9 19:00:18 2010 New Revision: 5929 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5929 Log: Remove various .c #includes from Intel 440BX/82371EB boards. - Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and northbridge/intel/i440bx/debug.c. - Add various header files which are now needed. - Make functions that need to be visible non-static. - Drop a remaining "select ROMCC" from a 4440BX board. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c trunk/src/mainboard/a-trend/atc-6240/romstage.c trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/mainboard/asus/p2b-ds/romstage.c trunk/src/mainboard/asus/p2b-f/romstage.c trunk/src/mainboard/asus/p2b-ls/romstage.c trunk/src/mainboard/asus/p2b/romstage.c trunk/src/mainboard/asus/p3b-f/romstage.c trunk/src/mainboard/azza/pt-6ibd/romstage.c trunk/src/mainboard/biostar/m6tba/romstage.c trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c trunk/src/mainboard/msi/ms6119/romstage.c trunk/src/mainboard/msi/ms6147/romstage.c trunk/src/mainboard/msi/ms6156/romstage.c trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nokia/ip530/romstage.c trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c trunk/src/mainboard/tyan/s1846/romstage.c trunk/src/northbridge/intel/i440bx/Makefile.inc trunk/src/northbridge/intel/i440bx/debug.c trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i440bx/raminit.h trunk/src/southbridge/intel/i82371eb/Makefile.inc trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Modified: trunk/src/mainboard/a-trend/atc-6220/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6220/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/a-trend/atc-6220/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/a-trend/atc-6240/romstage.c ============================================================================== --- trunk/src/mainboard/a-trend/atc-6240/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/a-trend/atc-6240/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c ============================================================================== --- trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/abit/be6-ii_v2_0/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -39,14 +38,14 @@ /* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { /* FIXME: It's a Winbond W83977EF, actually. */ Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -27,7 +27,7 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" @@ -38,14 +38,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { enable_lapic(); /* FIXME? */ Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -27,9 +27,8 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -38,14 +37,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { enable_lapic(); /* FIXME? */ Modified: trunk/src/mainboard/asus/p2b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-f/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p2b-f/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -39,14 +38,14 @@ /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ Modified: trunk/src/mainboard/asus/p2b-ls/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ls/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p2b-ls/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" @@ -38,14 +38,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ Modified: trunk/src/mainboard/asus/p2b/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p2b/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/asus/p3b-f/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p3b-f/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/asus/p3b-f/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,10 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" -#include "southbridge/intel/i82371eb/i82371eb_early_pm.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,17 +35,18 @@ #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include <lib.h> +void enable_pm(void); +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - /* * ASUS P3B-F specific SPD enable magic. * Modified: trunk/src/mainboard/azza/pt-6ibd/romstage.c ============================================================================== --- trunk/src/mainboard/azza/pt-6ibd/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/azza/pt-6ibd/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -39,14 +38,14 @@ /* FIXME: It's a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { /* FIXME: It's a Winbond W83977EF, actually. */ Modified: trunk/src/mainboard/biostar/m6tba/romstage.c ============================================================================== --- trunk/src/mainboard/biostar/m6tba/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/biostar/m6tba/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c ============================================================================== --- trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -39,14 +38,14 @@ /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { /* FIXME: Should be PC97307! */ Modified: trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/gigabyte/ga-6bxc/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -38,14 +37,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/gigabyte/ga-6bxe/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" @@ -38,14 +38,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { it8671f_48mhz_clkin(); Modified: trunk/src/mainboard/msi/ms6119/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6119/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/msi/ms6119/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/msi/ms6147/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6147/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/msi/ms6147/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include <cpu/x86/bist.h> @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/msi/ms6156/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6156/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/msi/ms6156/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/nokia/ip530/Kconfig Sat Oct 9 19:00:18 2010 (r5929) @@ -28,7 +28,6 @@ select SOUTHBRIDGE_TI_PCI1X2X select DRIVERS_DEC_21143 select BOARD_ROMSIZE_KB_256 - select ROMCC select PIRQ_ROUTE select HAVE_PIRQ_TABLE select UDELAY_TSC Modified: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- trunk/src/mainboard/nokia/ip530/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/nokia/ip530/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c ============================================================================== --- trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -38,14 +37,14 @@ #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/tyan/s1846/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s1846/romstage.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/mainboard/tyan/s1846/romstage.c Sat Oct 9 19:00:18 2010 (r5929) @@ -26,9 +26,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" -#include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" @@ -37,14 +36,14 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) -static inline int spd_read_byte(unsigned int device, unsigned int address) +void enable_smbus(void); +int smbus_read_byte(u8 device, u8 address); + +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } -#include "northbridge/intel/i440bx/raminit.c" -#include "northbridge/intel/i440bx/debug.c" - void main(unsigned long bist) { pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/northbridge/intel/i440bx/Makefile.inc ============================================================================== --- trunk/src/northbridge/intel/i440bx/Makefile.inc Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/northbridge/intel/i440bx/Makefile.inc Sat Oct 9 19:00:18 2010 (r5929) @@ -20,3 +20,6 @@ driver-y += northbridge.c +romstage-y += raminit.c +romstage-y += debug.c + Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/northbridge/intel/i440bx/debug.c Sat Oct 9 19:00:18 2010 (r5929) @@ -1,4 +1,6 @@ -static void dump_spd_registers(void) +#include "raminit.h" + +void dump_spd_registers(void) { #if CONFIG_DEBUG_RAM_SETUP int i; Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/northbridge/intel/i440bx/raminit.c Sat Oct 9 19:00:18 2010 (r5929) @@ -21,7 +21,12 @@ #include <spd.h> #include <delay.h> +#include <stdint.h> #include <stdlib.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> #include "i440bx.h" #include "raminit.h" @@ -630,7 +635,7 @@ Public interface. -----------------------------------------------------------------------------*/ -static void sdram_set_registers(void) +void sdram_set_registers(void) { int i, max; uint8_t reg; @@ -956,7 +961,7 @@ PRINT_DEBUG("\n"); } -static void sdram_set_spd_registers(void) +void sdram_set_spd_registers(void) { /* Setup DRAM row boundary registers and other attributes. */ set_dram_row_attributes(); @@ -972,7 +977,7 @@ pci_write_config8(NB, DRAMT, 0x03); } -static void sdram_enable(void) +void sdram_enable(void) { int i; Modified: trunk/src/northbridge/intel/i440bx/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.h Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/northbridge/intel/i440bx/raminit.h Sat Oct 9 19:00:18 2010 (r5929) @@ -26,5 +26,12 @@ /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ #define DIMM_SPD_BASE 0x50 + +/* Function prototypes. */ +int spd_read_byte(unsigned int device, unsigned int address); +void sdram_set_registers(void); +void sdram_set_spd_registers(void); +void sdram_enable(void); +void dump_spd_registers(void); #endif /* RAMINIT_H */ Modified: trunk/src/southbridge/intel/i82371eb/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82371eb/Makefile.inc Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/Makefile.inc Sat Oct 9 19:00:18 2010 (r5929) @@ -25,4 +25,6 @@ driver-y += i82371eb_smbus.c driver-y += i82371eb_reset.c -#romstage-y += i82371eb_early_rom.c +romstage-y += i82371eb_early_pm.c +romstage-y += i82371eb_early_smbus.c + Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sat Oct 9 19:00:18 2010 (r5929) @@ -21,10 +21,17 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H +#if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) + +#include <arch/io.h> +#include <device/device.h> #include "chip.h" + void i82371eb_enable(device_t dev); void i82371eb_hard_reset(void); + +#endif #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the @@ -55,6 +62,8 @@ #define PMBA 0x40 /* Power management base address */ #define PMREGMISC 0x80 /* Miscellaneous power management */ +#define PM_IO_BASE 0xe400 + /* Bit definitions */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ #define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_pm.c Sat Oct 9 19:00:18 2010 (r5929) @@ -19,24 +19,25 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> #include <device/pci_ids.h> +#include <console/console.h> #include "i82371eb.h" -#define PM_IO_BASE 0xe400 +void enable_pm(void); -static void enable_pm(void) +void enable_pm(void) { device_t dev; u8 reg8; u16 reg16; - /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */ + /* Get the SMBus/PM device of the 82371AB/EB/MB. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); - if (dev == PCI_DEV_INVALID) - die("SMBus/PM controller not found\n"); - /* Set the PM I/O base. */ pci_write_config32(dev, PMBA, PM_IO_BASE | 1); @@ -50,4 +51,3 @@ reg8 |= PMIOSE; pci_write_config8(dev, PMREGMISC, reg8); } - Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c Sat Oct 9 19:00:18 2010 (r5929) @@ -18,28 +18,29 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */ - #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82371eb.h" #include "i82371eb_smbus.h" #define SMBUS_IO_BASE 0x0f00 -static void enable_smbus(void) +int smbus_read_byte(u8 device, u8 address); + +void enable_smbus(void) { device_t dev; u8 reg8; u16 reg16; - /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */ + /* Get the SMBus/PM device of the 82371AB/EB/MB. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); - if (dev == PCI_DEV_INVALID) - die("SMBus/PM controller not found\n"); - /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); @@ -57,7 +58,7 @@ outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); } -static int smbus_read_byte(u8 device, u8 address) +int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.c Sat Oct 9 19:00:18 2010 (r5929) @@ -24,6 +24,7 @@ #include <device/pci_ids.h> #include <device/smbus.h> #include "i82371eb.h" +#include "i82371eb_smbus.h" /* TODO: Needed later? */ static const struct smbus_bus_operations lops_smbus_bus = { Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Sat Oct 9 09:18:50 2010 (r5928) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_smbus.h Sat Oct 9 19:00:18 2010 (r5929) @@ -10,6 +10,9 @@ #define SMBUS_STATUS_MASK 0x1e #define SMBUS_ERROR_FLAG (1<<2) +void enable_smbus(void); +int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address); + static inline void smbus_delay(void) { outb(0x80, 0x80); @@ -63,7 +66,7 @@ return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } -static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { unsigned status_register; unsigned byte;

1 0

[PATCH] Move d810e2cb to tiny boot block.
by Warren Turkal 09 Oct '10

09 Oct '10

I just tried building the d810e2cb board with a tiny boot block. It builds! Ship it! :) Joseph, I see that you did the work on romstage.c on that board. Would you be able to test this patch to make sure it works? If anyone else has this board, I'd appreciate the testing. Thanks, wt 8<--------- Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/mainboard/intel/d810e2cb/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 8c6c76b..6d407d2 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select HAVE_MAINBOARD_RESOURCES select GFXUMA + select TINY_BOOTBLOCK config MAINBOARD_DIR string -- 1.7.1

2 3

[commit] r5928 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 09 Oct '10

09 Oct '10

Author: zbao Date: Sat Oct 9 09:18:50 2010 New Revision: 5928 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5928 Log: Trivial. Spell checking. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h Modified: trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct/mctecc_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -61,7 +61,7 @@ * guarantee that the NB scrubs the entire dram on its node. Do do this, we * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all - * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do + * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do * this efficiently, we need only to sample one of the nodes, the node with the * largest ammount of dram populated is the one which will take the longest amount * of time (the scrub rate is set to max, the same rate, on all nodes). So, Modified: trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct/mctmtr_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -38,7 +38,7 @@ u32 lo, hi; /* Set temporary top of memory from Node structure data. - * Adjust temp top of memory down to accomodate 32-bit IO space. + * Adjust temp top of memory down to accommodate 32-bit IO space. * Bottom40bIO=top of memory, right justified 8 bits * (defines dram versus IO space type) * Bottom32bIO=sub 4GB top of memory, right justified 8 bits @@ -151,7 +151,7 @@ * 2. Each range must be naturally aligned (Base is same as size) * * There are two code paths: the ascending path and descending path - * (analogous to bsf and bsr), where the next limit is a funtion of the + * (analogous to bsf and bsr), where the next limit is a function of the * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path @@ -219,7 +219,7 @@ u32 lo, hi; /*====================================================================== - * Adjust temp top of memory down to accomodate UMA memory start + * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -56,7 +56,7 @@ * guarantee that the NB scrubs the entire dram on its node. Do do this, we * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all - * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do + * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do * this efficiently, we need only to sample one of the nodes, the node with the * largest ammount of dram populated is the one which will take the longest amount * of time (the scrub rate is set to max, the same rate, on all nodes). So, Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -36,7 +36,7 @@ u32 lo, hi; /* Set temporary top of memory from Node structure data. - * Adjust temp top of memory down to accomodate 32-bit IO space. + * Adjust temp top of memory down to accommodate 32-bit IO space. * Bottom40bIO=top of memory, right justified 8 bits * (defines dram versus IO space type) * Bottom32bIO=sub 4GB top of memory, right justified 8 bits @@ -145,7 +145,7 @@ * 2. Each range must be naturally aligned (Base is same as size) * * There are two code paths: the ascending path and descending path - * (analogous to bsf and bsr), where the next limit is a funtion of the + * (analogous to bsf and bsr), where the next limit is a function of the * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path @@ -213,7 +213,7 @@ u32 lo, hi; /*====================================================================== - * Adjust temp top of memory down to accomodate UMA memory start + * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -91,7 +91,7 @@ DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 1); else { - /* Broadcast write to all D3Dbyte chiplet register offset 0xc + /* Broadcast write to all D3Dbyte chipset register offset 0xc * Set bit 0 (wrTrain) * Program bit 4 to nibble being trained (only matters for x4dimms) * retain value of 3:2 (Trdimmsel) @@ -114,7 +114,7 @@ AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); Value = bitTestSet(Value, 0); /* enable WL training */ Value = bitTestReset(Value, 4); /* for x8 only */ - Value = bitTestReset(Value, 5); /* for harward WL training */ + Value = bitTestReset(Value, 5); /* for hardware WL training */ AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value); Addr=0x4D030F0C; AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr); @@ -172,7 +172,7 @@ * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT * IN u32: MRS value - * OUT u32: sWAPPED BANK BITS + * OUT u32: Swapped BANK BITS * * ---------------------------------------------------------------------------- */ @@ -208,7 +208,7 @@ * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT * IN u32: MRS value - * OUT u32: sWAPPED BANK BITS + * OUT u32: Swapped BANK BITS * * ---------------------------------------------------------------------------- */ @@ -262,7 +262,7 @@ MemClkFreq = get_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); /* Configure the DCT to send initialization MR commands to the target DIMM - * ;by programming the F2x[1,0]7C register using the following steps. + * by programming the F2x[1,0]7C register using the following steps. */ rank = 0; while ((rank < pDCTData->DimmRanks[dimm]) && (rank < 2)) @@ -271,14 +271,14 @@ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsChipSelStart, MrsChipSelEnd, dimm*2+rank); /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * ;register that defines the required DDR3-defined function for write - * ; levelization. + * register that defines the required DDR3-defined function for write + * levelization. */ MrsBank = swapBankBits(pDCTData,1); set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank); /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * ; for write levelization. + * for write levelization. */ tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0 */ @@ -347,7 +347,7 @@ tempW1 = bitTestSet(tempW, MRS_Level); if (rank == 0) { - /* ?Enable the output driver of the first rank of the target DIMM. */ + /* Enable the output driver of the first rank of the target DIMM. */ tempW = tempW1; } else @@ -371,7 +371,7 @@ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsAddressStart, MrsAddressEnd, tempW); /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to - * ;the specified DIMM. + * the specified DIMM. */ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); @@ -381,13 +381,13 @@ { } /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * ;register that defines the required DDR3-defined function for Rtt_WR. + * register that defines the required DDR3-defined function for Rtt_WR. */ MrsBank = swapBankBits(pDCTData,2); set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank); /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * ; for Rtt_WR (DRAMTermDyn). + * for Rtt_WR (DRAMTermDyn). */ tempW = 0;/* PASR = 0,*/ /* program MrsAddress[7,6,5:3]=SRT,ASR,CWL, @@ -457,19 +457,19 @@ { /* Program F2x[1, 0]7C[MrsChipSel[2:0]] for the current rank - * ;to be trained. + * to be trained. */ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsChipSelStart, MrsChipSelEnd, currDimm*2+rank); /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal - * ;DRAM register that defines the required DDR3-defined function - * ; for write levelization. + * DRAM register that defines the required DDR3-defined function + * for write levelization. */ MrsBank = swapBankBits(pDCTData,1); set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank); /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required - * ;DDR3-defined function for write levelization. + * DDR3-defined function for write levelization. */ tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */ @@ -528,7 +528,7 @@ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsAddressStart, MrsAddressEnd, tempW); /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command - * ; to the specified DIMM. + * to the specified DIMM. */ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); @@ -537,13 +537,13 @@ pDCTData->NodeId, FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd)) == 1); /* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM - * ;register that defines the required DDR3-defined function for Rtt_WR. + * register that defines the required DDR3-defined function for Rtt_WR. */ MrsBank = swapBankBits(pDCTData,2); set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank); /* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function - * ; for Rtt_WR (DRAMTermDyn). + * for Rtt_WR (DRAMTermDyn). */ tempW = 0;/* PASR = 0,*/ /* program MrsAddress[7,6,5:3]=SRT,ASR,CWL, @@ -651,7 +651,7 @@ u16 Addl_Data_Offset, Addl_Data_Port; /* Program F2x[1, 0]9C_x08[WrLvOdt[3:0]] to the proper ODT settings for the - * ;current memory subsystem configuration. + * current memory subsystem configuration. */ programODT(pMCTData, pDCTData, dimm); @@ -711,12 +711,12 @@ while(ByteLane < MAX_BYTE_LANES) { /* Program an initialization value to registers F2x[1, 0]9C_x[51:50] and - * ;F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields - * ; If the target frequency is different than 400MHz, BIOS must + * F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields + * If the target frequency is different than 400MHz, BIOS must * execute two training passes for each DIMM. * For pass 1 at a 400MHz MEMCLK frequency, use an initial total delay value - * ; of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined - * ;by design. + * of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined + * by design. */ pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c Sat Oct 9 09:18:50 2010 (r5928) @@ -64,7 +64,6 @@ } /*----------------------------------------------------------------------------- - * uint 32 * u32 bitTestSet(u32 csMask,u32 tempD) * * Description: @@ -86,7 +85,6 @@ } /*----------------------------------------------------------------------------- - * uint 32 * u32 bitTestReset(u32 csMask,u32 tempD) * * Description: @@ -110,12 +108,11 @@ } /*----------------------------------------------------------------------------- - * uint 32 * u32 get_Bits(DCTStruct *DCTData, u8 DCT, u8 Node, u8 func, u16 offset, * u8 low, u8 high) * * Description: - * This routine Gets the PCT bits from the specidfied Node, DCT and PCI address + * This routine Gets the PCT bits from the specified Node, DCT and PCI address * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT @@ -161,12 +158,11 @@ } /*----------------------------------------------------------------------------- - * uint 32 * void set_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, u16 offset, * u8 low, u8 high, u32 value) * * Description: - * This routine Sets the PCT bits from the specidfied Node, DCT and PCI address + * This routine Sets the PCT bits from the specified Node, DCT and PCI address * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT @@ -212,12 +208,11 @@ } /*------------------------------------------------- - * uint 32 * u32 get_ADD_DCT_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, * u16 offset,u8 low, u8 high) * * Description: - * This routine gets the Additional PCT register from Function 2 by specidfied + * This routine gets the Additional PCT register from Function 2 by specified * Node, DCT and PCI address * * Parameters: @@ -251,12 +246,11 @@ } /*------------------------------------------------- - * uint 32 * void set_DCT_ADDR_Bits(DCTStruct *DCTData, u8 DCT,u8 Node,u8 func, * u16 offset,u8 low, u8 high, u32 value) * * Description: - * This routine sets the Additional PCT register from Function 2 by specidfied + * This routine sets the Additional PCT register from Function 2 by specified * Node, DCT and PCI address * * Parameters: @@ -297,7 +291,6 @@ } /*------------------------------------------------- - * uint 32 * BOOL bitTest(u32 value, u8 bitLoc) * * Description: Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h Sat Oct 9 04:31:10 2010 (r5927) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h Sat Oct 9 09:18:50 2010 (r5928) @@ -23,7 +23,7 @@ #define MAX_TOTAL_DIMMS 8 /* Maximum Number of DIMMs in systems */ /* (DCT0 + DCT1) */ #define MAX_DIMMS 4 /* Maximum Number of DIMMs on each DCT */ -#define MAX_LDIMMS 4 /* Maximum number of Logial DIMMs per DCT */ +#define MAX_LDIMMS 4 /* Maximum number of Logical DIMMs per DCT */ /*MCT Max variables */ #define MAX_ERRORS 32 /* Maximum number of Errors Reported */

1 0

[commit] r5927 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3
by repository service 08 Oct '10

08 Oct '10

Author: zbao Date: Sat Oct 9 04:31:10 2010 New Revision: 5927 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5927 Log: Trivial. Spell checking. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mct_d.h trunk/src/northbridge/amd/amdmct/mct/mctardk3.c trunk/src/northbridge/amd/amdmct/mct/mctardk4.c trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Sat Oct 9 04:31:10 2010 (r5927) @@ -110,7 +110,7 @@ #define Mod64BitMux 4 /* func 2, offset A0h, bit 4 */ #define DisableJitter 1 /* func 2, offset A0h, bit 1 */ #define DramEnabled 9 /* func 2, offset A0h, bit 9 */ -#define SyncOnUcEccEn 2 /* fun 3, offset 44h, bit 2 */ +#define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2 */ /*============================================================================= Jedec DDR II @@ -349,7 +349,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFail; /* Bitmap showing the chanel informaiton about failed Chip Selects*/ + u16 ChannelTrainFail; /* Bitmap showing the channel information about failed Chip Selects*/ /* 0 in any bit field indicates Channel 0*/ /* 1 in any bit field indicates Channel 1*/ }; @@ -509,7 +509,7 @@ #endif -// global function +/* global function */ u32 NodePresent(u32 Node); u32 Get_NB32n(struct DCTStatStruc *pDCTstat, u32 addrx); u32 Get_NB32(u32 addr); /* NOTE: extend addr to 32 bit for bus > 0 */ Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h Sat Oct 9 04:31:10 2010 (r5927) @@ -236,7 +236,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -436,7 +436,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 CSUsrTestFail; /* Chip selects excluded by user */ @@ -471,7 +471,7 @@ u8 MaxDCTs; /* Max number of DCTs in system*/ // NOTE: removed u8 DCT. Use ->dev_ for pci R/W; /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk3.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Sat Oct 9 04:31:10 2010 (r5927) @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 021100xFF301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -128,7 +128,7 @@ * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) * These must be listed in ascending order. - * FFh (0xFE) has special meanying of 'any', and must be listed first for each speed grade. + * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value * #5, BYTE, Number of DIMMs (Primary Key) Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk4.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Sat Oct 9 04:31:10 2010 (r5927) @@ -59,7 +59,7 @@ * #1, BYTE, Speed (DCTStatstruc.Speed) * #2, BYTE, number of Address bus loads on the Channel. * These must be listed in ascending order. - * FFh (-1) has special meanying of 'any', and must be listed first for + * FFh (-1) has special meaning of 'any', and must be listed first for * each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Sat Oct 9 04:31:10 2010 (r5927) @@ -134,7 +134,7 @@ /* Bug#15880: Determine validity of reset settings for DDR PHY timing * regi.. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */ u32 dev; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Oct 8 22:09:21 2010 (r5926) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sat Oct 9 04:31:10 2010 (r5927) @@ -263,7 +263,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -464,7 +464,7 @@ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */ @@ -513,7 +513,7 @@ u8 MaxDCTs; /* Max number of DCTs in system*/ /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL;

1 0

[commit] r5926 - in trunk/src/southbridge/intel: i82801ax i82801bx
by repository service 08 Oct '10

08 Oct '10

Author: uwe Date: Fri Oct 8 22:09:21 2010 New Revision: 5926 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5926 Log: Drop unused i82801ax_early_lpc.c and i82801bx_early_lpc.c. Nothing ever calls the functions in these files, and we already have i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same _and_ are hooked up correctly in the Makefile.inc and via the USE_WATCHDOG_ON_BOOT mechanism. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c trunk/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c

1 0

[commit] r5925 - trunk/src/southbridge/intel/i82801ax
by repository service 08 Oct '10

08 Oct '10

Author: uwe Date: Fri Oct 8 21:24:56 2010 New Revision: 5925 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5925 Log: Round 2 of i82801AX fixes to get it into a usable shape. - Remove left-overs from more generic code in i82801xx times, and fix register names as needed. - Simplify IDE init code (and save some ROM space too). - Simplify PIRQ code. - Use u8 et al instead of uint8_t everywhere. - Random other fixes. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/intel/i82801ax/chip.h trunk/src/southbridge/intel/i82801ax/i82801ax.c trunk/src/southbridge/intel/i82801ax/i82801ax.h trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Modified: trunk/src/southbridge/intel/i82801ax/chip.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/chip.h Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/chip.h Fri Oct 8 21:24:56 2010 (r5925) @@ -25,22 +25,16 @@ #ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801ax_config { - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; + u8 pirqa_routing; + u8 pirqb_routing; + u8 pirqc_routing; + u8 pirqd_routing; - uint8_t ide0_enable; - uint8_t ide1_enable; + u8 ide0_enable; + u8 ide1_enable; }; extern struct chip_operations southbridge_intel_i82801ax_ops; Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.c Fri Oct 8 21:24:56 2010 (r5925) @@ -27,38 +27,21 @@ void i82801ax_enable(device_t dev) { - unsigned int index = 0; - uint16_t cur_disable_mask, new_disable_mask; + u16 reg16, index; + device_t lpc_dev; - /* All 82801xx devices should be on bus 0. */ - unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC - device_t lpc_dev = dev_find_slot(0, devfn); // 0 + /* Search for the 82801AA/AB LPC device (D31:F0) on PCI bus 0. */ + lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc_dev) return; - /* We're going to assume, perhaps incorrectly, that if a function - * exists it can be disabled. Workarounds for ICH variants that don't - * follow this should be done by checking the device ID. - */ - if (PCI_SLOT(dev->path.pci.devfn) == 31) { - index = PCI_FUNC(dev->path.pci.devfn); - } else if (PCI_SLOT(dev->path.pci.devfn) == 29) { - index = 8 + PCI_FUNC(dev->path.pci.devfn); - } + index = PCI_FUNC(dev->path.pci.devfn); - /* Function 0 is a bit of an exception. */ - if (index == 0) { - index = 14; - } - - cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); - new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */ - if (!dev->enabled) { - new_disable_mask |= (1 << index); /* Disable it, if desired. */ - } - if (new_disable_mask != cur_disable_mask) { - pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); - } + reg16 = pci_read_config16(lpc_dev, FUNC_DIS); + reg16 &= ~(1 << index); /* Enable device. */ + if (!dev->enabled) + reg16 |= (1 << index); /* Disable device, if desired. */ + pci_write_config16(lpc_dev, FUNC_DIS, reg16); } struct chip_operations southbridge_intel_i82801ax_ops = { Modified: trunk/src/southbridge/intel/i82801ax/i82801ax.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax.h Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax.h Fri Oct 8 21:24:56 2010 (r5925) @@ -26,37 +26,36 @@ extern void i82801ax_enable(device_t dev); #endif +#define SMBUS_IO_BASE 0x0f00 +#define PMBASE_ADDR 0x0400 +#define HPET_ADDR 0xfed00000 + #define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 #define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 +#define GEN_STA 0xd4 #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 #define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */ #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E -#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ -#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ -#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ -#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ +#define GPIO_BASE 0x58 /* GPIO Base Address Register */ +#define GPIO_CNTL 0x5C /* GPIO Control Register */ +#define GPIO_EN (1 << 4) #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 #define PIRQC_ROUT 0x62 #define PIRQD_ROUT 0x63 -#define PIRQE_ROUT 0x68 -#define PIRQF_ROUT 0x69 -#define PIRQG_ROUT 0x6A -#define PIRQH_ROUT 0x6B #define FUNC_DIS 0xF2 -#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ -#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ -#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ +#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */ +#define LPC_EN 0xE6 /* LPC IF Enables */ + +// TODO: FDC_DEC etc. #define SBUS_NUM 0x19 #define SUB_BUS_NUM 0x1A @@ -77,14 +76,14 @@ #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -/* PCI Configuration Space (D31:F1) */ +/* IDE Timing registers (IDE_TIM) */ #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ /* IDE_TIM bits */ #define IDE_DECODE_ENABLE (1 << 15) -/* PCI Configuration Space (D31:F3) */ +/* SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 @@ -93,13 +92,7 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* SMBus I/O bits. - * TODO: Does it matter where we put the SMBus IO base, as long as we keep - * consistent and don't interfere with anything else? - */ -/* #define SMBUS_IO_BASE 0x1000 */ -#define SMBUS_IO_BASE 0x0f00 - +/* SMBus I/O registers. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 #define SMBHSTCMD 0x3 @@ -107,14 +100,7 @@ #define SMBHSTDAT0 0x5 #define SMBHSTDAT1 0x6 #define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (10 * 1000 * 100) -/* HPET, if present */ -#define HPET_ADDR 0xfed00000 - -#endif /* SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H */ +#endif Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ac97.c Fri Oct 8 21:24:56 2010 (r5925) @@ -19,8 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code should work for all ICH* southbridges with AC97 audio/modem. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -61,4 +59,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM, }; - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 21:24:56 2010 (r5925) @@ -27,21 +27,10 @@ static void enable_smbus(void) { device_t dev; - uint16_t device_id; - /* Set the SMBus device statically. */ + /* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3); - /* Check to make sure we've got the right device. */ - device_id = pci_read_config16(dev, 0x2); - - /* Clear bits 7-4 (the only bits that vary between models). */ - device_id &= 0xff0f; - - if (device_id != 0x2403) { - die("Device not found, Corey probably screwed up!"); - } - /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_ide.c Fri Oct 8 21:24:56 2010 (r5925) @@ -31,33 +31,24 @@ static void ide_init(struct device *dev) { - /* Get the chip configuration */ - config_t *config = dev->chip_info; + u16 reg16; + config_t *conf = dev->chip_info; - /* Enable IDE devices so the Linux IDE driver will work. */ - uint16_t ideTimingConfig; - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide0_enable) { - /* Enable primary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); - - ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); - ideTimingConfig &= ~IDE_DECODE_ENABLE; - if (!config || config->ide1_enable) { - /* Enable secondary IDE interface. */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); - } else { - printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); - } - pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); + reg16 = pci_read_config16(dev, IDE_TIM_PRI); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide0_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_PRI, reg16); + + reg16 = pci_read_config16(dev, IDE_TIM_SEC); + reg16 &= ~IDE_DECODE_ENABLE; + if (!conf || conf->ide1_enable) + reg16 |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", + conf->ide0_enable ? "on" : "off"); + pci_write_config16(dev, IDE_TIM_SEC, reg16); } static struct device_operations ide_ops = { @@ -69,17 +60,16 @@ .enable = i82801ax_enable, }; -/* 82801AA */ +/* 82801AA (ICH) */ static const struct pci_driver i82801aa_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2411, }; -/* 82801AB */ +/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_ide __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2421, }; - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Fri Oct 8 21:24:56 2010 (r5925) @@ -36,7 +36,7 @@ typedef struct southbridge_intel_i82801ax_config config_t; -/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control +/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible) * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved * 0x02 - 0010 = Reserved @@ -53,8 +53,10 @@ * 0x0D - 1101 = Reserved * 0x0E - 1110 = IRQ14 * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. + * + * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN) + * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above. + * 1 - The PIRQ is not routed to the 8259. */ #define PIRQA 0x03 @@ -66,25 +68,24 @@ * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. -*/ - + */ static void i82801ax_enable_apic(struct device *dev) { - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; - volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; + volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); @@ -112,34 +113,22 @@ /* TODO: Explain/#define the real meaning of these magic numbers. */ } -static void i82801ax_pirq_init(device_t dev, uint16_t ich_model) +static void i82801ax_pirq_init(device_t dev) { - /* Get the chip configuration */ + u8 reg8; config_t *config = dev->chip_info; - if (config->pirqa_routing) { - pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); - } else { - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - } + reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA; + pci_write_config8(dev, PIRQA_ROUT, reg8); - if (config->pirqb_routing) { - pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); - } else { - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - } + reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB; + pci_write_config8(dev, PIRQB_ROUT, reg8); - if (config->pirqc_routing) { - pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); - } else { - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - } + reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC; + pci_write_config8(dev, PIRQC_ROUT, reg8); - if (config->pirqd_routing) { - pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); - } else { - pci_write_config8(dev, PIRQD_ROUT, PIRQD); - } + reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD; + pci_write_config8(dev, PIRQD_ROUT, reg8); } static void i82801ax_power_options(device_t dev) @@ -172,10 +161,10 @@ } } -static void gpio_init(device_t dev, uint16_t ich_model) +static void gpio_init(device_t dev) { - pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, GPIO_EN); } static void i82801ax_rtc_init(struct device *dev) @@ -190,7 +179,7 @@ reg8 &= ~(1 << 1); /* Preserve the power fail state. */ pci_write_config8(dev, GEN_PMCON_3, reg8); } - reg32 = pci_read_config32(dev, GEN_STS); + reg32 = pci_read_config32(dev, GEN_STA); rtc_failed |= reg32 & (1 << 2); rtc_init(rtc_failed); @@ -213,7 +202,7 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801ax_lpc_decode_en(device_t dev) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -221,13 +210,11 @@ * We also need to set the value for LPC I/F Enables Register. */ pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F); + pci_write_config16(dev, LPC_EN, 0x300F); } static void lpc_init(struct device *dev) { - uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); @@ -237,13 +224,13 @@ i82801ax_enable_serial_irqs(dev); /* Setup the PIRQ. */ - i82801ax_pirq_init(dev, ich_model); + i82801ax_pirq_init(dev); /* Setup power options. */ i82801ax_power_options(dev); /* Set the state of the GPIO lines. */ - gpio_init(dev, ich_model); + gpio_init(dev); /* Initialize the real time clock. */ i82801ax_rtc_init(dev); @@ -255,7 +242,7 @@ isa_dma_init(); /* Setup decode ports and LPC I/F enables. */ - i82801ax_lpc_decode_en(dev, ich_model); + i82801ax_lpc_decode_en(dev); } static void i82801ax_lpc_read_resources(device_t dev) @@ -293,15 +280,16 @@ .enable = i82801ax_enable, }; +/* 82801AA (ICH) */ static const struct pci_driver i82801aa_lpc __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2410, }; +/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_lpc __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2420, }; - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_pci.c Fri Oct 8 21:24:56 2010 (r5925) @@ -26,16 +26,12 @@ static void pci_init(struct device *dev) { - uint16_t reg16; + u16 reg16; - /* Clear system errors */ - reg16 = pci_read_config16(dev, 0x06); - reg16 |= 0xf900; /* Clear possible errors */ - pci_write_config16(dev, 0x06, reg16); - - reg16 = pci_read_config16(dev, 0x1e); - reg16 |= 0xf800; /* Clear possible errors */ - pci_write_config16(dev, 0x1e, reg16); + /* Clear possible errors. */ + reg16 = pci_read_config16(dev, PCI_STATUS); + reg16 |= 0xf900; + pci_write_config16(dev, PCI_STATUS, reg16); } static struct device_operations pci_ops = { @@ -46,15 +42,16 @@ .scan_bus = pci_scan_bridge, }; +/* 82801AA (ICH) */ static const struct pci_driver i82801aa_pci __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2418, }; +/* 82801AB (ICH0) */ static const struct pci_driver i82801ab_pci __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x2428, }; - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 21:24:56 2010 (r5925) @@ -66,4 +66,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_SMB, }; - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Fri Oct 8 18:40:23 2010 (r5924) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_usb.c Fri Oct 8 21:24:56 2010 (r5925) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This code should work for all ICH* southbridges with USB. */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -53,4 +51,3 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801AB_USB, }; -

1 0

[commit] r5924 - in trunk/src/southbridge/intel: i82801ax i82801bx
by repository service 08 Oct '10

08 Oct '10

Author: uwe Date: Fri Oct 8 18:40:23 2010 New Revision: 5924 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5924 Log: Intel 82801ax/82801bx: Fix and hook up i82801xx_smbus.c. - Fix incorrect #includes, add missing ones. - Drop unused do_smbus_write_block() and smbus_wait_until_blk_done(). - Pass smbus_io_base to all functions as the other ICH implementations do. - Random other fixes which are required to make it build. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h trunk/src/southbridge/intel/i82801bx/Makefile.inc trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Modified: trunk/src/southbridge/intel/i82801ax/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801ax/Makefile.inc Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801ax/Makefile.inc Fri Oct 8 18:40:23 2010 (r5924) @@ -23,11 +23,9 @@ driver-y += i82801ax_ide.c driver-y += i82801ax_lpc.c driver-y += i82801ax_pci.c -# driver-y += i82801ax_smbus.c +driver-y += i82801ax_smbus.c driver-y += i82801ax_usb.c ramstage-y += i82801ax_reset.c ramstage-y += i82801ax_watchdog.c -# TODO: Fix and enable i82801ax_smbus.o later. - Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_early_smbus.c Fri Oct 8 18:40:23 2010 (r5924) @@ -63,19 +63,6 @@ static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static void smbus_write_byte(unsigned device, unsigned address, - unsigned char val) -{ - print_err("Unimplemented smbus_write_byte() called\n"); - return; -} - -static inline int smbus_write_block(unsigned device, unsigned length, - unsigned cmd, unsigned data1, - unsigned data2) -{ - return do_smbus_write_block(device, length, cmd, data1, data2); -} Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.c Fri Oct 8 18:40:23 2010 (r5924) @@ -19,25 +19,28 @@ */ #include <stdint.h> -#include <smbus.h> -#include <pci.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> #include <arch/io.h> #include "i82801ax.h" -#include "i82801_smbus.h" +#include "i82801ax_smbus.h" -static int smbus_read_byte(struct bus *bus, device_t dev, u8 address) +static int lsmbus_read_byte(device_t dev, u8 address) { - unsigned device; /* TODO: u16? */ + u16 device; struct resource *res; + struct bus *pbus; device = dev->path.i2c.device; - res = find_resource(bus->dev, 0x20); + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); return do_smbus_read_byte(res->base, device, address); } static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = smbus_read_byte, + .read_byte = lsmbus_read_byte, }; static const struct device_operations smbus_ops = { @@ -46,7 +49,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801ax_enable, .ops_smbus_bus = &lops_smbus_bus, }; Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Fri Oct 8 18:40:23 2010 (r5924) @@ -25,7 +25,7 @@ inb(0x80); } -static int smbus_wait_until_ready(void) +static int smbus_wait_until_ready(u16 smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; @@ -33,12 +33,12 @@ smbus_delay(); if (--loops == 0) break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + byte = inb(smbus_io_base + SMBHSTSTAT); } while (byte & 1); return loops ? 0 : -1; } -static int smbus_wait_until_done(void) +static int smbus_wait_until_done(u16 smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; @@ -46,131 +46,54 @@ smbus_delay(); if (--loops == 0) break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + byte = inb(smbus_io_base + SMBHSTSTAT); } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); return loops ? 0 : -1; } -static int smbus_wait_until_blk_done(void) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } while ((byte & (1 << 7)) == 0); - return loops ? 0 : -1; -} - -static int do_smbus_read_byte(unsigned device, unsigned address) +static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, + unsigned address) { unsigned char global_status_register; unsigned char byte; - if (smbus_wait_until_ready() < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } /* Setup transaction */ /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL); /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); /* Set the command/address... */ - outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + outb(address & 0xff, smbus_io_base + SMBHSTCMD); /* Set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (SMBUS_IO_BASE + SMBHSTCTL)); + outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_io_base + SMBHSTCTL)); /* Clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT); /* Clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + outb(0, smbus_io_base + SMBHSTDAT0); /* Start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), + smbus_io_base + SMBHSTCTL); /* Poll for transaction completion */ - if (smbus_wait_until_done() < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + global_status_register = inb(smbus_io_base + SMBHSTSTAT); /* Ignore the "In Use" status... */ global_status_register &= ~(3 << 5); /* Read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + byte = inb(smbus_io_base + SMBHSTDAT0); if (global_status_register != (1 << 1)) { return SMBUS_ERROR; } return byte; } - -static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ - unsigned char byte; - unsigned char stat; - int i; - - print_err("Untested smbus_write_block called\n"); - - /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); - - if (smbus_wait_until_ready() < 0) { - return -2; - } - - /* Setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for (stat = 0; (stat & 0x40) == 0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* Clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* Set the command address */ - outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - - /* Set the block length */ - outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Try sending out the first byte of data here */ - byte = (data1 >> (0)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - /* Issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for (i = 0; i < length; i++) { - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done() < 0) { - return -3; - } - - /* Load the next byte */ - if (i > 3) - byte = (data2 >> (i % 4)) & 0x0ff; - else - byte = (data1 >> (i)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - - /* Clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -} Modified: trunk/src/southbridge/intel/i82801bx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801bx/Makefile.inc Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801bx/Makefile.inc Fri Oct 8 18:40:23 2010 (r5924) @@ -25,12 +25,10 @@ driver-y += i82801bx_nic.c driver-y += i82801bx_pci.c driver-y += i82801bx_sata.c -# driver-y += i82801bx_smbus.c +driver-y += i82801bx_smbus.c driver-y += i82801bx_usb.c driver-y += i82801bx_usb_ehci.c ramstage-y += i82801bx_reset.c ramstage-y += i82801bx_watchdog.c -# TODO: Fix and enable i82801bx_smbus.o later. - Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_early_smbus.c Fri Oct 8 18:40:23 2010 (r5924) @@ -63,5 +63,5 @@ static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.c Fri Oct 8 18:40:23 2010 (r5924) @@ -18,28 +18,29 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* TODO: Check datasheets if this will work for all ICH* southbridges. */ - #include <stdint.h> -#include <smbus.h> -#include <pci.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> #include <arch/io.h> #include "i82801bx.h" -#include "i82801_smbus.h" +#include "i82801bx_smbus.h" -static int smbus_read_byte(struct bus *bus, device_t dev, u8 address) +static int lsmbus_read_byte(device_t dev, u8 address) { - unsigned device; /* TODO: u16? */ + u16 device; struct resource *res; + struct bus *pbus; device = dev->path.i2c.device; - res = find_resource(bus->dev, 0x20); + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); return do_smbus_read_byte(res->base, device, address); } static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = smbus_read_byte, + .read_byte = lsmbus_read_byte, }; static const struct device_operations smbus_ops = { @@ -48,7 +49,7 @@ .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - .enable = i82801er_enable, + .enable = i82801bx_enable, .ops_smbus_bus = &lops_smbus_bus, }; Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Fri Oct 8 07:08:47 2010 (r5923) +++ trunk/src/southbridge/intel/i82801bx/i82801bx_smbus.h Fri Oct 8 18:40:23 2010 (r5924) @@ -25,7 +25,7 @@ inb(0x80); } -static int smbus_wait_until_ready(void) +static int smbus_wait_until_ready(u16 smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; @@ -33,12 +33,12 @@ smbus_delay(); if (--loops == 0) break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + byte = inb(smbus_io_base + SMBHSTSTAT); } while (byte & 1); return loops ? 0 : -1; } -static int smbus_wait_until_done(void) +static int smbus_wait_until_done(u16 smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; @@ -46,135 +46,54 @@ smbus_delay(); if (--loops == 0) break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + byte = inb(smbus_io_base + SMBHSTSTAT); } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); return loops ? 0 : -1; } -#ifdef UNUNSED_CODE -static int smbus_wait_until_blk_done(void) -{ - unsigned loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } while ((byte & (1 << 7)) == 0); - return loops ? 0 : -1; -} -#endif - -static int do_smbus_read_byte(unsigned device, unsigned address) +static int do_smbus_read_byte(u16 smbus_io_base, unsigned device, + unsigned address) { unsigned char global_status_register; unsigned char byte; - if (smbus_wait_until_ready() < 0) { + if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } /* Setup transaction */ /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + outb(inb(smbus_io_base + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD); /* Set the command/address... */ - outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + outb(address & 0xff, smbus_io_base + SMBHSTCMD); /* Set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (SMBUS_IO_BASE + SMBHSTCTL)); + outb((inb(smbus_io_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_io_base + SMBHSTCTL)); /* Clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + outb(inb(smbus_io_base + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* Clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + outb(0, smbus_io_base + SMBHSTDAT0); /* Start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); + outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), + smbus_io_base + SMBHSTCTL); /* Poll for transaction completion */ - if (smbus_wait_until_done() < 0) { + if (smbus_wait_until_done(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; } - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + global_status_register = inb(smbus_io_base + SMBHSTSTAT); /* Ignore the "In Use" status... */ global_status_register &= ~(3 << 5); /* Read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + byte = inb(smbus_io_base + SMBHSTDAT0); if (global_status_register != (1 << 1)) { return SMBUS_ERROR; } return byte; } - -#ifdef UNUNSED_CODE -static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, - unsigned data1, unsigned data2) -{ - unsigned char byte; - unsigned char stat; - int i; - - print_err("Untested smbus_write_block called\n"); - - /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); - - if (smbus_wait_until_ready() < 0) { - return -2; - } - - /* Setup transaction */ - /* Obtain ownership */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - for (stat = 0; (stat & 0x40) == 0;) { - stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); - } - /* Clear the done bit */ - outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); - /* Disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - - /* Set the command address */ - outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); - - /* Set the block length */ - outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); - - /* Try sending out the first byte of data here */ - byte = (data1 >> (0)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - /* Issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, - SMBUS_IO_BASE + SMBHSTCTL); - - for (i = 0; i < length; i++) { - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done() < 0) { - return -3; - } - - /* Load the next byte */ - if (i > 3) - byte = (data2 >> (i % 4)) & 0x0ff; - else - byte = (data1 >> (i)) & 0x0ff; - outb(byte, SMBUS_IO_BASE + SMBBLKDAT); - - /* Clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); - } - - print_debug("SMBUS Block complete\n"); - return 0; -} -#endif

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coreboot October 2010