coreboot October 2010

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316 discussions

[PATCH] Small refactoring in ioapic.c to simplify the code
by Uwe Hermann 17 Oct '10

17 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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another fintek for superiotool (was Re: [flashrom] [patch] EPoX EP-8NPA7I board enable)
by Jonathan A. Kollasch 16 Oct '10

16 Oct '10

On Sat, Oct 16, 2010 at 11:04:06AM +0200, Uwe Hermann wrote: > On Sat, Oct 16, 2010 at 01:03:11AM +0000, Jonathan A. Kollasch wrote: > > EP-8NPA7I. > > OK, thanks. > > > > Attached, my superiotool is locally modified for dumping this one. > > What modifications were needed? Should they be merged into superiotool? > Basically adding the list of registers and default values for the F71806/F71872 (one is apparently missing the KBC LDN, but both have the same chip ID). I'm not sure I have the defaults right at this point however. Jonathan Kollasch

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[PATCH] model_65x CPU support
by Keith Hui 16 Oct '10

16 Oct '10

Attached patch moves support for Deschutes Slot 1 CPUs (model_65x) into its own home. This is similar to the Katmai patch I submitted before, but without microcode this time. With 17 of them they will make the patch too large. I think I'll defer them for later or someone else*, hehe. :D abuild-tested. I have no Deschutes CPUs to boot test this with. Signed-off-by: Keith Hui <buurin(a)gmail.com> * also because I like to keep all microcodes for the same family within one file instead of one microcode per file.

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[commit] r5954 - in trunk/src/cpu/intel: model_65x slot_1
by repository service 16 Oct '10

16 Oct '10

Author: uwe Date: Sat Oct 16 10:45:31 2010 New Revision: 5954 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5954 Log: Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory. abuild-tested. I have no Deschutes CPUs to boot test this with. Signed-off-by: Keith Hui <buurin(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/cpu/intel/model_65x/ trunk/src/cpu/intel/model_65x/Kconfig trunk/src/cpu/intel/model_65x/Makefile.inc trunk/src/cpu/intel/model_65x/model_65x_init.c Modified: trunk/src/cpu/intel/slot_1/Makefile.inc Added: trunk/src/cpu/intel/model_65x/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_65x/Kconfig Sat Oct 16 10:45:31 2010 (r5954) @@ -0,0 +1,3 @@ +config CPU_INTEL_MODEL_65X + bool + select SMP Added: trunk/src/cpu/intel/model_65x/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_65x/Makefile.inc Sat Oct 16 10:45:31 2010 (r5954) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += model_65x_init.c + Added: trunk/src/cpu/intel/model_65x/model_65x_init.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_65x/model_65x_init.c Sat Oct 16 10:45:31 2010 (r5954) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> + +static u32 microcode_updates[] = { + + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static void model_65x_init(device_t dev) +{ + /* Turn on caching if we haven't already */ + x86_enable_cache(); + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = model_65x_init, +}; + +/* + * Intel Pentium II Processor Specification Update + * http://download.intel.com/design/PentiumII/specupdt/24333749.pdf + * + * Mobile Intel Pentium II Processor Specification Update + * http://download.intel.com/design/intarch/specupdt/24388757.pdf + * + * Intel Pentium II Xeon Processor Specification Update + * http://download.intel.com/support/processors/pentiumii/xeon/24377632.pdf + */ +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x0650 }, /* PII/Celeron, dA0/mdA0/A0 */ + { X86_VENDOR_INTEL, 0x0651 }, /* PII/Celeron, dA1/A1 */ + { X86_VENDOR_INTEL, 0x0652 }, /* PII/Celeron/Xeon, dB0/mdB0/B0 */ + { X86_VENDOR_INTEL, 0x0653 }, /* PII/Xeon, dB1/B1 */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; Modified: trunk/src/cpu/intel/slot_1/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/slot_1/Makefile.inc Fri Oct 15 09:47:51 2010 (r5953) +++ trunk/src/cpu/intel/slot_1/Makefile.inc Sat Oct 16 10:45:31 2010 (r5954) @@ -20,6 +20,7 @@ ramstage-y += slot_1.c subdirs-y += ../model_6xx +subdirs-y += ../model_65x subdirs-y += ../model_67x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc

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Re: [coreboot] coreboot support for AMD HT3
by Maximilian Thuermer 16 Oct '10

16 Oct '10

Scott Duplichan wrote: > > At 1600x1200, 16-bit color is almost perfect. But the same > > resolution with 32-bit color results in a display that jumps so > > much it cannot be read. Why would 32-bit color make a difference? > Twice the bandwidth needed to get the graphics data out of RAM. > > I am thinking that refreshing 1600x1200 pixels 60 times per second > > takes a lot data, and that data has to cross the HT link. True > > color takes more data than high color, and true color may be > > exceeding the capacity of the cpu-RS780 link. The link is running > > at the slowest possible setting, 200 MHz, 8-bit. > Ouch! :\ That would seem to cause the problem. Can't say about HT3 I'm afraid. //Peter Hi Scott, HT3 is all there and working perfectly as long as it is between two CPUS or CPU and HTX expansion slot. I noticed frequencies not being set correctly in HT init for Southbridge links, all other links seem to run at their optimal speed. Normally, Southbridges support HT1 frequencies up to HT1000 which should be sufficient for your problem to vanish. Either you try overwriting the coreboot settings manually on CPU and SB side (HT Specification and BKDG should help here) or you try to fix the problem at its root which is that the Southbridge capability registers do not seem to get read out alright by the HT init procedures. Best regards, Maximilian Thuermer

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[commit] r5953 - in trunk/src/cpu/intel: slot_1 slot_2 socket_FC_PGA370 socket_PGA370
by repository service 15 Oct '10

15 Oct '10

Author: uwe Date: Fri Oct 15 09:47:51 2010 New Revision: 5953 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5953 Log: Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/intel/slot_1/Kconfig trunk/src/cpu/intel/slot_2/Kconfig trunk/src/cpu/intel/socket_FC_PGA370/Kconfig trunk/src/cpu/intel/socket_PGA370/Kconfig Modified: trunk/src/cpu/intel/slot_1/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_1/Kconfig Fri Oct 15 01:40:10 2010 (r5952) +++ trunk/src/cpu/intel/slot_1/Kconfig Fri Oct 15 09:47:51 2010 (r5953) @@ -21,11 +21,6 @@ bool select CACHE_AS_RAM -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_1 - config DCACHE_RAM_SIZE hex default 0x01000 Modified: trunk/src/cpu/intel/slot_2/Kconfig ============================================================================== --- trunk/src/cpu/intel/slot_2/Kconfig Fri Oct 15 01:40:10 2010 (r5952) +++ trunk/src/cpu/intel/slot_2/Kconfig Fri Oct 15 09:47:51 2010 (r5953) @@ -20,11 +20,6 @@ config CPU_INTEL_SLOT_2 bool -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_2 - config DCACHE_RAM_SIZE hex default 0x01000 Modified: trunk/src/cpu/intel/socket_FC_PGA370/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_FC_PGA370/Kconfig Fri Oct 15 01:40:10 2010 (r5952) +++ trunk/src/cpu/intel/socket_FC_PGA370/Kconfig Fri Oct 15 09:47:51 2010 (r5953) @@ -26,11 +26,6 @@ select CACHE_AS_RAM select TINY_BOOTBLOCK -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - depends on CPU_INTEL_SOCKET_FC_PGA370 - config DCACHE_RAM_SIZE hex default 0x8000 Modified: trunk/src/cpu/intel/socket_PGA370/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_PGA370/Kconfig Fri Oct 15 01:40:10 2010 (r5952) +++ trunk/src/cpu/intel/socket_PGA370/Kconfig Fri Oct 15 09:47:51 2010 (r5953) @@ -30,10 +30,6 @@ bool default n -config DCACHE_RAM_BASE - hex - default 0xc0000 - config DCACHE_RAM_SIZE hex default 0x01000

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[PATCH] Convert all Intel i810 boards to CAR
by Uwe Hermann 15 Oct '10

15 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

10 19

[PATCH] Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets
by Uwe Hermann 15 Oct '10

15 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

3 2

[commit] r5952 - trunk/src/arch/i386/lib
by repository service 15 Oct '10

15 Oct '10

Author: uwe Date: Fri Oct 15 01:40:10 2010 New Revision: 5952 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5952 Log: Cosmetics in ioapic.c (trivial, no functional changes). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/arch/i386/lib/ioapic.c Modified: trunk/src/arch/i386/lib/ioapic.c ============================================================================== --- trunk/src/arch/i386/lib/ioapic.c Thu Oct 14 01:00:41 2010 (r5951) +++ trunk/src/arch/i386/lib/ioapic.c Fri Oct 15 01:40:10 2010 (r5952) @@ -34,7 +34,6 @@ write32(ioapic_base + 0x10, value); } - void clear_ioapic(u32 ioapic_base) { u32 low, high; @@ -42,8 +41,8 @@ printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); - /* Read the available number of interrupts */ - ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + /* Read the available number of interrupts. */ + ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); @@ -55,11 +54,12 @@ io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", + i, high, low); } if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { - printk(BIOS_WARNING, "IO APIC not responding.\n"); + printk(BIOS_WARNING, "IOAPIC not responding.\n"); return; } } @@ -70,25 +70,25 @@ u32 low, high; u32 i, ioapic_interrupts; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", - bsp_lapicid); + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", + bsp_lapicid); if (ioapic_id) { printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); - /* Set IOAPIC ID if it has been specified */ + /* Set IOAPIC ID if it has been specified. */ io_apic_write(ioapic_base, 0x00, (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | - (ioapic_id << 24)); + (ioapic_id << 24)); } - /* Read the available number of interrupts */ - ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + /* Read the available number of interrupts. */ + ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); - // XXX this decision should probably be made elsewhere, and // it's the C3, not the EPIA this depends on. #if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT @@ -98,18 +98,20 @@ #endif #ifdef IOAPIC_INTERRUPTS_ON_FSB - /* For the Pentium 4 and above APICs deliver their interrupts + /* + * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. */ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); + io_apic_write(ioapic_base, 0x03, + io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif - /* Enable Virtual Wire Mode */ + /* Enable Virtual Wire Mode. */ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); @@ -117,11 +119,12 @@ io_apic_write(ioapic_base, 0x11, high); if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { - printk(BIOS_WARNING, "IO APIC not responding.\n"); + printk(BIOS_WARNING, "IOAPIC not responding.\n"); return; } - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", + 0, high, low); low = DISABLED; high = NONE; @@ -130,6 +133,7 @@ io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", + i, high, low); } }

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Re: [coreboot] CarPC project, with MB899 MB
by Peter Stuge 14 Oct '10

14 Oct '10

(Please remember to trim the quoted text when replying.) Nasa wrote: > > > If my goal is the fastest boot time possible, while still > > > supporting the basic system, would going to a Linux payload be the > > > way to go? > > > > Maybe, but maybe not. If you are using flash media which does not > > have a spin-up delay then it might actually be faster for another > > payload to load the kernel off the drive using DMA. > > I am indeed using an SSD drive to boot my system. Ok, then you have more options. Try them out and see which one is the fastest. :) > I also noted that my motherboard isn't supported for full linux > kernel install anyways. Sorry, what do you mean here? //Peter

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coreboot October 2010