coreboot October 2010

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[commit] r5962 - in trunk/src: devices include/device
by repository service 18 Oct '10

18 Oct '10

Author: uwe Date: Mon Oct 18 02:00:57 2010 New Revision: 5962 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5962 Log: Cosmetics and coding style fixes in devices/*. - Whitespace and indentation fixes in various places. - Fix various typos. - Use u8, u16 etc. everywhere. Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/devices/cardbus_device.c trunk/src/devices/pciexp_device.c trunk/src/devices/pcix_device.c trunk/src/devices/pnp_device.c trunk/src/devices/root_device.c trunk/src/devices/smbus_ops.c trunk/src/include/device/pciexp.h trunk/src/include/device/pcix.h trunk/src/include/device/pnp.h trunk/src/include/device/smbus.h Modified: trunk/src/devices/cardbus_device.c ============================================================================== --- trunk/src/devices/cardbus_device.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/cardbus_device.c Mon Oct 18 02:00:57 2010 (r5962) @@ -25,28 +25,30 @@ #include <device/pci_ids.h> #include <device/cardbus.h> -/* I don't think this code is quite correct but it is close. +/* + * I don't think this code is quite correct but it is close. * Anyone with a cardbus bridge and a little time should be able * to make it usable quickly. -- Eric Biederman 24 March 2005 */ /* - * IO should be max 256 bytes. However, since we may - * have a P2P bridge below a cardbus bridge, we need 4K. + * IO should be max 256 bytes. However, since we may have a P2P bridge below + * a cardbus bridge, we need 4K. */ -#define CARDBUS_IO_SIZE (4096) -#define CARDBUS_MEM_SIZE (32*1024*1024) +#define CARDBUS_IO_SIZE 4096 +#define CARDBUS_MEM_SIZE (32 * 1024 * 1024) -static void cardbus_record_bridge_resource( - device_t dev, resource_t moving, resource_t min_size, - unsigned index, unsigned long type) +static void cardbus_record_bridge_resource(device_t dev, resource_t moving, + resource_t min_size, unsigned int index, unsigned long type) { - /* Initialize the constraints on the current bus. */ struct resource *resource; + + /* Initialize the constraints on the current bus. */ resource = NULL; if (moving) { unsigned long gran; resource_t step; + resource = new_resource(dev, index); resource->size = 0; gran = 0; @@ -59,30 +61,33 @@ resource->align = gran; resource->limit = moving | (step - 1); resource->flags = type; - /* Don't let the minimum size exceed what we + + /* + * Don't let the minimum size exceed what we * can put in the resource. */ - if ((min_size - 1) > resource->limit) { + if ((min_size - 1) > resource->limit) min_size = resource->limit + 1; - } + resource->size = min_size; } return; } -static void cardbus_size_bridge_resource(device_t dev, unsigned index) +static void cardbus_size_bridge_resource(device_t dev, unsigned int index) { struct resource *resource; resource_t min_size; + resource = find_resource(dev, index); if (resource) { min_size = resource->size; - /* Allways allocate at least the miniumum size to a + /* + * Always allocate at least the miniumum size to a * cardbus bridge in case a new card is plugged in. */ - if (resource->size < min_size) { + if (resource->size < min_size) resource->size = min_size; - } } } @@ -90,34 +95,34 @@ { resource_t moving_base, moving_limit, moving; unsigned long type; - uint16_t ctl; + u16 ctl; - /* See if needs a card control registers base address */ + /* See if needs a card control registers base address. */ pci_get_resource(dev, PCI_BASE_ADDRESS_0); compact_resources(dev); - /* See which bridge I/O resources are implemented */ - moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0); + /* See which bridge I/O resources are implemented. */ + moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0); moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0); moving = moving_base & moving_limit; - /* Initialize the io space constraints on the current bus */ + /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_0, IORESOURCE_IO); + PCI_CB_IO_BASE_0, IORESOURCE_IO); cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); - /* See which bridge I/O resources are implemented */ - moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); + /* See which bridge I/O resources are implemented. */ + moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1); moving = moving_base & moving_limit; - /* Initialize the io space constraints on the current bus */ + /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_1, IORESOURCE_IO); + PCI_CB_IO_BASE_1, IORESOURCE_IO); - /* If I can enable prefetch for mem0 */ + /* If I can, enable prefetch for mem0. */ ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; @@ -125,30 +130,28 @@ pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl); ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); - /* See which bridge memory resources are implemented */ - moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0); + /* See which bridge memory resources are implemented. */ + moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0); moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0); moving = moving_base & moving_limit; - /* Initialize the memory space constraints on the current bus */ + /* Initialize the memory space constraints on the current bus. */ type = IORESOURCE_MEM; - if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { + if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) type |= IORESOURCE_PREFETCH; - } cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_0, type); - if (type & IORESOURCE_PREFETCH) { + PCI_CB_MEMORY_BASE_0, type); + if (type & IORESOURCE_PREFETCH) cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); - } - /* See which bridge memory resources are implemented */ - moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); + /* See which bridge memory resources are implemented. */ + moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1); moving = moving_base & moving_limit; - /* Initialize the memory space constraints on the current bus */ + /* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); + PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); compact_resources(dev); @@ -156,7 +159,8 @@ void cardbus_enable_resources(device_t dev) { - uint16_t ctrl; + u16 ctrl; + ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctrl |= (dev->link_list->bridge_ctrl & ( PCI_BRIDGE_CTL_PARITY | @@ -165,7 +169,8 @@ PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_MASTER_ABORT | PCI_BRIDGE_CTL_BUS_RESET)); - ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); /* error check */ + /* Error check */ + ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); @@ -176,8 +181,8 @@ .read_resources = cardbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, + .init = 0, + .scan_bus = pci_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, }; Modified: trunk/src/devices/pciexp_device.c ============================================================================== --- trunk/src/devices/pciexp_device.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/pciexp_device.c Mon Oct 18 02:00:57 2010 (r5962) @@ -26,13 +26,12 @@ static void pciexp_tune_dev(device_t dev) { - unsigned cap; + unsigned int cap; cap = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (!cap) { - /* error... */ + if (!cap) return; - } + #ifdef CONFIG_PCIE_TUNING printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); @@ -45,16 +44,16 @@ #endif } -unsigned int pciexp_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, - unsigned int max) +unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn, unsigned int max) { device_t child; + max = pci_scan_bus(bus, min_devfn, max_devfn, max); - for(child = bus->children; child; child = child->sibling) { - if ( (child->path.pci.devfn < min_devfn) || - (child->path.pci.devfn > max_devfn)) - { + + for (child = bus->children; child; child = child->sibling) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pciexp_tune_dev(child); @@ -76,8 +75,8 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pciexp_scan_bridge, + .init = 0, + .scan_bus = pciexp_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pciexp_bus_ops_pci, Modified: trunk/src/devices/pcix_device.c ============================================================================== --- trunk/src/devices/pcix_device.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/pcix_device.c Mon Oct 18 02:00:57 2010 (r5962) @@ -26,20 +26,21 @@ static void pcix_tune_dev(device_t dev) { - unsigned cap; - unsigned status, orig_cmd, cmd; - unsigned max_read, max_tran; + u32 status; + u16 orig_cmd, cmd; + unsigned int cap, max_read, max_tran; - if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) { + if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) return; - } + cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (!cap) { + if (!cap) return; - } + printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev)); + status = pci_read_config32(dev, cap + PCI_X_STATUS); - orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); + orig_cmd = cmd = pci_read_config16(dev, cap + PCI_X_CMD); max_read = (status & PCI_X_STATUS_MAX_READ) >> 21; max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23; @@ -51,23 +52,26 @@ cmd &= ~PCI_X_CMD_MAX_SPLIT; cmd |= max_tran << 4; } - /* Don't attempt to handle PCI-X errors */ + + /* Don't attempt to handle PCI-X errors. */ cmd &= ~PCI_X_CMD_DPERR_E; - /* Enable Relaxed Ordering */ + + /* Enable Relaxed Ordering. */ cmd |= PCI_X_CMD_ERO; - if (orig_cmd != cmd) { + + if (orig_cmd != cmd) pci_write_config16(dev, cap + PCI_X_CMD, cmd); - } } static void pcix_tune_bus(struct bus *bus) { device_t child; - for(child = bus->children; child; child = child->sibling) + + for (child = bus->children; child; child = child->sibling) pcix_tune_dev(child); } -const char *pcix_speed(unsigned sstatus) +const char *pcix_speed(u16 sstatus) { static const char conventional[] = "Conventional PCI"; static const char pcix_66mhz[] = "66MHz PCI-X"; @@ -76,10 +80,11 @@ static const char pcix_266mhz[] = "266MHz PCI-X"; static const char pcix_533mhz[] = "533MHZ PCI-X"; static const char unknown[] = "Unknown"; - const char *result; + result = unknown; - switch(PCI_X_SSTATUS_MFREQ(sstatus)) { + + switch (PCI_X_SSTATUS_MFREQ(sstatus)) { case PCI_X_SSTATUS_CONVENTIONAL_PCI: result = conventional; break; @@ -89,17 +94,14 @@ case PCI_X_SSTATUS_MODE1_100MHZ: result = pcix_100mhz; break; - case PCI_X_SSTATUS_MODE1_133MHZ: result = pcix_133mhz; break; - case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ: result = pcix_266mhz; break; - case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ: case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ: @@ -111,20 +113,21 @@ unsigned int pcix_scan_bridge(device_t dev, unsigned int max) { - unsigned pos; - unsigned sstatus; + unsigned int pos; + u16 sstatus; max = do_pci_scan_bridge(dev, max, pci_scan_bus); - /* Find the PCI-X capability */ + + /* Find the PCI-X capability. */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS); - if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI) { + if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI) pcix_tune_bus(dev->link_list); - } - /* Print the PCI-X bus speed */ - printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, pcix_speed(sstatus)); + /* Print the PCI-X bus speed. */ + printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, + pcix_speed(sstatus)); return max; } @@ -138,8 +141,8 @@ .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pcix_scan_bridge, + .init = 0, + .scan_bus = pcix_scan_bridge, .enable = 0, .reset_bus = pci_bus_reset, .ops_pci = &pcix_bus_ops_pci, Modified: trunk/src/devices/pnp_device.c ============================================================================== --- trunk/src/devices/pnp_device.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/pnp_device.c Mon Oct 18 02:00:57 2010 (r5962) @@ -32,13 +32,13 @@ /* PNP fundamental operations */ -void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +void pnp_write_config(device_t dev, u8 reg, u8 value) { outb(reg, dev->path.pnp.port); outb(value, dev->path.pnp.port + 1); } -uint8_t pnp_read_config(device_t dev, uint8_t reg) +u8 pnp_read_config(device_t dev, u8 reg) { outb(reg, dev->path.pnp.port); return inb(dev->path.pnp.port + 1); @@ -51,45 +51,49 @@ void pnp_set_enable(device_t dev, int enable) { - uint8_t tmp, bitpos; + u8 tmp, bitpos; tmp = pnp_read_config(dev, 0x30); - /* handle the virtual devices, which share same LDN register */ + + /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; - if (enable) { + if (enable) tmp |= (1 << bitpos); - } else { + else tmp &= ~(1 << bitpos); - } + pnp_write_config(dev, 0x30, tmp); } int pnp_read_enable(device_t dev) { - uint8_t tmp, bitpos; + u8 tmp, bitpos; + tmp = pnp_read_config(dev, 0x30); - /* handle the virtual devices, which share same LDN register */ + + /* Handle virtual devices, which share the same LDN register. */ bitpos = (dev->path.pnp.device >> 8) & 0x7; + return !!(tmp & (1 << bitpos)); } -void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +void pnp_set_iobase(device_t dev, u8 index, u16 iobase) { - /* Index == 0x60 or 0x62 */ + /* Index == 0x60 or 0x62. */ pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); pnp_write_config(dev, index + 1, iobase & 0xff); } -void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +void pnp_set_irq(device_t dev, u8 index, u8 irq) { - /* Index == 0x70 or 0x72 */ + /* Index == 0x70 or 0x72. */ pnp_write_config(dev, index, irq); } -void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +void pnp_set_drq(device_t dev, u8 index, u8 drq) { - /* Index == 0x74 */ + /* Index == 0x74. */ pnp_write_config(dev, index, drq & 0xff); } @@ -103,26 +107,22 @@ static void pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", - dev_path(dev), resource->index, - resource_type(resource), - resource->size); + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx " + "not assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); return; } - /* Now store the resource */ + /* Now store the resource. */ if (resource->flags & IORESOURCE_IO) { pnp_set_iobase(dev, resource->index, resource->base); - } - else if (resource->flags & IORESOURCE_DRQ) { + } else if (resource->flags & IORESOURCE_DRQ) { pnp_set_drq(dev, resource->index, resource->base); - } - else if (resource->flags & IORESOURCE_IRQ) { + } else if (resource->flags & IORESOURCE_IRQ) { pnp_set_irq(dev, resource->index, resource->base); - } - else { + } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; @@ -134,13 +134,12 @@ { struct resource *res; - /* Select the device */ + /* Select the logical device (LDN). */ pnp_set_logical_device(dev); /* Paranoia says I should disable the device here... */ - for(res = dev->resource_list; res; res = res->next) { + for (res = dev->resource_list; res; res = res->next) pnp_set_resource(dev, res); - } } void pnp_enable_resources(device_t dev) @@ -166,39 +165,45 @@ /* PNP chip opertations */ -static void pnp_get_ioresource(device_t dev, unsigned index, struct io_info *info) +static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info) { struct resource *resource; unsigned moving, gran, step; resource = new_resource(dev, index); - /* Initilize the resource */ + /* Initilize the resource. */ resource->limit = 0xffff; resource->flags |= IORESOURCE_IO; - /* Get the resource size */ + /* Get the resource size... */ + moving = info->mask; gran = 15; step = 1 << gran; - /* Find the first bit that moves */ - while((moving & step) == 0) { + + /* Find the first bit that moves. */ + while ((moving & step) == 0) { gran--; step >>= 1; } - /* Now find the first bit that does not move */ - while((moving & step) != 0) { + + /* Now find the first bit that does not move. */ + while ((moving & step) != 0) { gran--; step >>= 1; } - /* Of the moving bits the last bit in the first group, + + /* + * Of the moving bits the last bit in the first group, * tells us the size of this resource. */ if ((moving & step) == 0) { gran++; step <<= 1; } - /* Set the resource size and alignment */ + + /* Set the resource size and alignment. */ resource->gran = gran; resource->align = gran; resource->limit = info->mask | (step - 1); @@ -241,8 +246,10 @@ resource->size = 1; resource->flags |= IORESOURCE_DRQ; } - /* These are not IRQs, but set the flag to have the - * resource allocator do the right thing + + /* + * These are not IRQs, but set the flag to have the + * resource allocator do the right thing. */ if (info->flags & PNP_EN) { resource = new_resource(dev, PNP_IDX_EN); @@ -262,17 +269,17 @@ } void pnp_enable_devices(device_t base_dev, struct device_operations *ops, - unsigned functions, struct pnp_info *info) + unsigned int functions, struct pnp_info *info) { struct device_path path; device_t dev; int i; - path.type = DEVICE_PATH_PNP; + path.type = DEVICE_PATH_PNP; path.pnp.port = base_dev->path.pnp.port; - /* Setup the ops and resources on the newly allocated devices */ - for(i = 0; i < functions; i++) { + /* Setup the ops and resources on the newly allocated devices. */ + for (i = 0; i < functions; i++) { /* Skip logical devices this Super I/O doesn't have. */ if (info[i].function == -1) continue; @@ -280,15 +287,15 @@ path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path); - /* Don't initialize a device multiple times */ + /* Don't initialize a device multiple times. */ if (dev->ops) continue; - if (info[i].ops == 0) { + if (info[i].ops == 0) dev->ops = ops; - } else { + else dev->ops = info[i].ops; - } + get_resources(dev, &info[i]); } } Modified: trunk/src/devices/root_device.c ============================================================================== --- trunk/src/devices/root_device.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/root_device.c Mon Oct 18 02:00:57 2010 (r5962) @@ -71,40 +71,42 @@ * * @param bus Pointer to the device to which the static buses are attached to. * @param max Maximum bus number currently used before scanning. - * @return Largest bus number used. + * @return The largest bus number used. */ static int smbus_max = 0; unsigned int scan_static_bus(device_t bus, unsigned int max) { device_t child; - struct bus* link; + struct bus *link; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for(link = bus->link_list; link; link = link->next) { - /* for smbus bus enumerate */ + for (link = bus->link_list; link; link = link->next) { + /* For SMBus bus enumerate. */ child = link->children; - if(child && child->path.type == DEVICE_PATH_I2C) { + + if (child && child->path.type == DEVICE_PATH_I2C) link->secondary = ++smbus_max; - } - for(child =link->children; child; child = child->sibling) { - if (child->chip_ops && child->chip_ops->enable_dev) { + + for (child = link->children; child; child = child->sibling) { + if (child->chip_ops && child->chip_ops->enable_dev) child->chip_ops->enable_dev(child); - } - if (child->ops && child->ops->enable) { + + if (child->ops && child->ops->enable) child->ops->enable(child); + + if (child->path.type == DEVICE_PATH_I2C) { + printk(BIOS_DEBUG, "smbus: %s[%d]->", + dev_path(child->bus->dev), + child->bus->link_num); } - if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), child->bus->link_num ); - } - printk(BIOS_DEBUG, "%s %s\n", - dev_path(child), - child->enabled?"enabled": "disabled"); + printk(BIOS_DEBUG, "%s %s\n", dev_path(child), + child->enabled ? "enabled" : "disabled"); } } - for(link = bus->link_list; link; link = link->next) { - for(child = link->children; child; child = child->sibling) { + + for (link = bus->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { if (!child->ops || !child->ops->scan_bus) continue; printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); @@ -128,7 +130,7 @@ * * @param root The root device structure. * @param max The current bus number scanned so far, usually 0x00. - * @return TODO. + * @return The largest bus number used. */ static unsigned int root_dev_scan_bus(device_t root, unsigned int max) { @@ -141,7 +143,7 @@ static void root_dev_reset(struct bus *bus) { - printk(BIOS_INFO, "Reseting board...\n"); + printk(BIOS_INFO, "Resetting board...\n"); hard_reset(); } Modified: trunk/src/devices/smbus_ops.c ============================================================================== --- trunk/src/devices/smbus_ops.c Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/devices/smbus_ops.c Mon Oct 18 02:00:57 2010 (r5962) @@ -28,13 +28,17 @@ struct bus *get_pbus_smbus(device_t dev) { struct bus *pbus = dev->bus; - while (pbus && pbus->dev && !ops_smbus_bus(pbus)) { + + while (pbus && pbus->dev && !ops_smbus_bus(pbus)) pbus = pbus->dev->bus; - } - if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) { - printk(BIOS_ALERT, "%s Cannot find smbus bus operations", dev_path(dev)); + + if (!pbus || !pbus->dev || !pbus->dev->ops + || !pbus->dev->ops->ops_smbus_bus) { + printk(BIOS_ALERT, "%s Cannot find SMBus bus operations", + dev_path(dev)); die(""); } + return pbus; } @@ -50,67 +54,84 @@ int smbus_set_link(device_t dev) { struct bus *pbus_a[4]; // 4 level mux only. Enough? - struct bus *pbus = dev->bus; - int pbus_num=0; + struct bus *pbus = dev->bus; + int pbus_num = 0; int i; - while(pbus && pbus->dev && (pbus->dev->path.type==DEVICE_PATH_I2C)) { + + while (pbus && pbus->dev && (pbus->dev->path.type == DEVICE_PATH_I2C)) { pbus_a[pbus_num++] = pbus; - pbus = pbus->dev->bus; - } -// printk(BIOS_INFO, "smbus_set_link: "); - for (i=pbus_num-1; i>=0; i--) { -// printk(BIOS_INFO, " %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link); - if (ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) { - if (pbus_a[i]->dev->ops && pbus_a[i]->dev->ops->set_link) - pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link_num); + pbus = pbus->dev->bus; + } + + // printk(BIOS_INFO, "smbus_set_link: "); + for (i = pbus_num - 1; i >= 0; i--) { + // printk(BIOS_INFO, " %s[%d] -> ", dev_path(pbus_a[i]->dev), + // pbus_a[i]->link); + if (ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) { + if (pbus_a[i]->dev->ops + && pbus_a[i]->dev->ops->set_link) + pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, + pbus_a[i]->link_num); } } -// printk(BIOS_INFO, " %s\n", dev_path(dev)); + // printk(BIOS_INFO, " %s\n", dev_path(dev)); - return pbus_num; + return pbus_num; } int smbus_quick_read(device_t dev) { return ops_smbus_bus(get_pbus_smbus(dev))->quick_read(dev); } + int smbus_quick_write(device_t dev) { return ops_smbus_bus(get_pbus_smbus(dev))->quick_write(dev); } + int smbus_recv_byte(device_t dev) { return ops_smbus_bus(get_pbus_smbus(dev))->recv_byte(dev); } -int smbus_send_byte(device_t dev, uint8_t byte) + +int smbus_send_byte(device_t dev, u8 byte) { return ops_smbus_bus(get_pbus_smbus(dev))->send_byte(dev, byte); } -int smbus_read_byte(device_t dev, uint8_t addr) + +int smbus_read_byte(device_t dev, u8 addr) { return ops_smbus_bus(get_pbus_smbus(dev))->read_byte(dev, addr); } -int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val) + +int smbus_write_byte(device_t dev, u8 addr, u8 val) { return ops_smbus_bus(get_pbus_smbus(dev))->write_byte(dev, addr, val); } -int smbus_read_word(device_t dev, uint8_t addr) + +int smbus_read_word(device_t dev, u8 addr) { return ops_smbus_bus(get_pbus_smbus(dev))->read_word(dev, addr); } -int smbus_write_word(device_t dev, uint8_t addr, uint16_t val) + +int smbus_write_word(device_t dev, u8 addr, u16 val) { return ops_smbus_bus(get_pbus_smbus(dev))->write_word(dev, addr, val); } -int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data) + +int smbus_process_call(device_t dev, u8 cmd, u16 data) { return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data); } -int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer) + +int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) { - return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, bytes, buffer); + return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, + bytes, buffer); } -int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer) + +int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer) { - return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, bytes, buffer); + return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, + bytes, buffer); } Modified: trunk/src/include/device/pciexp.h ============================================================================== --- trunk/src/include/device/pciexp.h Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/include/device/pciexp.h Mon Oct 18 02:00:57 2010 (r5962) @@ -2,8 +2,8 @@ #define DEVICE_PCIEXP_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pciexp_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max); +unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); extern struct device_operations default_pciexp_ops_bus; Modified: trunk/src/include/device/pcix.h ============================================================================== --- trunk/src/include/device/pcix.h Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/include/device/pcix.h Mon Oct 18 02:00:57 2010 (r5962) @@ -2,10 +2,10 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max); +unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn, unsigned int max); unsigned int pcix_scan_bridge(device_t dev, unsigned int max); -const char *pcix_speed(unsigned sstatus); +const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; Modified: trunk/src/include/device/pnp.h ============================================================================== --- trunk/src/include/device/pnp.h Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/include/device/pnp.h Mon Oct 18 02:00:57 2010 (r5962) @@ -5,15 +5,15 @@ #include <device/device.h> #include <device/pnp_def.h> -/* Primitive pnp resource manipulation */ -void pnp_write_config(device_t dev, uint8_t reg, uint8_t value); -uint8_t pnp_read_config(device_t dev, uint8_t reg); -void pnp_set_logical_device(device_t dev); -void pnp_set_enable(device_t dev, int enable); -int pnp_read_enable(device_t dev); -void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase); -void pnp_set_irq(device_t dev, unsigned index, unsigned irq); -void pnp_set_drq(device_t dev, unsigned index, unsigned drq); +/* Primitive PNP resource manipulation */ +void pnp_write_config(device_t dev, u8 reg, u8 value); +u8 pnp_read_config(device_t dev, u8 reg); +void pnp_set_logical_device(device_t dev); +void pnp_set_enable(device_t dev, int enable); +int pnp_read_enable(device_t dev); +void pnp_set_iobase(device_t dev, u8 index, u16 iobase); +void pnp_set_irq(device_t dev, u8 index, u8 irq); +void pnp_set_drq(device_t dev, u8 index, u8 drq); /* PNP device operations */ void pnp_read_resources(device_t dev); @@ -31,8 +31,8 @@ struct pnp_info { struct device_operations *ops; - unsigned function; - unsigned flags; + unsigned int function; + unsigned int flags; #define PNP_IO0 0x001 #define PNP_IO1 0x002 #define PNP_IO2 0x004 @@ -48,6 +48,6 @@ }; struct resource *pnp_get_resource(device_t dev, unsigned index); void pnp_enable_devices(struct device *dev, struct device_operations *ops, - unsigned functions, struct pnp_info *info); + unsigned int functions, struct pnp_info *info); #endif /* DEVICE_PNP_H */ Modified: trunk/src/include/device/smbus.h ============================================================================== --- trunk/src/include/device/smbus.h Mon Oct 18 01:55:17 2010 (r5961) +++ trunk/src/include/device/smbus.h Mon Oct 18 02:00:57 2010 (r5962) @@ -6,44 +6,45 @@ #include <device/path.h> #include <device/smbus_def.h> -/* Common smbus bus operations */ +/* Common SMBus bus operations */ struct smbus_bus_operations { int (*quick_read) (device_t dev); int (*quick_write) (device_t dev); int (*recv_byte) (device_t dev); - int (*send_byte) (device_t dev, uint8_t value); - int (*read_byte) (device_t dev, uint8_t addr); - int (*write_byte) (device_t dev, uint8_t addr, uint8_t value); - int (*read_word) (device_t dev, uint8_t addr); - int (*write_word) (device_t dev, uint8_t addr, uint16_t value); - int (*process_call)(device_t dev, uint8_t cmd, uint16_t data); - int (*block_read) (device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer); - int (*block_write) (device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer); + int (*send_byte) (device_t dev, u8 value); + int (*read_byte) (device_t dev, u8 addr); + int (*write_byte) (device_t dev, u8 addr, u8 value); + int (*read_word) (device_t dev, u8 addr); + int (*write_word) (device_t dev, u8 addr, u16 value); + int (*process_call)(device_t dev, u8 cmd, u16 data); + int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); }; static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus) { - const struct smbus_bus_operations *bops; - bops = 0; - if (bus && bus->dev && bus->dev->ops) { - bops = bus->dev->ops->ops_smbus_bus; - } - return bops; + const struct smbus_bus_operations *bops; + + bops = 0; + if (bus && bus->dev && bus->dev->ops) + bops = bus->dev->ops->ops_smbus_bus; + + return bops; } + struct bus *get_pbus_smbus(device_t dev); int smbus_set_link(device_t dev); int smbus_quick_read(device_t dev); int smbus_quick_write(device_t dev); int smbus_recv_byte(device_t dev); -int smbus_send_byte(device_t dev, uint8_t byte); -int smbus_read_byte(device_t dev, uint8_t addr); -int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val); -int smbus_read_word(device_t dev, uint8_t addr); -int smbus_write_word(device_t dev, uint8_t addr, uint16_t val); -int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data); -int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer); -int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer); - +int smbus_send_byte(device_t dev, u8 byte); +int smbus_read_byte(device_t dev, u8 addr); +int smbus_write_byte(device_t dev, u8 addr, u8 val); +int smbus_read_word(device_t dev, u8 addr); +int smbus_write_word(device_t dev, u8 addr, u16 val); +int smbus_process_call(device_t dev, u8 cmd, u16 data); +int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); #endif /* DEVICE_SMBUS_H */

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[commit] r5961 - trunk/src/cpu/intel/microcode
by repository service 18 Oct '10

18 Oct '10

Author: stepan Date: Mon Oct 18 01:55:17 2010 New Revision: 5961 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5961 Log: update intel microcode update script Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/cpu/intel/microcode/update-microcodes.sh Modified: trunk/src/cpu/intel/microcode/update-microcodes.sh ============================================================================== --- trunk/src/cpu/intel/microcode/update-microcodes.sh Mon Oct 18 00:07:08 2010 (r5960) +++ trunk/src/cpu/intel/microcode/update-microcodes.sh Mon Oct 18 01:55:17 2010 (r5961) @@ -18,10 +18,10 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -MICROCODE_VERSION=20100209 +MICROCODE_VERSION=20100914 MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz MICROCODE_FILE=microcode-$MICROCODE_VERSION.dat -INTEL_MICROCODE=http://downloadmirror.intel.com/18683/eng/$MICROCODE_ARCHIVE +INTEL_MICROCODE=http://downloadmirror.intel.com/19342/eng/$MICROCODE_ARCHIVE # # Getting Intel(R) Microcode @@ -39,7 +39,7 @@ separate_microcode() { printf "Separating microcode...\n" - csplit -s -n4 -k microcode-20100209.dat '/^\/\*.*\.inc.*\*\//' '{500}' 2> /dev/null + csplit -s -n4 -k $MICROCODE_FILE '/^\/\*.*\.inc.*\*\//' '{500}' 2> /dev/null mv xx0000 header.inc perl -pi -e 's,\ \ \ \ \ \ \ ,\ ,' header.inc perl -pi -e 's,^,/,g' header.inc

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Re: [coreboot] [PATCH] model_65x CPU support
by Keith Hui 18 Oct '10

18 Oct '10

>Keith Hui wrote: >> Attached patch moves support for Deschutes Slot 1 CPUs (model_65x) >> into its own home. >Then I guess the patch should also delete some lines in existing files? Yes. I knew I must be missing something. (Oops) See attached patch. Signed-off-by: Keith Hui <buurin(a)gmail.com> >> This is similar to the Katmai patch I submitted before, but without >> microcode this time. With 17 of them they will make the patch too >> large. I think I'll defer them for later or someone else*, hehe. :D >> >> abuild-tested. > >It doesn't look like the new code is used anywhere? Should it be? It should be used from cpu/intel/slot_1. >> * also because I like to keep all microcodes for the same family >> within one file instead of one microcode per file. >We want microcode updates to be as close as possible to upstream How upstream are we talking about? :P These updates come from Intel as one big .h file. ;-) >format. Eventually I think we want to put them verbatim into cbfs. This I agree wholeheartedly. Did I ever mention that Award also stuff their microcode updates this way into the firmware image? And hey, I might as well take a crack at this! But a bit of scheduling headache then awaits. How much CPU init do we need to do before we start drawing things in from the cbfs? Is there anything that cannot be done until microcode updates are loaded? Is cpu_dev_ops.init() an appropriate place to access cbfs? If not, from where? Cheers Keith

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[commit] r5959 - in trunk/src/southbridge/amd: rs690 rs780
by repository service 17 Oct '10

17 Oct '10

Author: uwe Date: Sun Oct 17 23:59:43 2010 New Revision: 5959 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5959 Log: In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set to zero, so for boards with RS780 not on CPU's HT chain 0, the function will mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3() function will hang when it visits the MMIO. The following patch fixes the problem, and is tested on a K8 board with RS780 on HT chain 1. Signed-off-by: Liu Tao <liutao1980(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c trunk/src/southbridge/amd/rs780/rs780_cmn.c Modified: trunk/src/southbridge/amd/rs690/rs690_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs690/rs690_cmn.c Sun Oct 17 23:34:45 2010 (r5958) +++ trunk/src/southbridge/amd/rs690/rs690_cmn.c Sun Oct 17 23:59:43 2010 (r5959) @@ -202,15 +202,23 @@ { /* K8 Function1 is address map */ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); if (in_out) { + u32 dword, sblk; + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + dword = pci_read_config32(k8_f0, 0x64); + sblk = (dword >> 8) & 0x3; + + /* Fill MMIO limit/base pair. */ pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80); + 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, - ((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00); + (((mmio_base_add + 0x10000000 - + 1) >> 8) & 0xffffff00) | (sblk << 4)); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); } else { pci_write_config32(k8_f1, 0xb8, 0); Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_cmn.c Sun Oct 17 23:34:45 2010 (r5958) +++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Sun Oct 17 23:59:43 2010 (r5959) @@ -200,15 +200,23 @@ { /* K8 Function1 is address map */ device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); if (in_out) { + u32 dword, sblk; + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + dword = pci_read_config32(k8_f0, 0x64); + sblk = (dword >> 8) & 0x3; + + /* Fill MMIO limit/base pair. */ pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80); + 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, - ((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00); + (((mmio_base_add + 0x10000000 - + 1) >> 8) & 0xffffff00) | (sblk << 4)); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); } else { pci_write_config32(k8_f1, 0xb8, 0);

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[PATCH] fix dst-link field in RS780/RS690 function ProgK8TempMmioBase
by Liu Tao 17 Oct '10

17 Oct '10

Hello, in RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set to zero, so for boards with RS780 not on CPU's HT chain 0, the function will mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3() function will hang when it visits the MMIO. the following patch fixes the problem, and tested on a K8 board with RS780 on HT chain 1. Signed-off-by: Liu Tao <liutao1980(a)gmail.com> -- Regards, Liu Tao

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[commit] r5958 - trunk/src/southbridge/amd/rs780
by repository service 17 Oct '10

17 Oct '10

Author: uwe Date: Sun Oct 17 23:34:45 2010 New Revision: 5958 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5958 Log: We currently read the CPU HT speed from HT chain 0's register. Fix that to read the register from the chain where the SB chip is on. Signed-off-by: Liu Tao <liutao1980(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Sun Oct 17 21:30:58 2010 (r5957) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Sun Oct 17 23:34:45 2010 (r5958) @@ -304,7 +304,7 @@ volatile u32 * pointer; int i; u16 command; - u32 value; + u32 value, sblink; u16 deviceid, vendorid; device_t nb_dev = dev_find_slot(0, 0); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); @@ -453,9 +453,15 @@ vgainfo.usMinNBVoltage = 0; vgainfo.usBootUpNBVoltage = 0x1a; + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + value = pci_read_config32(k8_f0, 0x64); + sblink = (value >> 8) & 0x3; + printk(BIOS_DEBUG, "SBLINK = %d.\n", sblink); + + /* HT speed */ value = pci_read_config32(nb_dev, 0xd0); printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); - value = pci_read_config32(k8_f0, 0x88); + value = pci_read_config32(k8_f0, 0x88 + (sblink * 0x20)); printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */

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non-posted/posted MMIO on MMCONFIG
by Rudolf Marek 17 Oct '10

17 Oct '10

Hi, I check AMD BKDG and MMCONFIG region should be marked non-posted (CPU waits for transaction to complete). Also this suggest the PCI ENC. I think the early bar3 code sets non-posted in sb700/rs780 but in general we dont have any generic support. http://www.pcisig.com/specifications/pciexpress/PciEx_ECN_MMCONFIG_040217.p… It looks we have no support for posted/non-posted MMIO resource type right? As the side note, the fam10h has MMIO MMCONFIG region too. Most likely we should for AMDadd the NON_POSTED resource and set the bit in resourcemap (the MMIO routing registers) Thanks, Rudolf

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[commit] r5957 - in trunk/src/southbridge: amd/amd8132 amd/amd8151 amd/cs5530 broadcom/bcm21000 broadcom/bcm5780 broadcom/bcm5785 sis/sis966 ti/pci1x2x ti/pcixx12
by repository service 17 Oct '10

17 Oct '10

Author: uwe Date: Sun Oct 17 21:30:58 2010 New Revision: 5957 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5957 Log: Add more missing GPL-headers, fix inconsistencies in others. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/amd/amd8132/amd8132_bridge.c trunk/src/southbridge/amd/amd8151/amd8151_agp3.c trunk/src/southbridge/amd/cs5530/cs5530_vga.c trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c trunk/src/southbridge/broadcom/bcm5785/bcm5785.c trunk/src/southbridge/broadcom/bcm5785/bcm5785.h trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c trunk/src/southbridge/broadcom/bcm5785/bootblock.c trunk/src/southbridge/broadcom/bcm5785/chip.h trunk/src/southbridge/sis/sis966/sis761.c trunk/src/southbridge/ti/pci1x2x/pci1x2x.c trunk/src/southbridge/ti/pcixx12/chip.h trunk/src/southbridge/ti/pcixx12/pcixx12.c Modified: trunk/src/southbridge/amd/amd8132/amd8132_bridge.c ============================================================================== --- trunk/src/southbridge/amd/amd8132/amd8132_bridge.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/amd/amd8132/amd8132_bridge.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2005 Advanced Micro Devices, Inc. - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2005,2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,10 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Description: Amd 8132 support by yhlu - */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> Modified: trunk/src/southbridge/amd/amd8151/amd8151_agp3.c ============================================================================== --- trunk/src/southbridge/amd/amd8151/amd8151_agp3.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/amd/amd8151/amd8151_agp3.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,8 +1,23 @@ /* - * Copyright 2003 Tyan + * This file is part of the coreboot project. * - * Author: Yinghai Lu + * Copyright (C) 2003 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> Modified: trunk/src/southbridge/amd/cs5530/cs5530_vga.c ============================================================================== --- trunk/src/southbridge/amd/cs5530/cs5530_vga.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/amd/cs5530/cs5530_vga.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,4 +1,6 @@ /* + * This file is part of the coreboot project. + * * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> * * This program is free software; you can redistribute it and/or modify Modified: trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,8 +1,9 @@ /* * This file is part of the coreboot project. * -* Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for University of Heidelberg + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle <nuessle(a)uni-heidelberg.de> for + * University of Heidelberg. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -28,7 +28,6 @@ static void pcie_init(struct device *dev) { - /* Enable pci error detecting */ uint32_t dword; uint32_t msicap; @@ -61,7 +60,6 @@ .ops_pci = &lops_pci, }; - static const struct pci_driver pcie_driver1 __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, @@ -79,4 +77,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2, }; - Modified: trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5780/bcm5780_nic.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -9,10 +24,8 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> - static void nic_init(struct device *dev) { - #if CONFIG_PCI_ROM_RUN == 1 pci_dev_init(dev);// it will init option rom #endif @@ -37,11 +50,13 @@ .scan_bus = 0, .ops_pci = &lops_pci, }; + static const struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_BROADCOM, .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC, }; + static const struct pci_driver nic1_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_BROADCOM, Modified: trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcie.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -43,4 +58,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE, }; - Modified: trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5780/bcm5780_pcix.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -14,6 +29,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; @@ -34,4 +50,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,7 +1,23 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785.h ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785.h Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785.h Sun Oct 17 21:30:58 2010 (r5957) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef BCM5785_H #define BCM5785_H Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <reset.h> @@ -9,7 +24,6 @@ static void bcm5785_enable_lpc(void) { - uint8_t byte; device_t dev; @@ -119,8 +133,6 @@ #endif } - - static void bcm5785_enable_msg(void) { device_t dev; @@ -145,7 +157,6 @@ if(dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } - } static void bcm5785_early_setup(void) Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "bcm5785_smbus.h" Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + static void bcm5785_enable_rom(void) { unsigned char byte; Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -50,4 +65,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -18,13 +33,11 @@ static void lpc_init(device_t dev) { - /* Initialize the real time clock */ rtc_init(0); /* Initialize isa dma */ isa_dma_init(); - } static void bcm5785_lpc_read_resources(device_t dev) @@ -54,10 +67,9 @@ } /** - * @brief Enable resources for children devices - * - * @param dev the device whos children's resources are to be enabled + * Enable resources for children devices. * + * @param dev The device whos children's resources are to be enabled. */ static void bcm5785_lpc_enable_childrens_resources(device_t dev) { @@ -128,9 +140,9 @@ // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; + static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> @@ -39,4 +54,3 @@ outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -63,6 +78,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; @@ -82,4 +98,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -89,6 +104,7 @@ return do_smbus_send_byte(res->base, device, val); } + static int lsmbus_read_byte(device_t dev, uint8_t address) { unsigned device; @@ -102,6 +118,7 @@ return do_smbus_read_byte(res->base, device, address); } + static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) { unsigned device; @@ -115,6 +132,7 @@ return do_smbus_write_byte(res->base, device, address, val); } + static struct smbus_bus_operations lops_smbus_bus = { .recv_byte = lsmbus_recv_byte, .send_byte = lsmbus_send_byte, @@ -142,9 +160,9 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; + static const struct pci_driver sb_driver __pci_driver = { .ops = &sb_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_smbus.h Sun Oct 17 21:30:58 2010 (r5957) @@ -1,7 +1,23 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <device/smbus_def.h> #define SMBHSTSTAT 0x0 @@ -90,8 +106,8 @@ byte = inb(smbus_io_base + SMBHSTCMD); return byte; - } + static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) { uint8_t byte; @@ -117,10 +133,8 @@ } return 0; - } - static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { uint8_t byte; @@ -150,6 +164,7 @@ return byte; } + static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) { uint8_t byte; @@ -178,7 +193,4 @@ } return 0; - } - - Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_usb.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,21 @@ /* - * Copyright 2005 AMD - * by yinghai.lu(a)amd.com + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> @@ -27,6 +42,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; @@ -46,4 +62,3 @@ .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB, }; - Modified: trunk/src/southbridge/broadcom/bcm5785/bootblock.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bootblock.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/bootblock.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include "bcm5785_enable_rom.c" static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/broadcom/bcm5785/chip.h ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/chip.h Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/broadcom/bcm5785/chip.h Sun Oct 17 21:30:58 2010 (r5957) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef BCM5785_CHIP_H #define BCM5785_CHIP_H Modified: trunk/src/southbridge/sis/sis966/sis761.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis761.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/sis/sis966/sis761.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,6 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) + * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -14,7 +17,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * + */ + +/* * Turn off machine check triggers when reading * pci space where there are no devices. * This is necessary when scaning the bus for @@ -24,9 +29,6 @@ * * - Athlon64 workarounds by Stefan Reinauer * - "reset once" logic by Yinghai Lu - * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) - * Written by Morgan Tsai <my_tsai(a)sis.com> for SiS. - * */ #include <console/console.h> Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Sun Oct 17 21:30:58 2010 (r5957) @@ -17,6 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> Modified: trunk/src/southbridge/ti/pcixx12/chip.h ============================================================================== --- trunk/src/southbridge/ti/pcixx12/chip.h Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/ti/pcixx12/chip.h Sun Oct 17 21:30:58 2010 (r5957) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2008 coresystems GmbH + * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,8 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef _SOUTHBRIDGE_TI_PCIXX12 Modified: trunk/src/southbridge/ti/pcixx12/pcixx12.c ============================================================================== --- trunk/src/southbridge/ti/pcixx12/pcixx12.c Sun Oct 17 21:13:18 2010 (r5956) +++ trunk/src/southbridge/ti/pcixx12/pcixx12.c Sun Oct 17 21:30:58 2010 (r5957) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * (C) Copyright 2008 coresystems GmbH + * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,8 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h>

1 0

[commit] r5956 - trunk/src/southbridge/nvidia/ck804
by repository service 17 Oct '10

17 Oct '10

Author: uwe Date: Sun Oct 17 21:13:18 2010 New Revision: 5956 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5956 Log: Use common GPL-header format in CK804 files, add missing ones (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/nvidia/ck804/chip.h trunk/src/southbridge/nvidia/ck804/ck804.c trunk/src/southbridge/nvidia/ck804/ck804.h trunk/src/southbridge/nvidia/ck804/ck804_ac97.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c trunk/src/southbridge/nvidia/ck804/ck804_ht.c trunk/src/southbridge/nvidia/ck804/ck804_ide.c trunk/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/src/southbridge/nvidia/ck804/ck804_nic.c trunk/src/southbridge/nvidia/ck804/ck804_pci.c trunk/src/southbridge/nvidia/ck804/ck804_pcie.c trunk/src/southbridge/nvidia/ck804/ck804_reset.c trunk/src/southbridge/nvidia/ck804/ck804_sata.c trunk/src/southbridge/nvidia/ck804/ck804_smbus.c trunk/src/southbridge/nvidia/ck804/ck804_smbus.h trunk/src/southbridge/nvidia/ck804/ck804_usb.c trunk/src/southbridge/nvidia/ck804/ck804_usb2.c trunk/src/southbridge/nvidia/ck804/romstrap.inc trunk/src/southbridge/nvidia/ck804/romstrap.lds Modified: trunk/src/southbridge/nvidia/ck804/chip.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/chip.h Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/chip.h Sun Oct 17 21:13:18 2010 (r5956) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef CK804_CHIP_H #define CK804_CHIP_H Modified: trunk/src/southbridge/nvidia/ck804/ck804.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.h Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804.h Sun Oct 17 21:13:18 2010 (r5956) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef CK804_H #define CK804_H Modified: trunk/src/southbridge/nvidia/ck804/ck804_ac97.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_ac97.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_ac97.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <reset.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,7 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com - * 2005.12 yhlu make it for car so it could support more ck804s + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ static int set_ht_link_ck804(uint8_t ht_c_num) Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ static const unsigned int pcie_ss_tbl[] = { Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include "ck804_smbus.h" Modified: trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_enable_rom.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE Modified: trunk/src/southbridge/nvidia/ck804/ck804_ht.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_ht.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_ht.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_ide.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_ide.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_ide.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_lpc.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_lpc.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,8 +1,23 @@ /* - * (C) 2003 Linux Networx, SuSE Linux AG - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com - * 2006.1 yhlu add dest apicid for IRQ0 + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2003 SuSE Linux AG + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_nic.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_nic.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_nic.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_pci.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_pci.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_pci.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_pcie.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_pcie.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_pcie.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_reset.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_reset.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_reset.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <arch/io.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_sata.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_sata.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_sata.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_smbus.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_smbus.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_smbus.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_smbus.h Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_smbus.h Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <device/smbus_def.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_usb.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_usb.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_usb.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/ck804_usb2.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_usb2.c Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/ck804_usb2.c Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> Modified: trunk/src/southbridge/nvidia/ck804/romstrap.inc ============================================================================== --- trunk/src/southbridge/nvidia/ck804/romstrap.inc Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/romstrap.inc Sun Oct 17 21:13:18 2010 (r5956) @@ -1,6 +1,21 @@ /* - * Copyright 2004 Tyan Computer - * by yhlu(a)tyan.com + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ .section ".romstrap", "a", @progbits Modified: trunk/src/southbridge/nvidia/ck804/romstrap.lds ============================================================================== --- trunk/src/southbridge/nvidia/ck804/romstrap.lds Sun Oct 17 21:01:48 2010 (r5955) +++ trunk/src/southbridge/nvidia/ck804/romstrap.lds Sun Oct 17 21:13:18 2010 (r5956) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + SECTIONS { . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): {

1 0

[commit] r5955 - trunk/src/devices
by repository service 17 Oct '10

17 Oct '10

Author: uwe Date: Sun Oct 17 21:01:48 2010 New Revision: 5955 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5955 Log: Various Doxygen comment fixes, typo fixes, etc. - Fix incorrect argument names for @param entries. - Add missing @param and @return entries, partly as TODOs. - s/@returns/@return/, that's a typo. - Small whitespace fixes while I'm at it. - Drop useless @brief commands, they just clutter the comments and make them harder to read. Doxygen has an option to always use the first sentence of a Doxygen-comment as @brief automatically (should be on per default). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/devices/device.c trunk/src/devices/device_util.c trunk/src/devices/hypertransport.c trunk/src/devices/pci_device.c trunk/src/devices/pci_ops.c trunk/src/devices/pci_rom.c trunk/src/devices/pciexp_device.c trunk/src/devices/pcix_device.c trunk/src/devices/root_device.c trunk/src/devices/smbus_ops.c Modified: trunk/src/devices/device.c ============================================================================== --- trunk/src/devices/device.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/device.c Sun Oct 17 21:01:48 2010 (r5955) @@ -46,23 +46,20 @@ /** Linked list of free resources */ struct resource *free_resources = NULL; +DECLARE_SPIN_LOCK(dev_lock) /** - * @brief Allocate a new device structure. + * Allocate a new device structure. * - * Allocte a new device structure and attached it to the device tree as a + * Allocte a new device structure and attach it to the device tree as a * child of the parent bus. * - * @param parent parent bus the newly created device attached to. - * @param path path to the device to be created. - * - * @return pointer to the newly created device structure. + * @param parent Parent bus the newly created device should be attached to. + * @param path Path to the device to be created. + * @return Pointer to the newly created device structure. * * @see device_path */ - -DECLARE_SPIN_LOCK(dev_lock) - device_t alloc_dev(struct bus *parent, struct device_path *path) { device_t dev, child; @@ -103,10 +100,11 @@ } /** - * @brief round a number up to an alignment. - * @param val the starting value - * @param roundup Alignment as a power of two - * @returns rounded up number + * Round a number up to an alignment. + * + * @param val The starting value. + * @param roundup Alignment as a power of two. + * @return Rounded up number. */ static resource_t round(resource_t val, unsigned long pow) { @@ -117,15 +115,17 @@ return val; } -/** Read the resources on all devices of a given bus. - * @param bus bus to read the resources on. +/** + * Read the resources on all devices of a given bus. + * + * @param bus Bus to read the resources on. */ static void read_resources(struct bus *bus) { struct device *curdev; - printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), __func__, - bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), + __func__, bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -205,7 +205,8 @@ return state.result_dev; } -/* Compute allocate resources is the guts of the resource allocator. +/** + * Compute allocate resources is the guts of the resource allocator. * * The problem. * - Allocate resource locations for every device. @@ -231,6 +232,11 @@ * a device with a couple of resources, and not need to special case it in * the allocator. Also this allows handling of other types of bridges. * + * @param bus The bus we are traversing. + * @param bridge The bridge resource which must contain the bus' resources. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. + * @return TODO */ static void compute_resources(struct bus *bus, struct resource *bridge, unsigned long type_mask, unsigned long type) @@ -392,8 +398,8 @@ * * @param bus The bus we are traversing. * @param bridge The bridge resource which must contain the bus' resources. - * @param type_mask This value gets anded with the resource type. - * @param type This value must match the result of the and. + * @param type_mask This value gets ANDed with the resource type. + * @param type This value must match the result of the AND. */ static void allocate_resources(struct bus *bus, struct resource *bridge, unsigned long type_mask, unsigned long type) @@ -540,10 +546,11 @@ } #if CONFIG_PCI_64BIT_PREF_MEM == 1 - #define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) +#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM) #else - #define MEM_MASK (IORESOURCE_MEM) +#define MEM_MASK (IORESOURCE_MEM) #endif + #define IO_MASK (IORESOURCE_IO) #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) #define MEM_TYPE (IORESOURCE_MEM) @@ -749,9 +756,7 @@ #endif /** - * @brief Assign the computed resources to the devices on the bus. - * - * @param bus Pointer to the structure for this bus + * Assign the computed resources to the devices on the bus. * * Use the device specific set_resources method to store the computed * resources to hardware. For bridge devices, the set_resources() method @@ -760,6 +765,8 @@ * Mutual recursion: * assign_resources() -> device_operation::set_resources() * device_operation::set_resources() -> assign_resources() + * + * @param bus Pointer to the structure for this bus. */ void assign_resources(struct bus *bus) { @@ -784,9 +791,7 @@ } /** - * @brief Enable the resources for devices on a link - * - * @param link the link whose devices' resources are to be enabled + * Enable the resources for devices on a link. * * Enable resources of the device by calling the device specific * enable_resources() method. @@ -795,6 +800,7 @@ * order problem. This is done by calling the parent's enable_resources() * method before its childrens' enable_resources() methods. * + * @param link The link whose devices' resources are to be enabled. */ static void enable_resources(struct bus *link) { @@ -815,14 +821,10 @@ } /** - * @brief Reset all of the devices a bus - * * Reset all of the devices on a bus and clear the bus's reset_needed flag. * - * @param bus pointer to the bus structure - * + * @param bus Pointer to the bus structure. * @return 1 if the bus was successfully reset, 0 otherwise. - * */ int reset_bus(struct bus *bus) { @@ -835,7 +837,7 @@ } /** - * @brief Scan for devices on a bus. + * Scan for devices on a bus. * * If there are bridges on the bus, recursively scan the buses behind the * bridges. If the setting up and tuning of the bus causes a reset to be @@ -873,7 +875,7 @@ } /** - * @brief Determine the existence of devices and extend the device tree. + * Determine the existence of devices and extend the device tree. * * Most of the devices in the system are listed in the mainboard Config.lb * file. The device structures for these devices are generated at compile @@ -916,7 +918,7 @@ } /** - * @brief Configure devices on the devices tree. + * Configure devices on the devices tree. * * Starting at the root of the device tree, travel it recursively in two * passes. In the first pass, we compute and allocate resources (ranges) @@ -1032,7 +1034,7 @@ } /** - * @brief Enable devices on the device tree. + * Enable devices on the device tree. * * Starting at the root, walk the tree and enable all devices/bridges by * calling the device's enable_resources() method. @@ -1051,14 +1053,13 @@ } /** - * @brief Initialize a specific device - * - * @param dev the device to be initialized + * Initialize a specific device. * * The parent should be initialized first to avoid having an ordering * problem. This is done by calling the parent's init() * method before its childrens' init() methods. * + * @param dev The device to be initialized. */ static void init_dev(struct device *dev) { @@ -1095,10 +1096,10 @@ } /** - * @brief Initialize all devices in the global device tree. + * Initialize all devices in the global device tree. * - * Starting at the root device, call the device's init() method to do device- - * specific setup, then call each child's init() method. + * Starting at the root device, call the device's init() method to do + * device-specific setup, then call each child's init() method. */ void dev_initialize(void) { Modified: trunk/src/devices/device_util.c ============================================================================== --- trunk/src/devices/device_util.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/device_util.c Sun Oct 17 21:01:48 2010 (r5955) @@ -30,12 +30,12 @@ #include <string.h> /** - * @brief See if a device structure exists for path + * See if a device structure exists for path. * - * @param bus The bus to find the device on - * @param path The relative path from the bus to the appropriate device - * @return pointer to a device structure for the device on bus at path - * or 0/NULL if no device is found + * @param parent The bus to find the device on. + * @param path The relative path from the bus to the appropriate device. + * @return Pointer to a device structure for the device on bus at path + * or 0/NULL if no device is found. */ device_t find_dev_path(struct bus *parent, struct device_path *path) { @@ -49,11 +49,11 @@ } /** - * @brief See if a device structure already exists and if not allocate it + * See if a device structure already exists and if not allocate it. * - * @param bus The bus to find the device on - * @param path The relative path from the bus to the appropriate device - * @return pointer to a device structure for the device on bus at path + * @param parent The bus to find the device on. + * @param path The relative path from the bus to the appropriate device. + * @return Pointer to a device structure for the device on bus at path. */ device_t alloc_find_dev(struct bus *parent, struct device_path *path) { @@ -66,11 +66,11 @@ } /** - * @brief Given a PCI bus and a devfn number, find the device structure + * Given a PCI bus and a devfn number, find the device structure. * - * @param bus The bus number - * @param devfn a device/function number - * @return pointer to the device structure + * @param bus The bus number. + * @param devfn A device/function number. + * @return Pointer to the device structure (if found), 0 otherwise. */ struct device *dev_find_slot(unsigned int bus, unsigned int devfn) { @@ -89,11 +89,11 @@ } /** - * @brief Given a smbus bus and a device number, find the device structure + * Given an SMBus bus and a device number, find the device structure. * - * @param bus The bus number - * @param addr a device number - * @return pointer to the device structure + * @param bus The bus number. + * @param addr A device number. + * @return Pointer to the device structure (if found), 0 otherwise. */ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) { @@ -111,15 +111,18 @@ return result; } -/** Find a device of a given vendor and type - * @param vendor Vendor ID (e.g. 0x8086 for Intel) - * @param device Device ID +/** + * Find a device of a given vendor and type. + * + * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). + * @param device A PCI device ID. * @param from Pointer to the device structure, used as a starting point * in the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * head of the list (i.e. all_devices). + * @return Pointer to the device struct. */ -struct device *dev_find_device(unsigned int vendor, unsigned int device, struct device *from) +struct device *dev_find_device(unsigned int vendor, unsigned int device, + struct device *from) { if (!from) from = all_devices; @@ -131,12 +134,14 @@ return from; } -/** Find a device of a given class - * @param class Class of the device +/** + * Find a device of a given class. + * + * @param class Class of the device. * @param from Pointer to the device structure, used as a starting point * in the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices) - * @return Pointer to the device struct + * head of the list (i.e. all_devices). + * @return Pointer to the device struct. */ struct device *dev_find_class(unsigned int class, struct device *from) { @@ -149,12 +154,14 @@ return from; } -/* Warning: This function uses a static buffer. Don't call it more than once - * from the same print statement! */ - +/* + * Warning: This function uses a static buffer. Don't call it more than once + * from the same print statement! + */ const char *dev_path(device_t dev) { static char buffer[DEVICE_PATH_MAX]; + buffer[0] = '\0'; if (!dev) { memcpy(buffer, "<null>", 7); @@ -262,6 +269,8 @@ /** * Allocate 64 more resources to the free list. + * + * @return TODO. */ static int allocate_more_resources(void) { @@ -283,8 +292,14 @@ /** * Remove resource res from the device's list and add it to the free list. + * + * @param dev TODO + * @param res TODO + * @param prev TODO + * @return TODO. */ -static void free_resource(device_t dev, struct resource *res, struct resource *prev) +static void free_resource(device_t dev, struct resource *res, + struct resource *prev) { if (prev) prev->next = res->next; @@ -297,7 +312,8 @@ /** * See if we have unused but allocated resource structures. * If so remove the allocation. - * @param dev The device to find the resource on + * + * @param dev The device to find the resource on. */ void compact_resources(device_t dev) { @@ -312,16 +328,17 @@ } } - /** - * See if a resource structure already exists for a given index - * @param dev The device to find the resource on - * @param index The index of the resource on the device. - * @return the resource if it already exists + * See if a resource structure already exists for a given index. + * + * @param dev The device to find the resource on. + * @param index The index of the resource on the device. + * @return The resource, if it already exists. */ struct resource *probe_resource(device_t dev, unsigned index) { struct resource *res; + /* See if there is a resource with the appropriate index */ for (res = dev->resource_list; res; res = res->next) { if (res->index == index) @@ -331,11 +348,14 @@ } /** - * See if a resource structure already exists for a given index and if - * not allocate one. Then initialize the initialize the resource - * to default values. - * @param dev The device to find the resource on - * @param index The index of the resource on the device. + * See if a resource structure already exists for a given index and if not + * allocate one. + * + * Then initialize the initialize the resource to default values. + * + * @param dev The device to find the resource on. + * @param index The index of the resource on the device. + * @return TODO. */ struct resource *new_resource(device_t dev, unsigned index) { @@ -378,8 +398,10 @@ /** * Return an existing resource structure for a given index. - * @param dev The device to find the resource on - * @param index The index of the resource on the device. + * + * @param dev The device to find the resource on. + * @param index The index of the resource on the device. + * return TODO. */ struct resource *find_resource(device_t dev, unsigned index) { @@ -397,10 +419,11 @@ /** - * @brief round a number up to the next multiple of gran - * @param val the starting value - * @param gran granularity we are aligning the number to. - * @returns aligned value + * Round a number up to the next multiple of gran. + * + * @param val The starting value. + * @param gran Granularity we are aligning the number to. + * @return The aligned value. */ static resource_t align_up(resource_t val, unsigned long gran) { @@ -412,10 +435,11 @@ } /** - * @brief round a number up to the previous multiple of gran - * @param val the starting value - * @param gran granularity we are aligning the number to. - * @returns aligned value + * Round a number up to the previous multiple of gran. + * + * @param val The starting value. + * @param gran Granularity we are aligning the number to. + * @return The aligned value. */ static resource_t align_down(resource_t val, unsigned long gran) { @@ -426,9 +450,10 @@ } /** - * @brief Compute the maximum address that is part of a resource - * @param resource the resource whose limit is desired - * @returns the end + * Compute the maximum address that is part of a resource. + * + * @param resource The resource whose limit is desired. + * @return The end. */ resource_t resource_end(struct resource *resource) { @@ -449,9 +474,10 @@ } /** - * @brief Compute the maximum legal value for resource->base - * @param resource the resource whose maximum is desired - * @returns the maximum + * Compute the maximum legal value for resource->base. + * + * @param resource The resource whose maximum is desired. + * @return The maximum. */ resource_t resource_max(struct resource *resource) { @@ -463,8 +489,10 @@ } /** - * @brief return the resource type of a resource - * @param resource the resource type to decode. + * Return the resource type of a resource. + * + * @param resource The resource type to decode. + * @return TODO. */ const char *resource_type(struct resource *resource) { @@ -482,11 +510,14 @@ } /** - * @brief print the resource that was just stored. - * @param dev the device the stored resorce lives on - * @param resource the resource that was just stored. + * Print the resource that was just stored. + * + * @param dev The device the stored resorce lives on. + * @param resource The resource that was just stored. + * @param comment TODO */ -void report_resource_stored(device_t dev, struct resource *resource, const char *comment) +void report_resource_stored(device_t dev, struct resource *resource, + const char *comment) { if (resource->flags & IORESOURCE_STORED) { char buf[10]; Modified: trunk/src/devices/hypertransport.c ============================================================================== --- trunk/src/devices/hypertransport.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/hypertransport.c Sun Oct 17 21:01:48 2010 (r5955) @@ -23,10 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - 2005.11 yhlu add let the real sb to use small uintid -*/ - #include <bitops.h> #include <console/console.h> #include <device/device.h> @@ -35,8 +31,9 @@ #include <device/pci_ids.h> #include <device/hypertransport.h> -/* The hypertransport link is already optimized in pre-ram code - * so don't do it again +/* + * The hypertransport link is already optimized in pre-RAM code so don't do + * it again. */ #define OPT_HT_LINK 0 @@ -261,7 +258,6 @@ } return reset_needed; - } static unsigned ht_lookup_slave_capability(struct device *dev) @@ -598,17 +594,18 @@ } /** - * @brief Scan a PCI bridge and the buses behind the bridge. + * Scan a PCI bridge and the buses behind the bridge. * * Determine the existence of buses behind the bridge. Set up the bridge * according to the result of the scan. * * This function is the default scan_bus() method for PCI bridge devices. * - * @param dev pointer to the bridge device - * @param max the highest bus number assgined up to now - * - * @return The maximum bus number found, after scanning all subordinate busses + * @param bus TODO + * @param min_devfn TODO + * @param max_devfn TODO + * @param max The highest bus number assgined up to now. + * @return The maximum bus number found, after scanning all subordinate busses. */ static unsigned int hypertransport_scan_chain_x(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max) @@ -623,7 +620,6 @@ return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); } - /** Default device operations for hypertransport bridges */ static struct pci_operations ht_bus_ops_pci = { .set_subsystem = 0, Modified: trunk/src/devices/pci_device.c ============================================================================== --- trunk/src/devices/pci_device.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/pci_device.c Sun Oct 17 21:01:48 2010 (r5955) @@ -106,8 +106,9 @@ * matching capability. Always start at the head of the list. * * @param dev Pointer to the device structure. - * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. * @param last Location of the PCI capability register to start from. + * @return The next matching capability. */ unsigned pci_find_next_capability(struct device *dev, unsigned cap, unsigned last) @@ -157,7 +158,8 @@ * capability. Always start at the head of the list. * * @param dev Pointer to the device structure. - * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. + * @return The next matching capability. */ unsigned pci_find_capability(device_t dev, unsigned cap) { @@ -169,6 +171,7 @@ * * @param dev Pointer to the device structure. * @param index Address of the PCI configuration register. + * @return TODO */ struct resource *pci_get_resource(struct device *dev, unsigned long index) { @@ -373,11 +376,11 @@ /* See if the bridge I/O resources are implemented. */ moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8; moving_base |= - ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; + ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; moving_limit |= - ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; + ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; moving = moving_base & moving_limit; @@ -386,17 +389,14 @@ /* See if the bridge prefmem resources are implemented. */ moving_base = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; + ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; moving_base |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << - 32; + ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; moving_limit = - ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << - 16; + ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; moving_limit |= - ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << - 32; + ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; moving = moving_base & moving_limit; /* Initialize the prefetchable memory constraints on the current bus. */ @@ -704,7 +704,7 @@ }; /** - * @brief Detect the type of downstream bridge + * Detect the type of downstream bridge. * * This function is a heuristic to detect which type of bus is downstream * of a PCI-to-PCI bridge. This functions by looking for various capability @@ -768,8 +768,10 @@ } /** - * Set up PCI device operation. Check if it already has a driver. If not, use - * find_device_operations, or set to a default based on type. + * Set up PCI device operation. + * + * Check if it already has a driver. If not, use find_device_operations(), + * or set to a default based on type. * * @param dev Pointer to the device whose pci_ops you want to set. * @see pci_drivers @@ -827,7 +829,7 @@ } /** - * @brief See if we have already allocated a device structure for a given devfn. + * See if we have already allocated a device structure for a given devfn. * * Given a linked list of PCI device structures and a devfn number, find the * device structure correspond to the devfn, if present. This function also @@ -835,7 +837,6 @@ * * @param list The device structure list. * @param devfn A device/function number. - * * @return Pointer to the device structure found or NULL if we have not * allocated a device for this devfn yet. */ @@ -881,18 +882,17 @@ } /** - * @brief Scan a PCI bus. + * Scan a PCI bus. * * Determine the existence of a given PCI device. Allocate a new struct device * if dev==NULL was passed in and the device exists in hardware. * - * @param bus pointer to the bus structure - * @param devfn to look at - * - * @return The device structure for hte device (if found) - * or the NULL if no device is found. + * @param dev Pointer to the dev structure. + * @param bus Pointer to the bus structure. + * @param devfn A device/function number to look at. + * @return The device structure for the device (if found), NULL otherwise. */ -device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn) +device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) { u32 id, class; u8 hdr_type; @@ -989,7 +989,7 @@ } /** - * @brief Scan a PCI bus. + * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are * bridges on the bus, recursively scan the buses behind the bridges. @@ -997,12 +997,11 @@ * This function is the default scan_bus() method for the root device * 'dev_root'. * - * @param bus pointer to the bus structure - * @param min_devfn minimum devfn to look at in the scan usually 0x00 - * @param max_devfn maximum devfn to look at in the scan usually 0xff - * @param max current bus number - * - * @return The maximum bus number found, after scanning all subordinate busses + * @param bus Pointer to the bus structure. + * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. + * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. + * @param max Current bus number. + * @return The maximum bus number found, after scanning all subordinate busses. */ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, @@ -1084,7 +1083,7 @@ } /** - * @brief Scan a PCI bridge and the buses behind the bridge. + * Scan a PCI bridge and the buses behind the bridge. * * Determine the existence of buses behind the bridge. Set up the bridge * according to the result of the scan. @@ -1093,6 +1092,7 @@ * * @param dev Pointer to the bridge device. * @param max The highest bus number assigned up to now. + * @param do_scan_bus TODO * @return The maximum bus number found, after scanning all subordinate buses. */ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, @@ -1164,7 +1164,7 @@ } /** - * @brief Scan a PCI bridge and the buses behind the bridge. + * Scan a PCI bridge and the buses behind the bridge. * * Determine the existence of buses behind the bridge. Set up the bridge * according to the result of the scan. @@ -1181,14 +1181,13 @@ } /** - * @brief Scan a PCI domain. + * Scan a PCI domain. * * This function is the default scan_bus() method for PCI domains. * - * @param dev pointer to the domain - * @param max the highest bus number assgined up to now - * - * @return The maximum bus number found, after scanning all subordinate busses + * @param dev Pointer to the domain. + * @param max The highest bus number assigned up to now. + * @return The maximum bus number found, after scanning all subordinate busses. */ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) { @@ -1198,8 +1197,7 @@ #if CONFIG_PC80_SYSTEM == 1 /** - * - * @brief Assign IRQ numbers + * Assign IRQ numbers. * * This function assigns IRQs for all functions contained within the indicated * device address. If the device does not exist or does not require interrupts @@ -1207,12 +1205,11 @@ * * This function should be called for each PCI slot in your system. * - * @param bus - * @param slot - * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through - * PINTD of this slot. The particular irq #s that are passed in - * depend on the routing inside your southbridge and on your - * motherboard. + * @param bus Pointer to the bus structure. + * @param slot TODO + * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD + * of this slot. The particular IRQ #s that are passed in depend on the + * routing inside your southbridge and on your board. */ void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]) Modified: trunk/src/devices/pci_ops.c ============================================================================== --- trunk/src/devices/pci_ops.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/pci_ops.c Sun Oct 17 21:01:48 2010 (r5955) @@ -25,7 +25,8 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -/* The only consumer of the return value of get_pbus() is ops_pci_bus(). +/* + * The only consumer of the return value of get_pbus() is ops_pci_bus(). * ops_pci_bus() can handle being passed NULL and auto-picks working ops. */ static struct bus *get_pbus(device_t dev) Modified: trunk/src/devices/pci_rom.c ============================================================================== --- trunk/src/devices/pci_rom.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/pci_rom.c Sun Oct 17 21:01:48 2010 (r5955) @@ -29,7 +29,7 @@ #include <string.h> #include <cbfs.h> -struct rom_header * pci_rom_probe(struct device *dev) +struct rom_header *pci_rom_probe(struct device *dev) { struct rom_header *rom_header; struct pci_data *rom_data; Modified: trunk/src/devices/pciexp_device.c ============================================================================== --- trunk/src/devices/pciexp_device.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/pciexp_device.c Sun Oct 17 21:01:48 2010 (r5955) @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <device/pciexp.h> - static void pciexp_tune_dev(device_t dev) { unsigned cap; @@ -63,7 +62,6 @@ return max; } - unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) { return do_pci_scan_bridge(dev, max, pciexp_scan_bus); Modified: trunk/src/devices/pcix_device.c ============================================================================== --- trunk/src/devices/pcix_device.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/pcix_device.c Sun Oct 17 21:01:48 2010 (r5955) @@ -24,7 +24,6 @@ #include <device/pci_ids.h> #include <device/pcix.h> - static void pcix_tune_dev(device_t dev) { unsigned cap; @@ -130,7 +129,6 @@ return max; } - /** Default device operations for PCI-X bridges */ static struct pci_operations pcix_bus_ops_pci = { .set_subsystem = 0, Modified: trunk/src/devices/root_device.c ============================================================================== --- trunk/src/devices/root_device.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/root_device.c Sun Oct 17 21:01:48 2010 (r5955) @@ -28,9 +28,10 @@ #include <reset.h> /** - * Read the resources for the root device, - * that encompass the resources for the entire system. - * @param root Pointer to the device structure for the system root device + * Read the resources for the root device, that encompass the resources for + * the entire system. + * + * @param root Pointer to the device structure for the system root device. */ static void root_dev_read_resources(device_t root) { @@ -38,11 +39,12 @@ } /** - * @brief Write the resources for every device + * Write the resources for every device. + * + * Write the resources for the root device, and every device under it which + * are all of the devices. * - * Write the resources for the root device, - * and every device under it which are all of the devices. - * @param root Pointer to the device structure for the system root device + * @param root Pointer to the device structure for the system root device. */ static void root_dev_set_resources(device_t root) { @@ -50,7 +52,7 @@ } /** - * @brief Scan devices on static buses. + * Scan devices on static buses. * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time @@ -67,8 +69,8 @@ * This function is the default scan_bus() method for the root device and * LPC bridges. * - * @param bus Pointer to the device structure which the static buses are attached - * @param max Maximum bus number currently used before scanning. + * @param bus Pointer to the device to which the static buses are attached to. + * @param max Maximum bus number currently used before scanning. * @return Largest bus number used. */ static int smbus_max = 0; @@ -120,12 +122,13 @@ } /** - * @brief Scan root bus for generic systems - * - * @param root The root device structure - * @param max The current bus number scanned so far, usually 0x00 + * Scan root bus for generic systems. * * This function is the default scan_bus() method of the root device. + * + * @param root The root device structure. + * @param max The current bus number scanned so far, usually 0x00. + * @return TODO. */ static unsigned int root_dev_scan_bus(device_t root, unsigned int max) { @@ -143,10 +146,10 @@ } /** - * @brief Default device operation for root device + * Default device operation for root device. * * This is the default device operation for root devices. These operations - * should be fully usable as is. However the chip_operations::enable_dev() + * should be fully usable as is. However the chip_operations::enable_dev() * of a motherboard can override this if you want non-default behavior. */ struct device_operations default_dev_ops_root = { Modified: trunk/src/devices/smbus_ops.c ============================================================================== --- trunk/src/devices/smbus_ops.c Sat Oct 16 10:45:31 2010 (r5954) +++ trunk/src/devices/smbus_ops.c Sun Oct 17 21:01:48 2010 (r5955) @@ -38,11 +38,15 @@ return pbus; } -/*multi level i2c MUX??? may need to find the first i2c device and then set link - * down to current dev - 1 store get_pbus_smbus list link - 2 reverse the link and call set link */ - +/* + * Multi-level I2C MUX? may need to find the first i2c device and then set link + * down to current dev. + * + * 1 store get_pbus_smbus list link + * 2 reverse the link and call set link. + * + * @param dev TODO. + */ int smbus_set_link(device_t dev) { struct bus *pbus_a[4]; // 4 level mux only. Enough? @@ -110,5 +114,3 @@ { return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, bytes, buffer); } - -

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coreboot October 2010