[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

[Uwe Hermann]

See patch.

Next steps will be:

- Remove .c file includes from 440BX board's romstage.c files.

- Add L2 cache support from Keith Hui, and split CPU models before
   that, as needed by that patch.

Uwe.

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

[Patrick Georgi]

Am 06.10.2010 19:17, schrieb Uwe Hermann:
> Convert all Intel 440BX boards to Cache-as-RAM (CAR).
>
> Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.
>
> Add the following in src/cpu/intel/slot_1/Makefile.inc:
> cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
>
> Remove "select ROMCC" from all 440BX board Kconfig files.
>
> Drop all early_mtrr_init() calls, that's done by CAR code now.
>
> Various small fixes were needed to make it build:
>
> Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
> those were never called anyways.
>
> Remove the "static" from the main() functions in romstage.c files.
>
> Always call dump_spd_registers() from the 440BX debug.c, but use
> "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
> is enabled in menuconfig.
>
> Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
> commented out) from romstage.c's, as we've done for most other boards.
>
> Add missing #includes or prototypes. Some of the prototypes will be
> removed later when we get rid of the #include'd .c files.
>
> Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.
>
> Signed-off-by: Uwe Hermann

Acked-by: Patrick Georgi

It looks good, thanks for doing this

Regards
Patrick

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

[Idwer Vollering]

2010/10/6 Uwe Hermann
> See patch.

Here is a fix for building on 32-bit platforms:

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c      (revision 5917)
+++ src/northbridge/intel/i440bx/raminit.c      (working copy)
@@ -657,8 +657,8 @@
 }

struct dimm_size {
-       unsigned long side1;
-       unsigned long side2;
+       uint32_t side1;
+       uint32_t side2;
 };

static struct dimm_size spd_get_dimm_size(unsigned int device)
> Next steps will be:
>
> Remove .c file includes from 440BX board's romstage.c files.
>
> Add L2 cache support from Keith Hui, and split CPU models before
>
> that, as needed by that patch.
> Uwe.
>
> http://hermann-uwe.de     | http://sigrok.org
> http://randomprojects.org | http://unmaintained-free-software.org

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

[Stefan Reinauer]

On 10/6/10 2:27 PM, Idwer Vollering wrote:
> 2010/10/6 Uwe Hermann <[e-mail] >
> See patch.
>
>
> Here is a fix for building on 32-bit platforms:
> Index: src/northbridge/intel/i440bx/raminit.c
>
> --- src/northbridge/intel/i440bx/raminit.c      (revision 5917)
> +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
> @@ -657,8 +657,8 @@
>  }
>
> struct dimm_size {
>   unsigned long side1;
>   unsigned long side2;
>   uint32_t side1;
>   uint32_t side2;
>
> };

What's that error? It seems the above should be about the same on 32bit
platforms, especially it should be the same on 32bit platforms and 64bit
platforms, since the code is always compiled 32bit...
What did I miss?

Stefan

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

[Idwer Vollering]

2010/10/7 Stefan Reinauer
> On 10/6/10 2:27 PM, Idwer Vollering wrote:
>
> 2010/10/6 Uwe Hermann
> > See patch.
>
> Here is a fix for building on 32-bit platforms:
> Index: src/northbridge/intel/i440bx/raminit.c
>
> --- src/northbridge/intel/i440bx/raminit.c      (revision 5917)
> +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
> @@ -657,8 +657,8 @@
>  }
>
> struct dimm_size {
>   unsigned long side1;
>   unsigned long side2;
>   uint32_t side1;
>   uint32_t side2;
>
> };
>
> What's that error?

In file included from src/mainboard/asus/p2b/romstage.c:46:
src/northbridge/intel/i440bx/raminit.c: In function ‘spd_get_dimm_size’:
src/northbridge/intel/i440bx/raminit.c:717: error: format ‘%04x’ expects
type ‘unsigned int’, but argument 3 has type ‘long unsigned int’
> It seems the above should be about the same on 32bit platforms, especially
> it should be the same on 32bit platforms and 64bit platforms, since the code
> is always compiled 32bit...
> What did I miss?

Should it be something else than uint32_t ? Plain int ?
> Stefan

[PATCH] Convert all Intel 440BX boards to Cache-as-RAM (CAR)

Idwer Vollering  writes:
> 2010/10/7 Stefan Reinauer
> On 10/6/10 2:27 PM, Idwer Vollering wrote:
>
>     2010/10/6 Uwe Hermann <[e-mail]>
>
>         See patch.
>
>
>     Here is a fix for building on 32-bit platforms:
>
>     Index: src/northbridge/intel/i440bx/raminit.c
>     ===================================================================
>     --- src/northbridge/intel/i440bx/raminit.c      (revision 5917)
>     +++ src/northbridge/intel/i440bx/raminit.c      (working copy)
>     @@ -657,8 +657,8 @@
>      }
>
>      struct dimm_size {
>     -       unsigned long side1;
>     -       unsigned long side2;
>     +       uint32_t side1;
>     +       uint32_t side2;
>      };
>
>
> What's that error?
>
>
> In file included from src/mainboard/asus/p2b/romstage.c:46:
> src/northbridge/intel/i440bx/raminit.c: In function ‘spd_get_dimm_size’:
> src/northbridge/intel/i440bx/raminit.c:717: error: format ‘%04x’ expects type
> ‘unsigned int’, but argument 3 has type ‘long unsigned int’
> It seems the above should be about the same on 32bit platforms, especially
> it should be the same on 32bit platforms and 64bit platforms, since the
> code is always compiled 32bit...
> What did I miss?
>
>
> Should it be something else than uint32_t ? Plain int ?

%04lx?

uint32_t could be typedef'd to either unsigned long or unsigned on
a 32bit platform.  Using it is unlikely to deterministically solve
any printf format woes.

Eric