coreboot October 2010

coreboot@coreboot.org

55 participants
316 discussions

[commit] r5908 - in trunk/src/cpu: amd/car intel/car intel/model_106cx intel/model_6ex intel/model_6fx via/car
by repository service 02 Oct '10

02 Oct '10

Author: uwe Date: Sat Oct 2 22:51:29 2010 New Revision: 5908 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5908 Log: Add comments to make it clear why these two lines are written like that: movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -269,6 +269,11 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -221,6 +221,11 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -97,6 +97,11 @@ #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -97,6 +97,11 @@ #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -104,6 +104,11 @@ #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Sat Oct 2 22:36:26 2010 (r5907) +++ trunk/src/cpu/via/car/cache_as_ram.inc Sat Oct 2 22:51:29 2010 (r5908) @@ -97,6 +97,11 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx + /* + * IMPORTANT: The two lines below can _not_ be written like this: + * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ movl $REAL_XIP_ROM_BASE, %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr

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[PATCH] Drop unneeded header from i82371eb_enable_rom.c
by Keith Hui 02 Oct '10

02 Oct '10

A "I am alive" ping kind of patch while I continue to figure out ACPI for 440BX boards among other things. Drops <stdint.h> from the file. My coreboot still compiles fine without it. abuild tested. Signed-off-by: Keith Hui <buurin(a)gmail.com>

6 6

[commit] r5907 - in trunk/src: mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh mainboard/asus/m4a785-m mainboard/gigabyte/ma785gmt mainbo...
by repository service 02 Oct '10

02 Oct '10

Author: uwe Date: Sat Oct 2 22:36:26 2010 New Revision: 5907 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5907 Log: Allow selecting the physical USB Debug Port on AMD SB700. The AMD SB700 allows changing the physical USB port to be used as USB Debug Port, implement support for this. Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices currently, AFAICS. Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility. Untested, but should work. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/amd/mahogany/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -128,7 +128,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -145,7 +145,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -145,7 +145,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -182,7 +182,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -146,7 +146,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -141,7 +141,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -145,7 +145,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -148,7 +148,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sat Oct 2 22:36:26 2010 (r5907) @@ -152,7 +152,7 @@ uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(0); + sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif Modified: trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sat Oct 2 22:33:56 2010 (r5906) +++ trunk/src/southbridge/amd/sb700/sb700_enable_usbdebug.c Sat Oct 2 22:36:26 2010 (r5907) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,22 +26,39 @@ #define EHCI_BAR_INDEX 0x10 /* TODO: DBUG_PRT[31:29] */ #define EHCI_DEBUG_OFFSET 0xE0 /* Hardcoded to 0xE0 */ -/* Required for successful build, but currently empty. */ +#define EHCI_EOR (EHCI_BAR + 0x20) +#define DEBUGPORT_MISC_CONTROL (EHCI_EOR + 0x80) + void set_debug_port(unsigned int port) { - /* TODO: Allow changing the physical USB port used as Debug Port. */ + u32 reg32; + + /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ + reg32 = read32(DEBUGPORT_MISC_CONTROL); + reg32 &= ~(0xf << 28); + reg32 |= (port << 28); + reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ + write32(DEBUGPORT_MISC_CONTROL, reg32); } +/* + * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. + * This code currently only supports the first one, i.e., USB Debug devices + * attached to physical USB ports belonging to the first EHCI device. + */ static void sb700_enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */ - - /* Select the requested physical USB port (1-15) as the Debug Port. */ - set_debug_port(port); + device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* + * Select the requested physical USB port (1-15) as the Debug Port. + * Must be called after the EHCI BAR has been set up (see above). + */ + set_debug_port(port); }

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[commit] r5906 - trunk/src/console
by repository service 02 Oct '10

02 Oct '10

Author: uwe Date: Sat Oct 2 22:33:56 2010 New Revision: 5906 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5906 Log: AMD SB600 uses a hardcoded USB Debug Port number. It cannot be changed via software according to the datasheet, whereas this is indeed possible on AMD SB700. I tested using the SB700 mechanism on SB600 but it didn't work, so I suspect the datasheet is indeed correct. Thus, don't show the kconfig option for selecting the physical USB port on the AMD SB600 southbridge. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/console/Kconfig Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Sat Oct 2 16:10:08 2010 (r5905) +++ trunk/src/console/Kconfig Sat Oct 2 22:33:56 2010 (r5906) @@ -112,13 +112,13 @@ If unsure, say N. -# Note: This option doesn't make sense on Intel ICH southbridges as those -# hardcode the physical USB port to be used as Debug Port to 1. It cannot -# be changed by coreboot. +# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges +# as those hardcode the physical USB port to be used as Debug Port to 1. +# It cannot be changed by coreboot. config USBDEBUG_DEFAULT_PORT int "Default USB port to use as Debug Port" default 1 - depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX + depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600 help This option selects which physical USB port coreboot will try to use as EHCI Debug Port first (valid values are: 1-15).

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[PATCH] Allow selecting the physical USB Debug Port on AMD SB700
by Uwe Hermann 02 Oct '10

02 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 1

[PATCH] AMD SB600 uses a hardcoded USB Debug Port number
by Uwe Hermann 02 Oct '10

02 Oct '10

See patch. Will post a patch for changing the port on SB700 soon, on that southbridge it is indeed possible according to the datasheet. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 1

[commit] r5905 - in trunk/src/mainboard: asus/a8v-e_se asus/m2v-mx_se msi/ms9282
by repository service 02 Oct '10

02 Oct '10

Author: uwe Date: Sat Oct 2 16:10:08 2010 New Revision: 5905 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5905 Log: Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it. All these boards define QRANK_DIMM_SUPPORT anyway, which is probably what was meant. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sat Oct 2 14:51:38 2010 (r5904) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sat Oct 2 16:10:08 2010 (r5905) @@ -98,8 +98,6 @@ // defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" -#define K8_4RANK_DIMM_SUPPORT 1 - #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sat Oct 2 14:51:38 2010 (r5904) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sat Oct 2 16:10:08 2010 (r5905) @@ -80,8 +80,6 @@ // defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" -#define K8_4RANK_DIMM_SUPPORT 1 - #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Sat Oct 2 14:51:38 2010 (r5904) +++ trunk/src/mainboard/msi/ms9282/romstage.c Sat Oct 2 16:10:08 2010 (r5905) @@ -95,8 +95,6 @@ return smbus_read_byte(device, address); } -//#define K8_4RANK_DIMM_SUPPORT 1 - #include "northbridge/amd/amdk8/amdk8_f.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

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[patch] drop meaningless K8_4RANK_DIMM_SUPPORT define
by Jonathan A. Kollasch 02 Oct '10

02 Oct '10

Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it. All these boards define QRANK_DIMM_SUPPORT anyway, which is probably what was meant. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

2 1

[commit] r5904 - trunk/src/northbridge/amd/amdk8
by repository service 02 Oct '10

02 Oct '10

Author: uwe Date: Sat Oct 2 14:51:38 2010 New Revision: 5904 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5904 Log: Fix spelling/typos in comments. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/amd/amdk8/misc_control.c Modified: trunk/src/northbridge/amd/amdk8/misc_control.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/misc_control.c Fri Oct 1 23:48:52 2010 (r5903) +++ trunk/src/northbridge/amd/amdk8/misc_control.c Sat Oct 2 14:51:38 2010 (r5904) @@ -1,6 +1,6 @@ /* Turn off machine check triggers when reading - * pci space where there are no devices. - * This is necessary when scaning the bus for + * PCI space where there are no devices. + * This is necessary when scanning the bus for * devices which is done by the kernel * * written in 2003 by Eric Biederman @@ -26,13 +26,13 @@ * * @param * - * There is only one AGP aperture resource needed. The resoruce is added to + * There is only one AGP aperture resource needed. The resource is added to * the northbridge of BSP. * * The same trick can be used to augment legacy VGA resources which can - * be detect by generic pci reousrce allocator for VGA devices. + * be detect by generic PCI resource allocator for VGA devices. * BAD: it is more tricky than I think, the resource allocation code is - * implemented in a way to NOT DOING legacy VGA resource allcation on + * implemented in a way to NOT DOING legacy VGA resource allocation on * purpose :-(. */ static void mcf3_read_resources(device_t dev) @@ -42,7 +42,7 @@ /* Read the generic PCI resources */ pci_dev_read_resources(dev); - /* If we are not the first processor don't allocate the gart apeture */ + /* If we are not the first processor don't allocate the GART aperture */ if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) { return; } @@ -51,7 +51,7 @@ get_option(&iommu, "iommu"); if (iommu) { - /* Add a Gart apeture resource */ + /* Add a GART aperture resource */ resource = new_resource(dev, 0x94); resource->size = CONFIG_AGP_APERTURE_SIZE; resource->align = log2(resource->size); @@ -79,7 +79,7 @@ /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; - /* Update the other northbriges */ + /* Update the other northbridges */ pdev = 0; while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) { /* Store the GART size but don't enable it */

1 0

[patch] spelling fixes for comments in src/northbridge/amd/amdk8/misc_control.c
by Jonathan A. Kollasch 02 Oct '10

02 Oct '10

Fix spelling/typos in comments. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

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coreboot October 2010