coreboot October 2010

coreboot@coreboot.org

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316 discussions

[commit] r5897 - trunk/src/cpu/via/car
by repository service 02 Oct '10

02 Oct '10

Author: stepan Date: Fri Oct 1 14:24:57 2010 New Revision: 5897 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5897 Log: fix VIA C7 code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 13:34:05 2010 (r5896) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 14:24:57 2010 (r5897) @@ -100,7 +100,8 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -243,7 +244,8 @@ /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ movl $MTRRphysBase_MSR(3), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(3), %ecx

3 2

BBC EFI story
by ron minnich 02 Oct '10

02 Oct '10

This story is full of errors. I thought I'd point out a few. "New PCs could start in just seconds, thanks to an update to one of the oldest parts of desktop computers." I've got news for the UEFI forum: OLD computers, starting 10 years ago, have been starting in seconds, thanks to the coreboot project. We first showed a 12 second boot at the Atlanta Linux Symposium in Oct. 2000. It is hardly news that one can boot a computer quickly. The project then was called LinuxBIOS; the project today is called Coreboot. Coreboot works on embedded systems, desktops, laptops, and supercomputers. It has run in the iRobot packbot for 10 years, searching mines and saving lives. Some of the biggest supercomputers in the world have run coreboot. Work on coreboot was, in fact, funded first by the US Gov't (Dept. of Energy) and more recently by the German Government (see, for example, http://www.coreboot.org/pipermail/coreboot-announce/2010-May/000007.html) So why, might you ask, did vendors not pick this technology up 10 years ago? Technology that worked on x86, 64-bit x86, Power PC, and DEC Alpha? The reason is simple: it's open source. And, while vendors finally did decide that an open source operating system might be acceptable, they have had a lot of trouble accepting an open source BIOS. They feel that too much information is divulged if the BIOS is open source. They make a lot of excuses, but in the end, they finally admit that the issue is that they don't want the hardware to be that open. "The upgrade will spell the end for the 25-year-old PC start-up software known as Bios that initialises a machine so its operating system can get going." The BIOS could have been ended ten years ago, but for a simple fact: many customers don't much like EFI. It's clumsy, slow, and closed. And it's hard to work around, as it is designed to hide information. "The code was not intended to live nearly this long, and adapting it to modern PCs is one reason they take as long as they do to warm up." There's a lot more to it than that. The closed nature of the BIOS software made it very hard to replace. And, again, the vendors have shown time and again that they prefer a closed, proprietary solution to an open source solution. That's the real problem. "Alternatives to UEFI, such as Open Firmware and Coreboot, do exist and are typically used on computers that do not run chips based on Intel's x86 architecture." This statement is completely wrong. Coreboot has run on x86 systems from the start and, in fact, only runs on x86 systems now. Open Firmware also runs on x86 systems and is in fact the BIOS for the One Laptop Per Child project -- an x86 system. ""At the moment it can be 25-30 seconds of boot time before you see the first bit of OS sign-on," he said. "With UEFI we're getting it under a handful of seconds."" It's nice to see UEFI catching up only 10 years later; the first versions took 10 minutes to boot. Automobile computers, using ARM processors, and an open source BIOS called U-boot, boot Linux in 8/10 of a second. So, while UEFI is where coreboot was ten years ago, we've all moved on; seconds is kind of slow nowadays. "He said that 2011 would be the year that sales of UEFI machines start to dominate." Dominate what? Certainly not cell phones. Certainly not the ipad. In fact, UEFI is going to dominate a segment that matters less and less nowadays -- PC-compatible desktops and laptops. I think you can do better than this article; the BBC is one of the finest news organizations in the world. It seems you took a puff-piece from the UEFI group and removed the quotes. I'm very disappointed in the BBC. Thanks Ron Minnich Founder, LinuxBIOS, which is now coreboot.

3 2

[Patch] Quieter build
by Myles Watson 01 Oct '10

01 Oct '10

I'd like to redirect the output of iasl to a file. Patch attached. Here's a little justification: http://qa.coreboot.org/log_buildbrd.php?revision=5900&device=serengeti_chee… Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[commit] r5903 - trunk
by repository service 01 Oct '10

01 Oct '10

Author: myles Date: Fri Oct 1 23:48:52 2010 New Revision: 5903 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5903 Log: Redirect the output of iasl to a file to make the build quieter. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Oct 1 23:46:04 2010 (r5902) +++ trunk/Makefile Fri Oct 1 23:48:52 2010 (r5903) @@ -229,7 +229,7 @@ $(obj)/$(1).ramstage.o: src/$(1).asl @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CPP) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl - iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl + iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl > $$(basename $$(a)).asl.out mv $$(obj)/$(1).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c # keep %.o: %.c rule from catching the temporary .c file after a make clean

1 0

[commit] r5901 - in trunk/src/cpu/intel: model_106cx model_6ex model_6fx
by repository service 01 Oct '10

01 Oct '10

Author: uwe Date: Fri Oct 1 19:37:45 2010 New Revision: 5901 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5901 Log: Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial). This is abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 17:23:41 2010 (r5900) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) @@ -18,140 +18,140 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> - /* Save the BIST result */ - movl %eax, %ebp +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) - /* Zero out all Fixed Range and Variable Range MTRRs */ + /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $( (mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + movw (%esi), %bx + movzx %bx, %ecx wrmsr add $2, %esi dec %edi jnz clear_mtrrs - /* Configure the default memory type to uncacheable */ + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr - /* Set cache as ram base address */ + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - /* Set cache as ram mask */ + /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax xorl %edx, %edx wrmsr - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax wrmsr - /* Enable L2 Cache */ + /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr - /* CR0.CD = 0, CR0.NW = 0 */ + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 - /* Clear the cache memory reagion */ + /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi movl $(CACHE_AS_RAM_SIZE / 4), %ecx - //movl $0x23322332, %eax + // movl $0x23322332, %eax xorl %eax, %eax rep stosl - /* Enable Cache As RAM mode by disabling cache */ + /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr - movl $MTRRphysMask_MSR(1), %ecx + movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax - wrmsr + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* enable cache */ - movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 - /* Set up stack pointer */ + /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) - /* leave some space for the struct ehci_debug_info */ + /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax #endif movl %eax, %esp - /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp pushl %eax post_code(0x23) - /* Call romstage.c main function */ + /* Call romstage.c main function. */ call main post_code(0x2f) post_code(0x30) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x31) - /* Disable MTRR */ + /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~(1 << 11)), %eax @@ -175,40 +175,40 @@ post_code(0x33) - /* Enable Cache */ + /* Enable cache. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 post_code(0x36) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB */ + /* Enable Write Back and Speculative Reads for the first 1MB. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax xorl %edx, %edx wrmsr post_code(0x39) - /* And Enable Cache again after setting MTRRs */ + /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 post_code(0x3a) - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax @@ -216,23 +216,23 @@ post_code(0x3b) - /* Invalidate the cache again */ + /* Invalidate the cache again. */ invd post_code(0x3c) - /* clear boot_complete flag */ + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: post_code(0x11) - cld /* clear direction flag */ + cld /* Clear direction flag. */ movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi - call copy_and_run + pushl %esi + call copy_and_run .Lhlt: post_code(0xee) @@ -241,14 +241,14 @@ mtrr_table: /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F mtrr_table_end: Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 17:23:41 2010 (r5900) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) @@ -18,140 +18,140 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> - /* Save the BIST result */ - movl %eax, %ebp +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) - /* Zero out all Fixed Range and Variable Range MTRRs */ + /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $( (mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + movw (%esi), %bx + movzx %bx, %ecx wrmsr add $2, %esi dec %edi jnz clear_mtrrs - /* Configure the default memory type to uncacheable */ + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr - /* Set cache as ram base address */ + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - /* Set cache as ram mask */ + /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax movl $0x0000000f, %edx wrmsr - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax wrmsr - /* Enable L2 Cache */ + /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr - /* CR0.CD = 0, CR0.NW = 0 */ + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 - /* Clear the cache memory reagion */ + /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi movl $(CACHE_AS_RAM_SIZE / 4), %ecx - //movl $0x23322332, %eax + // movl $0x23322332, %eax xorl %eax, %eax rep stosl - /* Enable Cache As RAM mode by disabling cache */ + /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax - wrmsr + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* enable cache */ - movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 - /* Set up stack pointer */ + /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) - /* leave some space for the struct ehci_debug_info */ + /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax #endif movl %eax, %esp - /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp pushl %eax post_code(0x23) - /* Call romstage.c main function */ + /* Call romstage.c main function. */ call main post_code(0x2f) post_code(0x30) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x31) - /* Disable MTRR */ + /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~(1 << 11)), %eax @@ -175,41 +175,40 @@ post_code(0x33) - /* Enable Cache */ + /* Enable cache. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 - post_code(0x36) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB */ + /* Enable Write Back and Speculative Reads for the first 1MB. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax movl $0x0000000f, %edx // 36bit address space wrmsr post_code(0x39) - /* And Enable Cache again after setting MTRRs */ + /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 post_code(0x3a) - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax @@ -217,23 +216,23 @@ post_code(0x3b) - /* Invalidate the cache again */ + /* Invalidate the cache again. */ invd post_code(0x3c) - /* clear boot_complete flag */ + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: post_code(0x11) - cld /* clear direction flag */ + cld /* Clear direction flag. */ movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi - call copy_and_run + pushl %esi + call copy_and_run .Lhlt: post_code(0xee) @@ -242,14 +241,14 @@ mtrr_table: /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F mtrr_table_end: Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 17:23:41 2010 (r5900) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Fri Oct 1 19:37:45 2010 (r5901) @@ -18,22 +18,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> - /* Save the BIST result */ - movl %eax, %ebp +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) /* Disable prefetchers */ movl $0x01a0, %ecx @@ -42,123 +42,123 @@ orl $((1 << 5) | (1 << 7)), %edx wrmsr - /* Zero out all Fixed Range and Variable Range MTRRs */ + /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $( (mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx + movw (%esi), %bx + movzx %bx, %ecx wrmsr add $2, %esi dec %edi jnz clear_mtrrs - /* Configure the default memory type to uncacheable */ + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr - /* Set cache as ram base address */ + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - /* Set cache as ram mask */ + /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax + movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax movl $0x0000000f, %edx wrmsr - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax wrmsr - /* Enable L2 Cache */ + /* Enable L2 cache. */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr - /* CR0.CD = 0, CR0.NW = 0 */ + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 - /* Clear the cache memory reagion */ + /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi movl $(CACHE_AS_RAM_SIZE / 4), %ecx - //movl $0x23322332, %eax + // movl $0x23322332, %eax xorl %eax, %eax rep stosl - /* Enable Cache As RAM mode by disabling cache */ + /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax movl %eax, %cr0 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax - wrmsr + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - /* enable cache */ - movl %cr0, %eax - andl $( ~( (1 << 30) | (1 << 29) ) ), %eax + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 - /* Set up stack pointer */ + /* Set up the stack pointer. */ #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1) - /* leave some space for the struct ehci_debug_info */ + /* Leave some space for the struct ehci_debug_info. */ movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax #else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax #endif movl %eax, %esp - /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp pushl %eax post_code(0x23) - /* Call romstage.c main function */ + /* Call romstage.c main function. */ call main post_code(0x2f) post_code(0x30) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x31) - /* Disable MTRR */ + /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~(1 << 11)), %eax @@ -182,40 +182,40 @@ post_code(0x33) - /* Enable Cache */ + /* Enable cache. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 post_code(0x36) - /* Disable Cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $(1 << 30), %eax movl %eax, %cr0 post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB */ + /* Enable Write Back and Speculative Reads for the first 1MB. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax movl $0x0000000f, %edx // 36bit address space wrmsr post_code(0x39) - /* And Enable Cache again after setting MTRRs */ + /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~( (1 << 30) | (1 << 29) ), %eax + andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 post_code(0x3a) - /* Enable MTRR */ + /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax @@ -230,23 +230,23 @@ andl $~((1 << 5) | (1 << 7)), %edx wrmsr - /* Invalidate the cache again */ + /* Invalidate the cache again. */ invd post_code(0x3c) - /* clear boot_complete flag */ + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: post_code(0x11) - cld /* clear direction flag */ + cld /* Clear direction flag. */ movl %ebp, %esi - movl $ROMSTAGE_STACK, %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi - call copy_and_run + pushl %esi + call copy_and_run .Lhlt: post_code(0xee) @@ -255,14 +255,14 @@ mtrr_table: /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F mtrr_table_end:

3 3

[commit] r5900 - trunk/src/lib
by repository service 01 Oct '10

01 Oct '10

Author: myles Date: Fri Oct 1 17:23:41 2010 New Revision: 5900 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5900 Log: Fix make warnings: Makefile:261: warning: overriding commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o' Makefile:261: warning: ignoring old commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o' lzma.c is already included unconditionally in the same file. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/lib/Makefile.inc Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Fri Oct 1 17:16:20 2010 (r5899) +++ trunk/src/lib/Makefile.inc Fri Oct 1 17:23:41 2010 (r5900) @@ -28,8 +28,6 @@ ramstage-$(CONFIG_USBDEBUG) += usbdebug.c -ramstage-$(CONFIG_COMPRESSED_PAYLOAD_LZMA) += lzma.c - ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c smm-y += memcpy.c

3 4

build service results for r5899
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5899 to the coreboot repository. This caused the following changes: Change Log: Fix some breakage from 5890. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of digitallogic:adl855pc has been fixed Compilation of intel:d810e2cb has been fixed Compilation of lanner:em8510 has been fixed Compilation of rca:rm4100 has been fixed Compilation of thomson:ip1000 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5899 - trunk/src/cpu/intel/car
by repository service 01 Oct '10

01 Oct '10

Author: myles Date: Fri Oct 1 17:16:20 2010 New Revision: 5899 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5899 Log: Fix some breakage from 5890. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/intel/car/cache_as_ram.inc Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 16:50:12 2010 (r5898) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 17:16:20 2010 (r5899) @@ -221,7 +221,8 @@ */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx

1 0

build service results for r5898
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5898 to the coreboot repository. This caused the following changes: Change Log: Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig, rename it slightly, make it visible only on relevant northbridges, drop it entirely from via boards (as they seem to have picked it up from AMD code without using it themselves), and make it default to false for all boards. Some romstages used to set this to "true" (ie. "print debug output"), but I didn't follow up on it in Kconfig - if you need it to debug CAR, enable it yourself. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=adl855pc&vendo… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=d810e2cb&vendo… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=rm4100&vendor=… Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5898&device=ip1000&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5898 - in trunk/src: . mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/amd/tilapia_fam10 mainboard/asus/a8v-e_se mainboard/asu...
by repository service 01 Oct '10

01 Oct '10

Author: oxygene Date: Fri Oct 1 16:50:12 2010 New Revision: 5898 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5898 Log: Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig, rename it slightly, make it visible only on relevant northbridges, drop it entirely from via boards (as they seem to have picked it up from AMD code without using it themselves), and make it default to false for all boards. Some romstages used to set this to "true" (ie. "print debug output"), but I didn't follow up on it in Kconfig - if you need it to debug CAR, enable it yourself. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/Kconfig trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdfam10/debug.c trunk/src/northbridge/amd/amdk8/Kconfig trunk/src/northbridge/amd/amdk8/debug.c trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/Kconfig Fri Oct 1 16:50:12 2010 (r5898) @@ -499,6 +499,16 @@ If unsure, say N. +config HAVE_DEBUG_CAR + def_bool n + +config DEBUG_CAR + bool "Output verbose Cache-as-RAM debug messages" + default n + depends on HAVE_DEBUG_CAR + help + This option enables additional CAR related debug messages. + config DEBUG_PIRQ bool "Check PIRQ table consistency" default n Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -2,7 +2,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -24,8 +24,6 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -24,8 +24,6 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -25,7 +25,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -24,7 +24,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 /* Used by RAM init. */ #define QRANK_DIMM_SUPPORT 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/msi/ms7260/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -20,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define RAM_TIMING_DEBUG 1 // #define DQS_TRAIN_DEBUG 1 // #define RES_DEBUG 1 Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/msi/ms9185/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -24,7 +24,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/msi/ms9282/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/mainboard/via/epia-m700/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -23,7 +23,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define PAYLOAD_IS_SEABIOS 0 #include <stdint.h> Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Fri Oct 1 16:50:12 2010 (r5898) @@ -21,6 +21,7 @@ bool select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS + select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select MMCONF_SUPPORT Modified: trunk/src/northbridge/amd/amdfam10/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/debug.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/northbridge/amd/amdfam10/debug.c Fri Oct 1 16:50:12 2010 (r5898) @@ -26,7 +26,7 @@ static inline void print_debug_addr(const char *str, void *val) { -#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1 +#if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } Modified: trunk/src/northbridge/amd/amdk8/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdk8/Kconfig Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/northbridge/amd/amdk8/Kconfig Fri Oct 1 16:50:12 2010 (r5898) @@ -21,6 +21,7 @@ bool select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS + select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT config AGP_APERTURE_SIZE Modified: trunk/src/northbridge/amd/amdk8/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/debug.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/northbridge/amd/amdk8/debug.c Fri Oct 1 16:50:12 2010 (r5898) @@ -3,13 +3,9 @@ * */ -#ifndef CACHE_AS_RAM_ADDRESS_DEBUG -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#endif - static inline void print_debug_addr(const char *str, void *val) { -#if CACHE_AS_RAM_ADDRESS_DEBUG == 1 +#if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val); #endif } Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Fri Oct 1 14:24:57 2010 (r5897) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Fri Oct 1 16:50:12 2010 (r5898) @@ -21,7 +21,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #include <stdint.h> #include <device/pci_def.h>

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coreboot October 2010