coreboot October 2010

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316 discussions

[PATCH]Move CACHE_AS_RAM_ADDRESS_DEBUG to Kconfig, default to false
by Patrick Georgi 01 Oct '10

01 Oct '10

Hi, attached patch moves CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig, renames it slightly, makes it visible only on relevant northbridges, drops it entirely from via boards (as they seem to have picked it up from AMD code without using it themselves), and make it default to false for all boards. Some romstages used to set this to "true" (ie. "print debug output"), but I didn't follow up on it in Kconfig - if you need it to debug CAR, enable it yourself. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

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build service results for r5897
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5897 to the coreboot repository. This caused the following changes: Change Log: fix VIA C7 code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=adl855pc&vendo… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=d810e2cb&vendo… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=rm4100&vendor=… Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5897&device=ip1000&vendor=… Compilation of via:vt8454c has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Make via/vt8454c use the big bootblock.
by Warren Turkal 01 Oct '10

01 Oct '10

This change gets the board building again. Since it is late here, I am going to go to sleep. Anyone can feel free to commit this change if they ack it. Thanks, wt 8<------------------------------------------------------------------- The tiny boot block breaks cache-as-ram for this board. Specifically, the crt0s.romstage.o target will not build without this change. Signed-off-by: Warren Turkal <wt(a)penguintechs.org> --- src/mainboard/via/vt8454c/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index 6c08007..3ef94a3 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select TINY_BOOTBLOCK +# select TINY_BOOTBLOCK config MAINBOARD_DIR string -- 1.7.1

2 2

build service results for r5896
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5896 to the coreboot repository. This caused the following changes: Change Log: ICS951462_ADDRESS defined but _never_ used. Drop it. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=adl855pc&vendo… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=d810e2cb&vendo… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=rm4100&vendor=… Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=ip1000&vendor=… Compilation of via:vt8454c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5896&device=vt8454c&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5896 - in trunk/src/mainboard: amd/dbm690t amd/mahogany asrock/939a785gmh kontron/kt690 technexion/tim5690 technexion/tim8690
by repository service 01 Oct '10

01 Oct '10

Author: oxygene Date: Fri Oct 1 13:34:05 2010 New Revision: 5896 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5896 Log: ICS951462_ADDRESS defined but _never_ used. Drop it. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -30,7 +30,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/amd/mahogany/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -30,7 +30,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -31,7 +31,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/kontron/kt690/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -31,7 +31,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -30,7 +30,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Fri Oct 1 12:02:33 2010 (r5895) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Fri Oct 1 13:34:05 2010 (r5896) @@ -30,7 +30,6 @@ #define DIMM0 0x50 #define DIMM1 0x51 -#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h>

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build service results for r5895
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5895 to the coreboot repository. This caused the following changes: Change Log: Make i945/raminit.c:fsbclk() return u16 rather than int This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is thrown because the comparison in the last hunk is between u16 and -1 and can never be true. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=adl855pc&vendo… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=d810e2cb&vendo… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=rm4100&vendor=… Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=ip1000&vendor=… Compilation of via:vt8454c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5895&device=vt8454c&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5894
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5894 to the coreboot repository. This caused the following changes: Change Log: Remove a couple of defines that seem to be the result of copy&paste, without actually being used. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=adl855pc&vendo… Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=d810e2cb&vendo… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=rm4100&vendor=… Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=ip1000&vendor=… Compilation of via:vt8454c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5894&device=vt8454c&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5895 - trunk/src/northbridge/intel/i945
by repository service 01 Oct '10

01 Oct '10

Author: oxygene Date: Fri Oct 1 12:02:33 2010 New Revision: 5895 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5895 Log: Make i945/raminit.c:fsbclk() return u16 rather than int This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is thrown because the comparison in the last hunk is between u16 and -1 and can never be true. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/northbridge/intel/i945/raminit.c Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Fri Oct 1 11:58:44 2010 (r5894) +++ trunk/src/northbridge/intel/i945/raminit.c Fri Oct 1 12:02:33 2010 (r5895) @@ -103,7 +103,7 @@ } #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) -static int fsbclk(void) +static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 400; @@ -111,10 +111,10 @@ case 3: return 667; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } - return -1; + return 0xffff; } #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) -static int fsbclk(void) +static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 1066; @@ -122,7 +122,7 @@ case 2: return 800; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } - return -1; + return 0xffff; } #endif @@ -1929,7 +1929,7 @@ MCHBAR32(PLLMON) = 0x80800000; sysinfo->fsb_frequency = fsbclk(); - if (sysinfo->fsb_frequency == -1) + if (sysinfo->fsb_frequency == 0xffff) die("Unsupported FSB speed"); /* Program CPCTL according to FSB speed */

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[commit] r5894 - in trunk/src/mainboard: dell/s1850 intel/eagleheights intel/jarrell intel/mtarvon intel/truxton supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhe_g2 supermicro/x6dhr_ig superm...
by repository service 01 Oct '10

01 Oct '10

Author: oxygene Date: Fri Oct 1 11:58:44 2010 New Revision: 5894 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5894 Log: Remove a couple of defines that seem to be the result of copy&paste, without actually being used. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/dell/s1850/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) #define DEVPRES_CONFIG ( \ @@ -35,9 +32,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -59,9 +59,6 @@ #define UART_MSR 0x06 #define UART_SCR 0x07 -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/intel/jarrell/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -29,10 +29,6 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -/* Beta values: 0x00090800 */ -/* Silver values: 0x000a0900 */ -#define RECVENA_CONFIG 0x000a090a -#define RECVENB_CONFIG 0x000a090a #define DIMM_MAP_LOGICAL 0x0124 static inline int spd_read_byte(unsigned device, unsigned address) Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -38,9 +38,6 @@ #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/intel/truxton/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -40,9 +40,6 @@ #include "cpu/x86/bist.h" #include "spd.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) static inline int spd_read_byte(u16 device, u8 address) Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -21,9 +21,6 @@ #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -22,9 +22,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -37,9 +34,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) @@ -35,9 +32,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0708090a -#define RECVENB_CONFIG 0x0708090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Oct 1 11:13:18 2010 (r5893) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Oct 1 11:58:44 2010 (r5894) @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address);

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build service results for r5893
by repository service 01 Oct '10

01 Oct '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5893 to the coreboot repository. This caused the following changes: Change Log: Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM Both chipsets use the src/northbridge/intel/i945 code but that code needs to know which chipset is actually used. Having separate NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed since code can test the NORTHBRIDGE_ option directly. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=adl855pc&vendo… Compilation of getac:p470 has been fixed Compilation of ibase:mb899 has been fixed Compilation of intel:d810e2cb is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=d810e2cb&vendo… Compilation of intel:d945gclf has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=em8510&vendor=… Compilation of rca:rm4100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=rm4100&vendor=… Compilation of roda:rk886ex has been fixed Compilation of thomson:ip1000 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=ip1000&vendor=… Compilation of via:vt8454c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5893&device=vt8454c&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot October 2010