[commit] r5910 - in trunk: src/lib src/mainboard/amd/db800 src/mainboard/amd/mahogany_fam10 src/mainboard/amd/norwich src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard...
Author: oxygene Date: Tue Oct 5 11:07:10 2010 New Revision: 5910 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5910
Log: Remove lib/ramtest.c-include from all CAR boards. Remove many more .c-includes from i945 based boards.
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/lib/Makefile.inc trunk/src/lib/ramtest.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/d810e2cb/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/intel/i945/Makefile.inc trunk/src/northbridge/intel/i945/debug.c trunk/src/northbridge/intel/i945/early_init.c trunk/src/northbridge/intel/i945/errata.c trunk/src/northbridge/intel/i945/i945.h trunk/src/northbridge/intel/i945/raminit.c trunk/src/northbridge/intel/i945/raminit.h trunk/src/northbridge/intel/i945/udelay.c trunk/src/pc80/Makefile.inc trunk/src/southbridge/intel/i82801gx/Makefile.inc trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h trunk/util/abuild/abuild
Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/lib/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -21,6 +21,7 @@ romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
Modified: trunk/src/lib/ramtest.c ============================================================================== --- trunk/src/lib/ramtest.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/lib/ramtest.c Tue Oct 5 11:07:10 2010 (r5910) @@ -1,4 +1,6 @@ +#include <stdint.h> #include <lib.h> /* Prototypes */ +#include <console/console.h>
static void write_phys(unsigned long addr, u32 value) {
Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/db800/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/norwich/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/rumba/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h"
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,11 +45,11 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/arima/hdama/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -7,7 +7,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -48,7 +48,6 @@
#include <cpu/amd/model_fxx_rev.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h"
Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,11 +27,11 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" +#include <lib.h> #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/broadcom/blast/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,6 @@ #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h"
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -6,7 +6,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/getac/p470/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,24 +26,20 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h"
-#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void);
-#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { u32 gpios;
@@ -87,18 +83,6 @@ outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ }
-#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -55,7 +55,6 @@ #include "southbridge/sis/sis966/sis966_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,6 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -41,10 +41,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -45,10 +45,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -55,7 +55,6 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,11 +49,11 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c"
Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibase/mb899/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h>
#include "superio/winbond/w83627ehg/w83627ehg.h"
@@ -34,21 +35,17 @@ #include <console/console.h> #include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -64,18 +61,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ
Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibm/e325/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/ibm/e326/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -48,10 +48,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/intel/d810e2cb/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d810e2cb/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/d810e2cb/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801bx/i82801bx.h" #include "southbridge/intel/i82801bx/i82801bx_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" @@ -36,6 +35,7 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "gpio.c" +#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,6 +26,7 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h>
#include "superio/smsc/lpc47m15x/lpc47m15x.h"
@@ -34,21 +35,17 @@ #include <console/console.h> #include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-#include "northbridge/intel/i945/udelay.c" - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void enable_smbus(void); + +void setup_ich7_gpios(void) { /* TODO: This is highly board specific and should be moved */ printk(BIOS_DEBUG, " GPIOS..."); @@ -65,18 +62,6 @@ outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ
Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -34,7 +34,6 @@ #include <console/console.h> #include <cpu/x86/bist.h>
-#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "reset.c"
Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit.h"
Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c"
/* tyan does not want the default */ #include "resourcemap.c"
Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c"
/* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c"
Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -91,7 +91,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "lib/ramtest.c"
/* tyan does not want the default */ #include "northbridge/amd/amdk8/resourcemap.c"
Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,13 +27,13 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" +#include <lib.h>
#if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,10 +46,10 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c"
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -21,6 +21,7 @@
#include <stdint.h> #include <string.h> +#include <lib.h> #include <arch/io.h> #include <arch/romcc_io.h> #include <device/pci_def.h> @@ -35,21 +36,17 @@ #include <console/console.h> #include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void);
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) + +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -65,18 +62,6 @@ outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ
Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lanner/em8510/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -30,7 +30,6 @@ #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h"
Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -4,7 +4,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h"
Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -29,7 +29,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -29,7 +29,6 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,7 +49,6 @@
#include <cpu/amd/model_fxx_rev.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h"
Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -56,12 +56,12 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <lib.h>
#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c"
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/newisys/khepri/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/rca/rm4100/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c"
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,24 +28,20 @@ #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> +#include <lib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <cpu/x86/bist.h>
-#if CONFIG_USBDEBUG -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "northbridge/intel/i945/i945.h" +#include "northbridge/intel/i945/raminit.h" +#include "southbridge/intel/i82801gx/i82801gx.h"
-#include "northbridge/intel/i945/udelay.c" +void enable_smbus(void);
-#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) +void setup_ich7_gpios(void) { printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ @@ -61,18 +57,6 @@ outl(0x00010030, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - static void ich7_enable_lpc(void) { // Enable Serial IRQ
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -16,7 +16,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -49,7 +49,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -43,7 +43,7 @@ #include <cpu/x86/lapic.h>
#include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -43,7 +43,7 @@ #include <cpu/x86/lapic.h>
#include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -28,7 +28,7 @@ #include <arch/llshell.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" #include "northbridge/intel/i82830/memory_initialized.c"
Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/traverse/geos/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2735/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h"
Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2850/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2875/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2880/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2881/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -13,7 +13,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2882/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2885/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -14,7 +14,7 @@ #include <pc80/mc146818rtc.h>
#include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -15,7 +15,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h>
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -46,7 +46,7 @@ #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c" #include "pc80/usbdebug_serial.c" #endif -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_10xxx_rev.h>
Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s4880/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -9,7 +9,7 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/tyan/s4882/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -8,7 +8,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h>
#include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c"
Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/epia-cn/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c"
Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/epia-m700/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -33,7 +33,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c"
Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/pc2500e/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c"
Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/via/vt8454c/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/winent/pl6064/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -26,7 +26,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h>
Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/mainboard/wyse/s50/romstage.c Tue Oct 5 11:07:10 2010 (r5910) @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" +#include <lib.h> #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h>
Modified: trunk/src/northbridge/intel/i945/Makefile.inc ============================================================================== --- trunk/src/northbridge/intel/i945/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -20,3 +20,9 @@ driver-y += northbridge.c driver-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +romstage-y += udelay.c +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += errata.c +romstage-y += debug.c
Modified: trunk/src/northbridge/intel/i945/debug.c ============================================================================== --- trunk/src/northbridge/intel/i945/debug.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/debug.c Tue Oct 5 11:07:10 2010 (r5910) @@ -19,11 +19,18 @@ * MA 02110-1301 USA */
+#include <lib.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "i945.h" + #define SMBUS_MEM_DEVICE_START 0x50 #define SMBUS_MEM_DEVICE_END 0x53 #define SMBUS_MEM_DEVICE_INC 1
-static inline void print_pci_devices(void) +void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -42,7 +49,7 @@ } }
-static inline void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned dev) { int i;
@@ -61,7 +68,7 @@ } }
-static inline void dump_pci_devices(void) +void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -78,7 +85,7 @@ } }
-static inline void dump_spd_registers(void) +void dump_spd_registers(void) { unsigned device; device = SMBUS_MEM_DEVICE_START; @@ -103,7 +110,7 @@ } }
-static inline void dump_mem(unsigned start, unsigned end) +void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:");
Modified: trunk/src/northbridge/intel/i945/early_init.c ============================================================================== --- trunk/src/northbridge/intel/i945/early_init.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/early_init.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,10 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> #include "i945.h" #include "pcie_config.c"
-static int i945_silicon_revision(void) +int i945_silicon_revision(void) { return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); } @@ -856,7 +862,7 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); }
-static void i945_early_initialization(void) +void i945_early_initialization(void) { /* Print some chipset specific information */ switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { @@ -879,7 +885,7 @@ RCBA32(0x2010) |= (1 << 10); }
-static void i945_late_initialization(void) +void i945_late_initialization(void) { i945_setup_egress_port();
Modified: trunk/src/northbridge/intel/i945/errata.c ============================================================================== --- trunk/src/northbridge/intel/i945/errata.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/errata.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <stdint.h> +#include "i945.h" #include "raminit.h"
int fixup_i945_errata(void)
Modified: trunk/src/northbridge/intel/i945/i945.h ============================================================================== --- trunk/src/northbridge/intel/i945/i945.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/i945.h Tue Oct 5 11:07:10 2010 (r5910) @@ -333,5 +333,22 @@
static inline void barrier(void) { asm("" ::: "memory"); }
+int i945_silicon_revision(void); +void i945_early_initialization(void); +void i945_late_initialization(void); + +/* provided by southbridge code */ +int smbus_read_byte(unsigned device, unsigned address); + +/* provided by mainboard code */ +void setup_ich7_gpios(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); + #endif #endif
Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/raminit.c Tue Oct 5 11:07:10 2010 (r5910) @@ -17,10 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <pc80/mc146818rtc.h> #include <spd.h> +#include <string.h> +#include <arch/romcc_io.h> #include "raminit.h" #include "i945.h"
@@ -45,6 +48,11 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21)
+static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + static __attribute__((noinline)) void do_ram_command(u32 command) { u32 reg32;
Modified: trunk/src/northbridge/intel/i945/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/raminit.h Tue Oct 5 11:07:10 2010 (r5910) @@ -71,4 +71,6 @@ void sdram_initialize(int boot_path); unsigned long get_top_of_ram(void); int fixup_i945_errata(void); +void udelay(u32 us); + #endif /* RAMINIT_H */
Modified: trunk/src/northbridge/intel/i945/udelay.c ============================================================================== --- trunk/src/northbridge/intel/i945/udelay.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/northbridge/intel/i945/udelay.c Tue Oct 5 11:07:10 2010 (r5910) @@ -18,6 +18,7 @@ */
#include <delay.h> +#include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h>
Modified: trunk/src/pc80/Makefile.inc ============================================================================== --- trunk/src/pc80/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/pc80/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -6,6 +6,7 @@
romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c romstage-$(CONFIG_CACHE_AS_RAM) += serial.c +romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c subdirs-y += vga
$(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)
Modified: trunk/src/southbridge/intel/i82801gx/Makefile.inc ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Makefile.inc Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/Makefile.inc Tue Oct 5 11:07:10 2010 (r5910) @@ -35,3 +35,7 @@
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c + +romstage-y += i82801gx_early_smbus.c +romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c +
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c Tue Oct 5 11:07:10 2010 (r5910) @@ -18,11 +18,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
+#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_def.h> #include "i82801gx.h" #include "i82801gx_smbus.h"
-static void enable_smbus(void) +int smbus_read_byte(unsigned device, unsigned address); + +void enable_smbus(void) { device_t dev;
@@ -52,7 +58,7 @@ print_debug("SMBus controller enabled.\n"); }
-static inline int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smbus.h Tue Oct 5 11:07:10 2010 (r5910) @@ -20,6 +20,8 @@
#include <device/smbus_def.h>
+void enable_smbus(void); + static void smbus_delay(void) { inb(0x80);
Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Mon Oct 4 22:43:55 2010 (r5909) +++ trunk/util/abuild/abuild Tue Oct 5 11:07:10 2010 (r5910) @@ -203,6 +203,7 @@ echo "CONFIG_SCANBUILD_ENABLE=y" >> .config echo "CONFIG_SCANBUILD_REPORT_LOCATION="$TARGET/scan-build-results-tmp"" >> .config fi + echo "CONFIG_USBDEBUG=y" >> .config fi
#yes "" | $MAKE oldconfig -j $cpus obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log
-
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