coreboot June 2009

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[flashrom] r635 - trunk
by svn＠coreboot.org 28 Jun '09

28 Jun '09

Author: uwe Date: 2009-06-28 23:47:57 +0200 (Sun, 28 Jun 2009) New Revision: 635 Modified: trunk/chipset_enable.c trunk/flashrom.c Log: Print the bus type(s) of both chipset and chip in the flashrom output (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-06-28 19:19:25 UTC (rev 634) +++ trunk/chipset_enable.c 2009-06-28 21:47:57 UTC (rev 635) @@ -1059,6 +1059,8 @@ else printf("OK.\n"); } + printf("This chipset supports the following protcols: %s.\n", + flashbuses_to_text(buses_supported)); return ret; } Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-28 19:19:25 UTC (rev 634) +++ trunk/flashrom.c 2009-06-28 21:47:57 UTC (rev 635) @@ -380,8 +380,10 @@ if (!flash || !flash->name) return NULL; - printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n", - flash->vendor, flash->name, flash->total_size, base); + printf("Found chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", + flash->vendor, flash->name, flash->total_size, + flashbuses_to_text(flash->bustype), base); + return flash; }

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[PATCH] flashrom: Fix all remaining bustypes (no more NONSPI in flashchips.c)
by Urja Rannikko 28 Jun '09

28 Jun '09

Fix all NONSPI bustypes in flashchips.c. Also noted as a comment if an FWH/LPC chip supports A/A Mux mode. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- I think we should add a bit in bustypes for A/A Mux so an external programmer can use it if available, any objections? I'll do it if its ok, should it be CHIP_BUSTYPE_AAMUX ? (or _A_A_MUX?) (or _PPMODE?) -- urjaman

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[flashrom] r634 - trunk
by svn＠coreboot.org 28 Jun '09

28 Jun '09

Author: hailfinger Date: 2009-06-28 21:19:25 +0200 (Sun, 28 Jun 2009) New Revision: 634 Modified: trunk/flashchips.c Log: Fix all NONSPI bustypes in flashchips.c. Also noted as a comment if an FWH/LPC chip supports A/A Mux mode. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-28 10:57:58 UTC (rev 633) +++ trunk/flashchips.c 2009-06-28 19:19:25 UTC (rev 634) @@ -58,7 +58,7 @@ { .vendor = "AMD", .name = "Am29F002(N)BB", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F002BB, .total_size = 256, @@ -74,7 +74,7 @@ { .vendor = "AMD", .name = "Am29F002(N)BT", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F002BT, .total_size = 256, @@ -90,7 +90,7 @@ { .vendor = "AMD", .name = "Am29F016D", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F016D, .total_size = 2048, @@ -106,7 +106,7 @@ { .vendor = "AMD", .name = "Am29F040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F040B, .total_size = 512, @@ -122,7 +122,7 @@ { .vendor = "AMD", .name = "Am29F080B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29F080B, .total_size = 1024, @@ -138,7 +138,7 @@ { .vendor = "AMD", .name = "Am29LV040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29LV040B, .total_size = 512, @@ -154,7 +154,7 @@ { .vendor = "AMD", .name = "Am29LV081B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMD_ID, .model_id = AM_29LV081B, .total_size = 1024, @@ -170,7 +170,7 @@ { .vendor = "ASD", .name = "AE49F2008", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ASD_ID, .model_id = ASD_AE49F2008, .total_size = 256, @@ -443,7 +443,7 @@ { .vendor = "Atmel", .name = "AT29C512", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ATMEL_ID, .model_id = AT_29C512, .total_size = 64, @@ -716,7 +716,7 @@ { .vendor = "AMIC", .name = "A29002B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A29002B, .total_size = 256, @@ -732,7 +732,7 @@ { .vendor = "AMIC", .name = "A29002T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, .model_id = AMIC_A29002T, .total_size = 256, @@ -1084,7 +1084,7 @@ { .vendor = "Fujitsu", .name = "MBM29F004BC", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = FUJITSU_ID, .model_id = MBM29F004BC, .total_size = 512, @@ -1100,7 +1100,7 @@ { .vendor = "Fujitsu", .name = "MBM29F004TC", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = FUJITSU_ID, .model_id = MBM29F004TC, .total_size = 512, @@ -1116,7 +1116,7 @@ { .vendor = "Fujitsu", .name = "MBM29F400BC", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = FUJITSU_ID, .model_id = MBM29F400BC, .total_size = 512, @@ -1132,7 +1132,7 @@ { .vendor = "Fujitsu", .name = "MBM29F400TC", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = FUJITSU_ID, .model_id = MBM29F400TC, .total_size = 512, @@ -1388,7 +1388,7 @@ { .vendor = "Macronix", .name = "MX29F002B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = MX_ID, .model_id = MX_29F002B, .total_size = 256, @@ -1404,7 +1404,7 @@ { .vendor = "Macronix", .name = "MX29F002T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = MX_ID, .model_id = MX_29F002T, .total_size = 256, @@ -1420,7 +1420,7 @@ { .vendor = "Macronix", .name = "MX29LV040C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = MX_ID, .model_id = MX_29LV040C, .total_size = 512, @@ -1644,7 +1644,7 @@ { .vendor = "PMC", .name = "Pm39LV010", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_39F010, .total_size = 128, @@ -1660,7 +1660,7 @@ { .vendor = "PMC", .name = "Pm49FL002", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC|CHIP_BUSTYPE_FWH, /* A/A Mux*/ .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_49FL002, .total_size = 256, @@ -1676,7 +1676,7 @@ { .vendor = "PMC", .name = "Pm49FL004", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC|CHIP_BUSTYPE_FWH, /* A/A Mux*/ .manufacture_id = PMC_ID_NOPREFIX, .model_id = PMC_49FL004, .total_size = 512, @@ -1692,7 +1692,7 @@ { .vendor = "Sharp", .name = "LHF00L04", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = SHARP_ID, .model_id = SHARP_LHF00L04, .total_size = 1024, @@ -1820,7 +1820,7 @@ { .vendor = "SST", .name = "SST28SF040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_28SF040, .total_size = 512, @@ -1836,7 +1836,7 @@ { .vendor = "SST", .name = "SST29EE010", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_29EE010, .total_size = 128, @@ -1852,7 +1852,7 @@ { .vendor = "SST", .name = "SST29LE010", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_29LE010, .total_size = 128, @@ -1868,7 +1868,7 @@ { .vendor = "SST", .name = "SST29EE020A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_29EE020A, .total_size = 256, @@ -1884,7 +1884,7 @@ { .vendor = "SST", .name = "SST29LE020", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_29LE020, .total_size = 256, @@ -1900,7 +1900,7 @@ { .vendor = "SST", .name = "SST39SF010A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39SF010, .total_size = 128, @@ -1916,7 +1916,7 @@ { .vendor = "SST", .name = "SST39SF020A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39SF020, .total_size = 256, @@ -1932,7 +1932,7 @@ { .vendor = "SST", .name = "SST39SF040", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39SF040, .total_size = 512, @@ -1948,7 +1948,7 @@ { .vendor = "SST", .name = "SST39VF512", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39VF512, .total_size = 64, @@ -1964,7 +1964,7 @@ { .vendor = "SST", .name = "SST39VF010", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39VF010, .total_size = 128, @@ -1980,7 +1980,7 @@ { .vendor = "SST", .name = "SST39VF020", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39VF020, .total_size = 256, @@ -1996,7 +1996,7 @@ { .vendor = "SST", .name = "SST39VF040", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39VF040, .total_size = 512, @@ -2012,7 +2012,7 @@ { .vendor = "SST", .name = "SST39VF080", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SST_ID, .model_id = SST_39VF080, .total_size = 1024, @@ -2028,7 +2028,7 @@ { .vendor = "SST", .name = "SST49LF002A/B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = SST_ID, .model_id = SST_49LF002A, .total_size = 256, @@ -2044,7 +2044,7 @@ { .vendor = "SST", .name = "SST49LF003A/B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = SST_ID, .model_id = SST_49LF003A, .total_size = 384, @@ -2060,7 +2060,7 @@ { .vendor = "SST", .name = "SST49LF004A/B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = SST_ID, .model_id = SST_49LF004A, .total_size = 512, @@ -2076,7 +2076,7 @@ { .vendor = "SST", .name = "SST49LF004C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = SST_ID, .model_id = SST_49LF004C, .total_size = 512, @@ -2092,7 +2092,7 @@ { .vendor = "SST", .name = "SST49LF008A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = SST_ID, .model_id = SST_49LF008A, .total_size = 1024, @@ -2108,7 +2108,7 @@ { .vendor = "SST", .name = "SST49LF008C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = SST_ID, .model_id = SST_49LF008C, .total_size = 1024, @@ -2124,7 +2124,7 @@ { .vendor = "SST", .name = "SST49LF016C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = SST_ID, .model_id = SST_49LF016C, .total_size = 2048, @@ -2188,7 +2188,7 @@ { .vendor = "SST", .name = "SST49LF040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = SST_ID, .model_id = SST_49LF040B, .total_size = 512, @@ -2204,9 +2204,9 @@ { .vendor = "SST", .name = "SST49LF080A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = SST_ID, - .model_id = SST_49LF080A, + .model_id = SST_49LF080A, .total_size = 1024, .page_size = 4096, .tested = TEST_OK_PREW, @@ -2220,7 +2220,7 @@ { .vendor = "SST", .name = "SST49LF160C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = SST_ID, .model_id = SST_49LF160C, .total_size = 2048, @@ -2396,7 +2396,7 @@ { .vendor = "ST", .name = "M29F002B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29F002B, .total_size = 256, @@ -2412,7 +2412,7 @@ { .vendor = "ST", .name = "M29F002T/NT", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29F002T, .total_size = 256, @@ -2428,7 +2428,7 @@ { .vendor = "ST", .name = "M29F040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29F040B, .total_size = 512, @@ -2444,7 +2444,7 @@ { .vendor = "ST", .name = "M29F400BT", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29F400BT, .total_size = 512, @@ -2460,7 +2460,7 @@ { .vendor = "ST", .name = "M29W010B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29W010B, .total_size = 128, @@ -2476,7 +2476,7 @@ { .vendor = "ST", .name = "M29W040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = ST_ID, .model_id = ST_M29W040B, .total_size = 512, @@ -2492,7 +2492,7 @@ { .vendor = "ST", .name = "M50FLW040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH|CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FLW040A, .total_size = 512, @@ -2508,7 +2508,7 @@ { .vendor = "ST", .name = "M50FLW040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH|CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FLW040B, .total_size = 512, @@ -2524,7 +2524,7 @@ { .vendor = "ST", .name = "M50FLW080A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH|CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FLW080A, .total_size = 1024, @@ -2540,7 +2540,7 @@ { .vendor = "ST", .name = "M50FLW080B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH|CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FLW080B, .total_size = 1024, @@ -2556,7 +2556,7 @@ { .vendor = "ST", .name = "M50FW002", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FW002, .total_size = 256, @@ -2572,7 +2572,7 @@ { .vendor = "ST", .name = "M50FW016", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FW016, .total_size = 2048, @@ -2588,7 +2588,7 @@ { .vendor = "ST", .name = "M50FW040", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FW040, .total_size = 512, @@ -2604,7 +2604,7 @@ { .vendor = "ST", .name = "M50FW080", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50FW080, .total_size = 1024, @@ -2620,7 +2620,7 @@ { .vendor = "ST", .name = "M50LPW116", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, /* A/A Mux */ .manufacture_id = ST_ID, .model_id = ST_M50LPW116, .total_size = 2048, @@ -2636,7 +2636,7 @@ { .vendor = "SyncMOS", .name = "S29C31004T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SYNCMOS_ID, .model_id = S29C31004T, .total_size = 512, @@ -2652,7 +2652,7 @@ { .vendor = "SyncMOS", .name = "S29C51001T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SYNCMOS_ID, .model_id = S29C51001T, .total_size = 128, @@ -2668,7 +2668,7 @@ { .vendor = "SyncMOS", .name = "S29C51002T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SYNCMOS_ID, .model_id = S29C51002T, .total_size = 256, @@ -2684,7 +2684,7 @@ { .vendor = "SyncMOS", .name = "S29C51004T", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = SYNCMOS_ID, .model_id = S29C51004T, .total_size = 512, @@ -2700,7 +2700,7 @@ { .vendor = "TI", .name = "TMS29F002RB", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = TI_OLD_ID, .model_id = TI_TMS29F002RB, .total_size = 256, @@ -2716,7 +2716,7 @@ { .vendor = "TI", .name = "TMS29F002RT", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = TI_OLD_ID, .model_id = TI_TMS29F002RT, .total_size = 256, @@ -2796,7 +2796,7 @@ { .vendor = "Winbond", .name = "W29C011", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C011, .total_size = 128, @@ -2844,7 +2844,7 @@ { .vendor = "Winbond", .name = "W29EE011", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_29C011, .total_size = 128, @@ -2940,7 +2940,7 @@ { .vendor = "Winbond", .name = "W49F002U", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, .model_id = W_49F002U, .total_size = 256,

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build service results for r4377
by coreboot information 28 Jun '09

28 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4377 to the coreboot repository. This caused the following changes: Change Log: Impact: fix vmlinux from 2.6.30 from 2.6.30 (?) the new vmlinux with per_cpu and brk support will have more sections. Elf file type is EXEC (Executable file) Entry point 0x200000 There are 7 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000200000 0xffffffff80200000 0x0000000000200000 0x0000000000e46000 0x0000000000e46000 R E 200000 LOAD 0x0000000001046000 0xffffffff81046000 0x0000000001046000 0x00000000001406e0 0x00000000001406e0 RWE 200000 LOAD 0x0000000001200000 0xffffffffff600000 0x0000000001187000 0x0000000000000888 0x0000000000000888 RWE 200000 LOAD 0x0000000001388000 0xffffffff81188000 0x0000000001188000 0x000000000008a086 0x000000000008a086 RWE 200000 LOAD 0x0000000001600000 0x0000000000000000 0x0000000001213000 0x0000000000015e20 0x0000000000015e20 RWE 200000 LOAD 0x0000000001629000 0xffffffff81229000 0x0000000001229000 0x0000000000000000 0x0000000000208000 RWE 200000 NOTE 0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8 0x0000000000000024 0x0000000000000024 4 Section to Segment mapping: Segment Sections... 00 .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param 01 .data .init.rodata .data.cacheline_aligned .data.read_mostly 02 .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies 03 .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs 04 .data.percpu 05 .bss .brk 06 .notes So need to increase NR_SECTIONS. also fix one typo about phys address mask. Peter says: A similar fix was also implemented by Maciej Pijanka, so let's commit this now, eh. Signed-off-by: Yinghai Lu <yinghai(a)kernel.org> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4377&device=sandpointx3_al… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4377&device=epia-m700&vend… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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mkelfImage patch
by Maciej Pijanka 28 Jun '09

28 Jun '09

Hello attached patch fixes when kernel binary has more than four section with was leading to corrupting memory and mysterious crash few functions later on illegal size for section that came from overwritten memory. best regards Maciej -- Maciej Pijanka, PLD-Linux Developer, Reg Linux user #133161 POE/Perl user

3 3

[v2] r4377 - trunk/util/mkelfImage/linux-i386
by svn＠coreboot.org 28 Jun '09

28 Jun '09

Author: stuge Date: 2009-06-28 17:04:06 +0200 (Sun, 28 Jun 2009) New Revision: 4377 Modified: trunk/util/mkelfImage/linux-i386/mkelf-linux-i386.c Log: Impact: fix vmlinux from 2.6.30 from 2.6.30 (?) the new vmlinux with per_cpu and brk support will have more sections. Elf file type is EXEC (Executable file) Entry point 0x200000 There are 7 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000200000 0xffffffff80200000 0x0000000000200000 0x0000000000e46000 0x0000000000e46000 R E 200000 LOAD 0x0000000001046000 0xffffffff81046000 0x0000000001046000 0x00000000001406e0 0x00000000001406e0 RWE 200000 LOAD 0x0000000001200000 0xffffffffff600000 0x0000000001187000 0x0000000000000888 0x0000000000000888 RWE 200000 LOAD 0x0000000001388000 0xffffffff81188000 0x0000000001188000 0x000000000008a086 0x000000000008a086 RWE 200000 LOAD 0x0000000001600000 0x0000000000000000 0x0000000001213000 0x0000000000015e20 0x0000000000015e20 RWE 200000 LOAD 0x0000000001629000 0xffffffff81229000 0x0000000001229000 0x0000000000000000 0x0000000000208000 RWE 200000 NOTE 0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8 0x0000000000000024 0x0000000000000024 4 Section to Segment mapping: Segment Sections... 00 .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param 01 .data .init.rodata .data.cacheline_aligned .data.read_mostly 02 .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies 03 .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs 04 .data.percpu 05 .bss .brk 06 .notes So need to increase NR_SECTIONS. also fix one typo about phys address mask. Peter says: A similar fix was also implemented by Maciej Pijanka, so let's commit this now, eh. Signed-off-by: Yinghai Lu <yinghai(a)kernel.org> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/mkelfImage/linux-i386/mkelf-linux-i386.c =================================================================== --- trunk/util/mkelfImage/linux-i386/mkelf-linux-i386.c 2009-06-27 16:06:51 UTC (rev 4376) +++ trunk/util/mkelfImage/linux-i386/mkelf-linux-i386.c 2009-06-28 15:04:06 UTC (rev 4377) @@ -157,14 +157,16 @@ return result; } +#define NR_SECTIONS 16 + struct kernel_info { int phdrs; - void *kernel[4]; - size_t filesz[4]; - size_t memsz[4]; - size_t paddr[4]; - size_t vaddr[4]; + void *kernel[NR_SECTIONS]; + size_t filesz[NR_SECTIONS]; + size_t memsz[NR_SECTIONS]; + size_t paddr[NR_SECTIONS]; + size_t vaddr[NR_SECTIONS]; size_t entry; size_t switch_64; char *version; @@ -182,6 +184,8 @@ for(i = 0; i < le16_to_cpu(ehdr->e_phnum); i++) { if (le32_to_cpu(phdr[i].p_type) != PT_LOAD) continue; + if(phdrs == NR_SECTIONS) + die("NR_SECTIONS is too small\n"); info->kernel[phdrs] = kernel_buf + le32_to_cpu(phdr[i].p_offset); info->filesz[phdrs] = le32_to_cpu(phdr[i].p_filesz); info->memsz[phdrs] = le32_to_cpu(phdr[i].p_memsz); @@ -212,10 +216,12 @@ for(i = 0; i < le16_to_cpu(ehdr->e_phnum); i++) { if (le32_to_cpu(phdr[i].p_type) != PT_LOAD) continue; + if(phdrs == NR_SECTIONS) + die("NR_SECTIONS is too small\n"); info->kernel[phdrs] = kernel_buf + le64_to_cpu(phdr[i].p_offset); info->filesz[phdrs] = le64_to_cpu(phdr[i].p_filesz); info->memsz[phdrs] = le64_to_cpu(phdr[i].p_memsz); - info->paddr[phdrs] = le64_to_cpu(phdr[i].p_paddr) & 0xffffff; + info->paddr[phdrs] = le64_to_cpu(phdr[i].p_paddr) & 0xfffffff; info->vaddr[phdrs] = le64_to_cpu(phdr[i].p_vaddr); phdrs++; }

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Patch reviews
by Carl-Daniel Hailfinger 28 Jun '09

28 Jun '09

Hi, I noticed that many people are waiting for reviews/commits of their patches. This can be a frustrating experience, so please let me explain the situation. Writing a patch is a _lot_ easier than reviewing it thoroughly. Even one-liners can have a profound unwanted impact on code flow which is not visible at a first glance. Reviewing a patch is time-consuming. I usually spend at least twice the time reviewing a patch compared to writing it myself. Writing a patch is also much more pleasant than reviewing it. Writing a patch is an act of creation whereas reviewing a patch is about finding flaws. That said, reviewing a patch thoroughly (that also includes reading the code around it, the code it calls and the code it is called from) is a great way to start with development. If you want to get your hands dirty, I recommend looking for unapplied patches and reviewing them. Don't be discouraged if someone else posts a review in the meantime, your review is still valuable. If you find the same things another reviewer has mentioned, still write about them (you did find them as well, you deserve the credit). Write about everything you checked even if it is OK. That shows others what you reviewed and how you worked. If you already know the codebase well, _please_ try to review unapplied patches. Patch reviewers are essential for the success of our project because: - they keep buggy code out - they keep bad design out - they help patch submitters to improve their code - they ensure steadily increasing code quality - they show the patch submitter that someone cared about the patch. If you have unapplied patches in your queue, please reply to them with a small note ("ping" etc.) so reviewers can find them and look at them. Regards, Carl-Daniel -- http://www.hailfinger.org/

10 16

[PATCH] Handle programmer init errors, fix IT87* SPI init
by Carl-Daniel Hailfinger 28 Jun '09

28 Jun '09

Handle programmer init errors and abort. If the programmer didn't initialize correctly, it is pointless to continue. Fix standalone IT87* SPI init to set flashbus to NONE if no IT87* SPI communication is possible. Print the I/O port detected by the IT87* SPI code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c =================================================================== --- flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c (Revision 632) +++ flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c (Arbeitskopie) @@ -83,11 +83,12 @@ tmp |= 1 << 4; sio_write(port, 0x24, tmp); } - printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + printf("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); /* LDN 0x7, reg 0x64/0x65 */ sio_write(port, 0x07, 0x7); flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); + printf("Serial flash port 0x%04x\n", flashport); } exit_conf_mode_ite(port); return flashport; @@ -113,8 +114,11 @@ get_io_perms(); ret = it87spi_common_init(); - if (!ret) + if (!ret) { buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } return ret; } Index: flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c =================================================================== --- flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c (Revision 632) +++ flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c (Arbeitskopie) @@ -692,7 +692,10 @@ if (optind < argc) filename = argv[optind++]; - ret = programmer_init(); + if (programmer_init()) { + fprintf(stderr, "Error: Programmer initialization failed.\n"); + exit(1); + } myusec_calibrate_delay(); -- http://www.hailfinger.org/ Index: flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c =================================================================== --- flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c (Revision 632) +++ flashrom-programmer_init_errorcheck_it87spi_initfix/it87spi.c (Arbeitskopie) @@ -83,11 +83,12 @@ tmp |= 1 << 4; sio_write(port, 0x24, tmp); } - printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + printf("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); /* LDN 0x7, reg 0x64/0x65 */ sio_write(port, 0x07, 0x7); flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); + printf("Serial flash port 0x%04x\n", flashport); } exit_conf_mode_ite(port); return flashport; @@ -113,8 +114,11 @@ get_io_perms(); ret = it87spi_common_init(); - if (!ret) + if (!ret) { buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } return ret; } Index: flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c =================================================================== --- flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c (Revision 632) +++ flashrom-programmer_init_errorcheck_it87spi_initfix/flashrom.c (Arbeitskopie) @@ -692,7 +692,10 @@ if (optind < argc) filename = argv[optind++]; - ret = programmer_init(); + if (programmer_init()) { + fprintf(stderr, "Error: Programmer initialization failed.\n"); + exit(1); + } myusec_calibrate_delay();

2 2

[flashrom] r633 - trunk
by svn＠coreboot.org 28 Jun '09

28 Jun '09

Author: hailfinger Date: 2009-06-28 12:57:58 +0200 (Sun, 28 Jun 2009) New Revision: 633 Modified: trunk/flashrom.c trunk/it87spi.c Log: Handle programmer init errors and abort. If the programmer didn't initialize correctly, it is pointless to continue. Fix standalone IT87* SPI init to set flashbus to NONE if no IT87* SPI communication is possible. Print the I/O port detected by the IT87* SPI code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-25 13:57:31 UTC (rev 632) +++ trunk/flashrom.c 2009-06-28 10:57:58 UTC (rev 633) @@ -692,7 +692,10 @@ if (optind < argc) filename = argv[optind++]; - ret = programmer_init(); + if (programmer_init()) { + fprintf(stderr, "Error: Programmer initialization failed.\n"); + exit(1); + } myusec_calibrate_delay(); Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-25 13:57:31 UTC (rev 632) +++ trunk/it87spi.c 2009-06-28 10:57:58 UTC (rev 633) @@ -83,11 +83,12 @@ tmp |= 1 << 4; sio_write(port, 0x24, tmp); } - printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + printf("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); /* LDN 0x7, reg 0x64/0x65 */ sio_write(port, 0x07, 0x7); flashport = sio_read(port, 0x64) << 8; flashport |= sio_read(port, 0x65); + printf("Serial flash port 0x%04x\n", flashport); } exit_conf_mode_ite(port); return flashport; @@ -113,8 +114,11 @@ get_io_perms(); ret = it87spi_common_init(); - if (!ret) + if (!ret) { buses_supported = CHIP_BUSTYPE_SPI; + } else { + buses_supported = CHIP_BUSTYPE_NONE; + } return ret; }

1 0

found Core i7 PCI devices
by Warren Turkal 28 Jun '09

28 Jun '09

I finally found the i7 devices. It turns out that the bios isn't advertising the existence of their bus, so Linux doesn't scan the bus. See [1] for more info. Here's lspci output for anyone interested: mediakitchen:/home/wt/test# lspci -H1 -M -s ff: ff:00.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers (rev 04) ff:00.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture System Address Decoder (rev 04) ff:02.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 0 (rev 04) ff:02.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 0 (rev 04) ff:03.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller (rev 04) ff:03.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Target Address Decoder (rev 04) ff:03.4 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Test Registers (rev 04) ff:04.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Control Registers (rev 04) ff:04.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Address Registers (rev 04) ff:04.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Rank Registers (rev 04) ff:04.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers (rev 04) ff:05.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Control Registers (rev 04) ff:05.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Address Registers (rev 04) ff:05.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Rank Registers (rev 04) ff:05.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers (rev 04) ff:06.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Control Registers (rev 04) ff:06.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Address Registers (rev 04) ff:06.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Rank Registers (rev 04) ff:06.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers (rev 04) [1]http://thread.gmane.org/gmane.linux.kernel.pci/4894 Thanks, wt

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coreboot June 2009